cuda : improve text-generation and batched decoding performance (#3776)
* cuda : prints wip * cuda : new cublas gemm branch for multi-batch quantized src0 * cuda : add F32 sgemm branch * cuda : fine-tune >= VOLTA params + use MMQ only for small batches * cuda : remove duplicated cuBLAS GEMM code * cuda : add CUDA_USE_TENSOR_CORES and GGML_CUDA_FORCE_MMQ macros * build : add compile option to force use of MMQ kernels
This commit is contained in:
Georgi Gerganov
GitHub
parent
34b2a5e1ee
commit
2f9ec7e271
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@ -82,6 +82,7 @@ set(LLAMA_BLAS_VENDOR "Generic" CACHE STRING "llama: BLAS library vendor")
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option(LLAMA_CUBLAS "llama: use CUDA" OFF)
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#option(LLAMA_CUDA_CUBLAS "llama: use cuBLAS for prompt processing" OFF)
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option(LLAMA_CUDA_FORCE_DMMV "llama: use dmmv instead of mmvq CUDA kernels" OFF)
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option(LLAMA_CUDA_FORCE_MMQ "llama: use mmq kernels instead of cuBLAS" OFF)
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set(LLAMA_CUDA_DMMV_X "32" CACHE STRING "llama: x stride for dmmv CUDA kernels")
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set(LLAMA_CUDA_MMV_Y "1" CACHE STRING "llama: y block size for mmv CUDA kernels")
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option(LLAMA_CUDA_F16 "llama: use 16 bit floats for some calculations" OFF)
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@ -305,6 +306,9 @@ if (LLAMA_CUBLAS)
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if (LLAMA_CUDA_FORCE_DMMV)
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add_compile_definitions(GGML_CUDA_FORCE_DMMV)
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endif()
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if (LLAMA_CUDA_FORCE_MMQ)
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add_compile_definitions(GGML_CUDA_FORCE_MMQ)
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endif()
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add_compile_definitions(GGML_CUDA_DMMV_X=${LLAMA_CUDA_DMMV_X})
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add_compile_definitions(GGML_CUDA_MMV_Y=${LLAMA_CUDA_MMV_Y})
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if (DEFINED LLAMA_CUDA_DMMV_Y)
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@ -405,6 +409,9 @@ if (LLAMA_HIPBLAS)
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if (LLAMA_CUDA_FORCE_DMMV)
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target_compile_definitions(ggml-rocm PRIVATE GGML_CUDA_FORCE_DMMV)
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endif()
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if (LLAMA_CUDA_FORCE_MMQ)
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target_compile_definitions(ggml-rocm PRIVATE GGML_CUDA_FORCE_MMQ)
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endif()
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target_compile_definitions(ggml-rocm PRIVATE GGML_CUDA_DMMV_X=${LLAMA_CUDA_DMMV_X})
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target_compile_definitions(ggml-rocm PRIVATE GGML_CUDA_MMV_Y=${LLAMA_CUDA_MMV_Y})
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target_compile_definitions(ggml-rocm PRIVATE K_QUANTS_PER_ITERATION=${LLAMA_CUDA_KQUANTS_ITER})
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3
Makefile
3
Makefile
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@ -397,6 +397,9 @@ endif # CUDA_DOCKER_ARCH
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ifdef LLAMA_CUDA_FORCE_DMMV
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NVCCFLAGS += -DGGML_CUDA_FORCE_DMMV
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endif # LLAMA_CUDA_FORCE_DMMV
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ifdef LLAMA_CUDA_FORCE_MMQ
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NVCCFLAGS += -DGGML_CUDA_FORCE_MMQ
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endif # LLAMA_CUDA_FORCE_MMQ
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ifdef LLAMA_CUDA_DMMV_X
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NVCCFLAGS += -DGGML_CUDA_DMMV_X=$(LLAMA_CUDA_DMMV_X)
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else
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130
ggml-cuda.cu
130
ggml-cuda.cu
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@ -87,6 +87,24 @@
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#define CC_OFFSET_AMD 1000000
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#define CC_RDNA2 (CC_OFFSET_AMD + 1030)
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// define this if you want to always fallback to MMQ kernels and not use cuBLAS for matrix multiplication
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// on modern hardware, using cuBLAS is recommended as it utilizes F16 tensor cores which are very performant
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// for large computational tasks. the drawback is that this requires some extra amount of VRAM:
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// - 7B quantum model: +100-200 MB
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// - 13B quantum model: +200-400 MB
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//
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//#define GGML_CUDA_FORCE_MMQ
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// TODO: improve this to be correct for more hardware
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// for example, currently fails for GeForce GTX 1660 which is TURING arch (> VOLTA) but does not have tensor cores
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// probably other such cases, and not sure what happens on AMD hardware
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#if !defined(GGML_CUDA_FORCE_MMQ)
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#define CUDA_USE_TENSOR_CORES
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#endif
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// max batch size to use MMQ kernels when tensor cores are available
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#define MMQ_MAX_BATCH_SIZE 32
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#if defined(GGML_USE_HIPBLAS)
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#define __CUDA_ARCH__ 1300
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@ -470,7 +488,6 @@ static int g_device_count = -1;
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static int g_main_device = 0;
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static int g_compute_capabilities[GGML_CUDA_MAX_DEVICES];
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static float g_tensor_split[GGML_CUDA_MAX_DEVICES] = {0};
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static bool g_mul_mat_q = true;
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static void * g_scratch_buffer = nullptr;
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static size_t g_scratch_size = 0; // disabled by default
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@ -3554,9 +3571,15 @@ static __device__ __forceinline__ void mul_mat_q(
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#define MMQ_X_Q4_0_RDNA1 64
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#define MMQ_Y_Q4_0_RDNA1 64
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#define NWARPS_Q4_0_RDNA1 8
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#if defined(CUDA_USE_TENSOR_CORES)
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#define MMQ_X_Q4_0_AMPERE 4
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#define MMQ_Y_Q4_0_AMPERE 32
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#define NWARPS_Q4_0_AMPERE 4
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#else
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#define MMQ_X_Q4_0_AMPERE 64
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#define MMQ_Y_Q4_0_AMPERE 128
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#define NWARPS_Q4_0_AMPERE 4
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#endif
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#define MMQ_X_Q4_0_PASCAL 64
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#define MMQ_Y_Q4_0_PASCAL 64
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#define NWARPS_Q4_0_PASCAL 8
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@ -3615,9 +3638,15 @@ template <bool need_check> static __global__ void
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#define MMQ_X_Q4_1_RDNA1 64
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#define MMQ_Y_Q4_1_RDNA1 64
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#define NWARPS_Q4_1_RDNA1 8
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#if defined(CUDA_USE_TENSOR_CORES)
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#define MMQ_X_Q4_1_AMPERE 4
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#define MMQ_Y_Q4_1_AMPERE 32
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#define NWARPS_Q4_1_AMPERE 4
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#else
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#define MMQ_X_Q4_1_AMPERE 64
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#define MMQ_Y_Q4_1_AMPERE 128
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#define NWARPS_Q4_1_AMPERE 4
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#endif
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#define MMQ_X_Q4_1_PASCAL 64
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#define MMQ_Y_Q4_1_PASCAL 64
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#define NWARPS_Q4_1_PASCAL 8
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@ -3678,9 +3707,15 @@ template <bool need_check> static __global__ void
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#define MMQ_X_Q5_0_RDNA1 64
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#define MMQ_Y_Q5_0_RDNA1 64
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#define NWARPS_Q5_0_RDNA1 8
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#if defined(CUDA_USE_TENSOR_CORES)
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#define MMQ_X_Q5_0_AMPERE 4
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#define MMQ_Y_Q5_0_AMPERE 32
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#define NWARPS_Q5_0_AMPERE 4
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#else
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#define MMQ_X_Q5_0_AMPERE 128
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#define MMQ_Y_Q5_0_AMPERE 64
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#define NWARPS_Q5_0_AMPERE 4
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#endif
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#define MMQ_X_Q5_0_PASCAL 64
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#define MMQ_Y_Q5_0_PASCAL 64
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#define NWARPS_Q5_0_PASCAL 8
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@ -3739,9 +3774,15 @@ template <bool need_check> static __global__ void
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#define MMQ_X_Q5_1_RDNA1 64
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#define MMQ_Y_Q5_1_RDNA1 64
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#define NWARPS_Q5_1_RDNA1 8
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#if defined(CUDA_USE_TENSOR_CORES)
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#define MMQ_X_Q5_1_AMPERE 4
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#define MMQ_Y_Q5_1_AMPERE 32
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#define NWARPS_Q5_1_AMPERE 4
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#else
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#define MMQ_X_Q5_1_AMPERE 128
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#define MMQ_Y_Q5_1_AMPERE 64
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#define NWARPS_Q5_1_AMPERE 4
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#endif
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#define MMQ_X_Q5_1_PASCAL 64
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#define MMQ_Y_Q5_1_PASCAL 64
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#define NWARPS_Q5_1_PASCAL 8
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@ -3800,9 +3841,15 @@ mul_mat_q5_1(
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#define MMQ_X_Q8_0_RDNA1 64
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#define MMQ_Y_Q8_0_RDNA1 64
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#define NWARPS_Q8_0_RDNA1 8
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#if defined(CUDA_USE_TENSOR_CORES)
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#define MMQ_X_Q8_0_AMPERE 4
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#define MMQ_Y_Q8_0_AMPERE 32
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#define NWARPS_Q8_0_AMPERE 4
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#else
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#define MMQ_X_Q8_0_AMPERE 128
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#define MMQ_Y_Q8_0_AMPERE 64
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#define NWARPS_Q8_0_AMPERE 4
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#endif
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#define MMQ_X_Q8_0_PASCAL 64
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#define MMQ_Y_Q8_0_PASCAL 64
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#define NWARPS_Q8_0_PASCAL 8
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@ -3861,9 +3908,15 @@ template <bool need_check> static __global__ void
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#define MMQ_X_Q2_K_RDNA1 128
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#define MMQ_Y_Q2_K_RDNA1 32
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#define NWARPS_Q2_K_RDNA1 8
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#if defined(CUDA_USE_TENSOR_CORES)
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#define MMQ_X_Q2_K_AMPERE 4
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#define MMQ_Y_Q2_K_AMPERE 32
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#define NWARPS_Q2_K_AMPERE 4
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#else
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#define MMQ_X_Q2_K_AMPERE 64
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#define MMQ_Y_Q2_K_AMPERE 128
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#define NWARPS_Q2_K_AMPERE 4
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#endif
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#define MMQ_X_Q2_K_PASCAL 64
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#define MMQ_Y_Q2_K_PASCAL 64
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#define NWARPS_Q2_K_PASCAL 8
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@ -3922,9 +3975,15 @@ mul_mat_q2_K(
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#define MMQ_X_Q3_K_RDNA1 32
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#define MMQ_Y_Q3_K_RDNA1 128
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#define NWARPS_Q3_K_RDNA1 8
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#if defined(CUDA_USE_TENSOR_CORES)
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#define MMQ_X_Q3_K_AMPERE 4
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#define MMQ_Y_Q3_K_AMPERE 32
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#define NWARPS_Q3_K_AMPERE 4
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#else
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#define MMQ_X_Q3_K_AMPERE 128
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#define MMQ_Y_Q3_K_AMPERE 128
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#define NWARPS_Q3_K_AMPERE 4
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#endif
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#define MMQ_X_Q3_K_PASCAL 64
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#define MMQ_Y_Q3_K_PASCAL 64
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#define NWARPS_Q3_K_PASCAL 8
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@ -3985,9 +4044,15 @@ template <bool need_check> static __global__ void
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#define MMQ_X_Q4_K_RDNA1 32
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#define MMQ_Y_Q4_K_RDNA1 64
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#define NWARPS_Q4_K_RDNA1 8
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#if defined(CUDA_USE_TENSOR_CORES)
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#define MMQ_X_Q4_K_AMPERE 4
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#define MMQ_Y_Q4_K_AMPERE 32
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#define NWARPS_Q4_K_AMPERE 4
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#else
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#define MMQ_X_Q4_K_AMPERE 64
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#define MMQ_Y_Q4_K_AMPERE 128
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#define NWARPS_Q4_K_AMPERE 4
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#endif
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#define MMQ_X_Q4_K_PASCAL 64
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#define MMQ_Y_Q4_K_PASCAL 64
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#define NWARPS_Q4_K_PASCAL 8
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@ -4048,9 +4113,15 @@ template <bool need_check> static __global__ void
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#define MMQ_X_Q5_K_RDNA1 32
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#define MMQ_Y_Q5_K_RDNA1 64
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#define NWARPS_Q5_K_RDNA1 8
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#if defined(CUDA_USE_TENSOR_CORES)
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#define MMQ_X_Q5_K_AMPERE 4
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#define MMQ_Y_Q5_K_AMPERE 32
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#define NWARPS_Q5_K_AMPERE 4
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#else
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#define MMQ_X_Q5_K_AMPERE 64
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#define MMQ_Y_Q5_K_AMPERE 128
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#define NWARPS_Q5_K_AMPERE 4
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#endif
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#define MMQ_X_Q5_K_PASCAL 64
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#define MMQ_Y_Q5_K_PASCAL 64
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#define NWARPS_Q5_K_PASCAL 8
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@ -4109,9 +4180,15 @@ mul_mat_q5_K(
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#define MMQ_X_Q6_K_RDNA1 32
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#define MMQ_Y_Q6_K_RDNA1 64
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#define NWARPS_Q6_K_RDNA1 8
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#if defined(CUDA_USE_TENSOR_CORES)
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#define MMQ_X_Q6_K_AMPERE 4
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#define MMQ_Y_Q6_K_AMPERE 32
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#define NWARPS_Q6_K_AMPERE 4
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#else
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#define MMQ_X_Q6_K_AMPERE 64
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#define MMQ_Y_Q6_K_AMPERE 64
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#define NWARPS_Q6_K_AMPERE 4
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#endif
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#define MMQ_X_Q6_K_PASCAL 64
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#define MMQ_Y_Q6_K_PASCAL 64
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#define NWARPS_Q6_K_PASCAL 8
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@ -5663,6 +5740,16 @@ void ggml_init_cublas() {
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CUDA_CHECK(cudaGetDeviceCount(&g_device_count));
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GGML_ASSERT(g_device_count <= GGML_CUDA_MAX_DEVICES);
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int64_t total_vram = 0;
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#if defined(GGML_CUDA_FORCE_MMQ)
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fprintf(stderr, "%s: GGML_CUDA_FORCE_MMQ: yes\n", __func__);
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#else
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fprintf(stderr, "%s: GGML_CUDA_FORCE_MMQ: no\n", __func__);
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#endif
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#if defined(CUDA_USE_TENSOR_CORES)
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fprintf(stderr, "%s: CUDA_USE_TENSOR_CORES: yes\n", __func__);
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#else
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fprintf(stderr, "%s: CUDA_USE_TENSOR_CORES: no\n", __func__);
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#endif
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fprintf(stderr, "%s: found %d " GGML_CUDA_NAME " devices:\n", __func__, g_device_count);
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for (int id = 0; id < g_device_count; ++id) {
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cudaDeviceProp prop;
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@ -6347,7 +6434,7 @@ inline void ggml_cuda_op_mul_mat_cublas(
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cublasSgemm(g_cublas_handles[id], CUBLAS_OP_T, CUBLAS_OP_N,
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row_diff, src1_ncols, ne10,
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&alpha, src0_ddf_i, ne00,
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src1_ddf_i, ne10,
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src1_ddf_i, ne10,
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&beta, dst_dd_i, ldc));
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if (src0_as != 0) {
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@ -7048,9 +7135,10 @@ static void ggml_cuda_mul_mat_vec_nc(const ggml_tensor * src0, const ggml_tensor
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ggml_mul_mat_vec_nc_f16_f32_cuda(src0_ddq, src1_ddf, dst_ddf, ne00, ne01, row_stride_x, ne02, ne12, channel_stride_x, main_stream);
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}
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static void ggml_cuda_mul_mat_mat_batched_cublas(const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst){
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static void ggml_cuda_mul_mat_mat_batched_cublas(const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) {
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GGML_ASSERT(!ggml_is_transposed(src0));
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GGML_ASSERT(!ggml_is_transposed(src1));
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GGML_ASSERT(src0->backend != GGML_BACKEND_GPU_SPLIT);
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GGML_ASSERT(src0->type == GGML_TYPE_F16);
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GGML_ASSERT(src1->type == GGML_TYPE_F32);
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@ -7202,17 +7290,24 @@ static void ggml_cuda_mul_mat_mat_batched_cublas(const ggml_tensor * src0, const
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}
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static void ggml_cuda_mul_mat(const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) {
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bool all_on_device = (src0->backend == GGML_BACKEND_GPU || src0->backend == GGML_BACKEND_GPU_SPLIT) &&
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src1->backend == GGML_BACKEND_GPU && dst->backend == GGML_BACKEND_GPU;
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const bool all_on_device =
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(src0->backend == GGML_BACKEND_GPU) &&
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(src1->backend == GGML_BACKEND_GPU) &&
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( dst->backend == GGML_BACKEND_GPU);
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int64_t min_compute_capability = INT_MAX;
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for (int64_t id = 0; id < g_device_count; ++id) {
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if (min_compute_capability > g_compute_capabilities[id]
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&& g_tensor_split[id] < (id + 1 < g_device_count ? g_tensor_split[id + 1] : 1.0f)) {
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if (min_compute_capability > g_compute_capabilities[id] && g_tensor_split[id] < (id + 1 < g_device_count ? g_tensor_split[id + 1] : 1.0f)) {
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min_compute_capability = g_compute_capabilities[id];
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}
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}
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#ifdef CUDA_USE_TENSOR_CORES
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const bool use_tensor_cores = true;
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#else
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const bool use_tensor_cores = false;
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#endif
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// debug helpers
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//printf("src0: %8d %8d %8d %8d\n", src0->ne[0], src0->ne[1], src0->ne[2], src0->ne[3]);
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//printf(" %8d %8d %8d %8d\n", src0->nb[0], src0->nb[1], src0->nb[2], src0->nb[3]);
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@ -7221,20 +7316,19 @@ static void ggml_cuda_mul_mat(const ggml_tensor * src0, const ggml_tensor * src1
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//printf("src0 is contiguous %d, transposed %d, type = %s, name = %s\n", ggml_is_contiguous(src0), ggml_is_transposed(src0), ggml_type_name(src0->type), src0->name);
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//printf("src1 is contiguous %d, transposed %d, type = %s, name = %s\n", ggml_is_contiguous(src1), ggml_is_transposed(src1), ggml_type_name(src1->type), src1->name);
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if (all_on_device && src0->type == GGML_TYPE_F16 && ggml_is_permuted(src0) && ggml_is_permuted(src1) && src1->ne[1] == 1) {
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if (all_on_device && !use_tensor_cores && src0->type == GGML_TYPE_F16 && ggml_is_permuted(src0) && ggml_is_permuted(src1) && src1->ne[1] == 1) {
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// KQ single-batch
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ggml_cuda_mul_mat_vec_p021(src0, src1, dst);
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} else if (all_on_device && src0->type == GGML_TYPE_F16 && !ggml_is_contiguous(src0) && !ggml_is_transposed(src1) && src1->ne[1] == 1) {
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} else if (all_on_device && !use_tensor_cores && src0->type == GGML_TYPE_F16 && !ggml_is_contiguous(src0) && !ggml_is_transposed(src1) && src1->ne[1] == 1) {
|
||||
// KQV single-batch
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||||
ggml_cuda_mul_mat_vec_nc(src0, src1, dst);
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||||
} else if (all_on_device && src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_F32 && !ggml_is_transposed(src0) && !ggml_is_transposed(src1) && src1->ne[2]*src1->ne[3] > 1) {
|
||||
} else if (all_on_device && src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_F32 && !ggml_is_transposed(src0) && !ggml_is_transposed(src1)) {
|
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// KQ + KQV multi-batch
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ggml_cuda_mul_mat_mat_batched_cublas(src0, src1, dst);
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||||
} else if (src0->type == GGML_TYPE_F32) {
|
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ggml_cuda_op_mul_mat(src0, src1, dst, ggml_cuda_op_mul_mat_cublas, false);
|
||||
} else if (ggml_is_quantized(src0->type) || src0->type == GGML_TYPE_F16) {
|
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if (src1->ne[1] == 1 && src0->ne[0] % GGML_CUDA_DMMV_X == 0) {
|
||||
|
||||
#ifdef GGML_CUDA_FORCE_DMMV
|
||||
const bool use_mul_mat_vec_q = false;
|
||||
#else
|
||||
|
|
@ -7247,7 +7341,15 @@ static void ggml_cuda_mul_mat(const ggml_tensor * src0, const ggml_tensor * src1
|
|||
ggml_cuda_op_mul_mat(src0, src1, dst, ggml_cuda_op_dequantize_mul_mat_vec, false);
|
||||
}
|
||||
} else {
|
||||
if (g_mul_mat_q && ggml_is_quantized(src0->type) && min_compute_capability >= MIN_CC_DP4A) {
|
||||
bool use_mul_mat_q = min_compute_capability >= MIN_CC_DP4A && ggml_is_quantized(src0->type);
|
||||
|
||||
// when tensor cores are available, use them for large batch size
|
||||
// ref: https://github.com/ggerganov/llama.cpp/pull/3776
|
||||
if (use_tensor_cores && min_compute_capability >= CC_VOLTA && src1->ne[1] > MMQ_MAX_BATCH_SIZE) {
|
||||
use_mul_mat_q = false;
|
||||
}
|
||||
|
||||
if (use_mul_mat_q) {
|
||||
ggml_cuda_op_mul_mat(src0, src1, dst, ggml_cuda_op_mul_mat_q, true);
|
||||
} else {
|
||||
ggml_cuda_op_mul_mat(src0, src1, dst, ggml_cuda_op_mul_mat_cublas, false);
|
||||
|
|
@ -7601,10 +7703,6 @@ void ggml_cuda_set_main_device(const int main_device) {
|
|||
}
|
||||
}
|
||||
|
||||
void ggml_cuda_set_mul_mat_q(const bool mul_mat_q) {
|
||||
g_mul_mat_q = mul_mat_q;
|
||||
}
|
||||
|
||||
void ggml_cuda_set_scratch_size(const size_t scratch_size) {
|
||||
// this is a hack to not completely break llama.cpp when using multiple models or contexts simultaneously
|
||||
// it still won't always work as expected, but it's better than nothing
|
||||
|
|
|
|||
|
|
@ -5959,8 +5959,6 @@ static int llama_decode_internal(
|
|||
}
|
||||
}
|
||||
|
||||
ggml_cuda_set_mul_mat_q(cparams.mul_mat_q);
|
||||
|
||||
// HACK: ggml-alloc may change the tensor backend when reusing a parent, so force output to be on the CPU here if needed
|
||||
if (!lctx.embedding.empty()) {
|
||||
embeddings->backend = GGML_BACKEND_CPU;
|
||||
|
|
|
|||
2
llama.h
2
llama.h
|
|
@ -178,7 +178,7 @@ extern "C" {
|
|||
float rope_freq_scale; // RoPE frequency scaling factor, 0 = from model
|
||||
|
||||
// Keep the booleans together to avoid misalignment during copy-by-value.
|
||||
bool mul_mat_q; // if true, use experimental mul_mat_q kernels
|
||||
bool mul_mat_q; // if true, use experimental mul_mat_q kernels (DEPRECATED - always true)
|
||||
bool f16_kv; // use fp16 for KV cache, fp32 otherwise
|
||||
bool logits_all; // the llama_eval() call computes all logits, not just the last one
|
||||
bool embedding; // embedding mode only
|
||||
|
|
|
|||
Loading…
Reference in a new issue