2012-12-06 12:15:58 +01:00
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#ifndef HW_XILINX_H
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#define HW_XILINX_H 1
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2011-08-22 10:15:24 +02:00
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#include "qemu-common.h"
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2013-02-04 11:37:52 +01:00
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#include "qapi/qmp/qerror.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/stream.h"
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2012-10-24 08:43:34 +02:00
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#include "net/net.h"
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2009-05-20 20:16:11 +02:00
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static inline DeviceState *
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2012-10-23 12:30:10 +02:00
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xilinx_intc_create(hwaddr base, qemu_irq irq, int kind_of_intr)
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2009-05-20 20:16:11 +02:00
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{
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DeviceState *dev;
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2012-06-13 06:46:45 +02:00
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dev = qdev_create(NULL, "xlnx.xps-intc");
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2009-07-15 13:43:31 +02:00
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qdev_prop_set_uint32(dev, "kind-of-intr", kind_of_intr);
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2009-10-07 01:15:58 +02:00
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qdev_init_nofail(dev);
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2013-01-20 02:47:33 +01:00
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
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2009-05-20 20:16:11 +02:00
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return dev;
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}
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/* OPB Timer/Counter. */
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static inline DeviceState *
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2012-10-23 12:30:10 +02:00
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xilinx_timer_create(hwaddr base, qemu_irq irq, int oto, int freq)
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2009-05-20 20:16:11 +02:00
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{
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DeviceState *dev;
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2012-06-28 04:52:23 +02:00
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dev = qdev_create(NULL, "xlnx.xps-timer");
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2012-06-13 06:46:43 +02:00
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qdev_prop_set_uint32(dev, "one-timer-only", oto);
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2012-06-29 05:20:46 +02:00
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qdev_prop_set_uint32(dev, "clock-frequency", freq);
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2009-10-07 01:15:58 +02:00
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qdev_init_nofail(dev);
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2013-01-20 02:47:33 +01:00
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
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2009-05-20 20:16:11 +02:00
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return dev;
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}
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/* XPS Ethernet Lite MAC. */
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static inline DeviceState *
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2012-10-23 12:30:10 +02:00
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xilinx_ethlite_create(NICInfo *nd, hwaddr base, qemu_irq irq,
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2009-05-20 20:16:11 +02:00
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int txpingpong, int rxpingpong)
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{
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DeviceState *dev;
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2012-06-13 06:46:47 +02:00
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qemu_check_nic_model(nd, "xlnx.xps-ethernetlite");
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2009-05-20 20:16:11 +02:00
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2012-06-13 06:46:47 +02:00
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dev = qdev_create(NULL, "xlnx.xps-ethernetlite");
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2009-10-21 15:25:38 +02:00
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qdev_set_nic_properties(dev, nd);
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2012-06-13 06:46:46 +02:00
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qdev_prop_set_uint32(dev, "tx-ping-pong", txpingpong);
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qdev_prop_set_uint32(dev, "rx-ping-pong", rxpingpong);
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2009-10-07 01:15:58 +02:00
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qdev_init_nofail(dev);
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2013-01-20 02:47:33 +01:00
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
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2009-05-20 20:16:11 +02:00
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return dev;
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}
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2011-03-14 11:29:19 +01:00
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2013-02-12 02:17:10 +01:00
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static inline void
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2013-04-16 02:28:35 +02:00
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xilinx_axiethernet_init(DeviceState *dev, NICInfo *nd, StreamSlave *ds,
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StreamSlave *cs, hwaddr base, qemu_irq irq, int txmem,
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int rxmem)
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2011-03-14 11:29:19 +01:00
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{
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qdev_set_nic_properties(dev, nd);
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2012-06-13 06:46:48 +02:00
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qdev_prop_set_uint32(dev, "rxmem", rxmem);
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qdev_prop_set_uint32(dev, "txmem", txmem);
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2013-04-16 02:28:35 +02:00
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object_property_set_link(OBJECT(dev), OBJECT(ds),
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2014-01-02 03:48:08 +01:00
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"axistream-connected", &error_abort);
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2013-04-16 02:28:35 +02:00
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object_property_set_link(OBJECT(dev), OBJECT(cs),
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2014-01-02 03:48:08 +01:00
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"axistream-control-connected", &error_abort);
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2011-03-14 11:29:19 +01:00
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qdev_init_nofail(dev);
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2013-01-20 02:47:33 +01:00
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
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2011-03-14 11:29:19 +01:00
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}
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2012-08-10 05:16:11 +02:00
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static inline void
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2013-04-16 02:28:35 +02:00
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xilinx_axidma_init(DeviceState *dev, StreamSlave *ds, StreamSlave *cs,
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hwaddr base, qemu_irq irq, qemu_irq irq2, int freqhz)
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2011-03-14 11:29:19 +01:00
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{
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qdev_prop_set_uint32(dev, "freqhz", freqhz);
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2013-04-16 02:28:35 +02:00
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object_property_set_link(OBJECT(dev), OBJECT(ds),
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2014-01-02 03:48:08 +01:00
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"axistream-connected", &error_abort);
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2013-04-16 02:28:35 +02:00
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object_property_set_link(OBJECT(dev), OBJECT(cs),
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2014-01-02 03:48:08 +01:00
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"axistream-control-connected", &error_abort);
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2011-03-14 11:29:19 +01:00
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qdev_init_nofail(dev);
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2013-01-20 02:47:33 +01:00
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, irq2);
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2011-03-14 11:29:19 +01:00
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}
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2012-12-06 12:15:58 +01:00
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#endif
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