2007-09-16 23:08:06 +02:00
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/*
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2007-05-23 21:58:11 +02:00
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* Motorola ColdFire MCF5206 SoC embedded peripheral emulation.
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*
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* Copyright (c) 2007 CodeSourcery.
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*
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2011-06-26 04:21:35 +02:00
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* This code is licensed under the GPL
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2007-05-23 21:58:11 +02:00
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*/
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2019-08-12 07:23:42 +02:00
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2016-01-26 19:17:23 +01:00
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#include "qemu/osdep.h"
|
hw/m68k: Replace fprintf(stderr, "*\n" with error_report()
Replace a large number of the fprintf(stderr, "*\n" calls with
error_report(). The functions were renamed with these commands and then
compiler issues where manually fixed.
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
Some lines where then manually tweaked to pass checkpatch.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Thomas Huth <huth@tuxfamily.org>
[thuth: Remove "qemu:" prefix from strings]
Signed-off-by: Thomas Huth <thuth@redhat.com>
2017-09-30 02:16:06 +02:00
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#include "qemu/error-report.h"
|
2020-05-26 11:40:52 +02:00
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#include "qemu/log.h"
|
2016-01-19 21:51:44 +01:00
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#include "cpu.h"
|
2019-08-12 07:23:42 +02:00
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#include "hw/irq.h"
|
2013-02-05 17:06:20 +01:00
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#include "hw/m68k/mcf.h"
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2012-12-17 18:20:00 +01:00
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#include "qemu/timer.h"
|
2013-02-04 15:40:22 +01:00
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#include "hw/ptimer.h"
|
2012-12-17 18:20:04 +01:00
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#include "sysemu/sysemu.h"
|
2020-08-19 08:52:01 +02:00
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#include "hw/sysbus.h"
|
2007-05-23 21:58:11 +02:00
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/* General purpose timer module. */
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typedef struct {
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uint16_t tmr;
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uint16_t trr;
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uint16_t tcr;
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uint16_t ter;
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ptimer_state *timer;
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qemu_irq irq;
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int irq_state;
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} m5206_timer_state;
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#define TMR_RST 0x01
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#define TMR_CLK 0x06
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#define TMR_FRR 0x08
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#define TMR_ORI 0x10
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#define TMR_OM 0x20
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#define TMR_CE 0xc0
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#define TER_CAP 0x01
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#define TER_REF 0x02
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static void m5206_timer_update(m5206_timer_state *s)
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{
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if ((s->tmr & TMR_ORI) != 0 && (s->ter & TER_REF))
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qemu_irq_raise(s->irq);
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else
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qemu_irq_lower(s->irq);
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|
}
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static void m5206_timer_reset(m5206_timer_state *s)
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{
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s->tmr = 0;
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s->trr = 0;
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}
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static void m5206_timer_recalibrate(m5206_timer_state *s)
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|
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|
{
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int prescale;
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int mode;
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|
2019-10-21 16:06:00 +02:00
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ptimer_transaction_begin(s->timer);
|
2007-05-23 21:58:11 +02:00
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|
ptimer_stop(s->timer);
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|
2019-10-21 16:06:00 +02:00
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if ((s->tmr & TMR_RST) == 0) {
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|
goto exit;
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|
}
|
2007-05-23 21:58:11 +02:00
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prescale = (s->tmr >> 8) + 1;
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mode = (s->tmr >> 1) & 3;
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if (mode == 2)
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prescale *= 16;
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|
2020-06-11 07:58:07 +02:00
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if (mode == 3 || mode == 0) {
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qemu_log_mask(LOG_UNIMP, "m5206_timer: mode %d not implemented\n",
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mode);
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goto exit;
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}
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if ((s->tmr & TMR_FRR) == 0) {
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qemu_log_mask(LOG_UNIMP,
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"m5206_timer: free running mode not implemented\n");
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goto exit;
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}
|
2007-05-23 21:58:11 +02:00
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/* Assume 66MHz system clock. */
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ptimer_set_freq(s->timer, 66000000 / prescale);
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ptimer_set_limit(s->timer, s->trr, 0);
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ptimer_run(s->timer, 0);
|
2019-10-21 16:06:00 +02:00
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exit:
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ptimer_transaction_commit(s->timer);
|
2007-05-23 21:58:11 +02:00
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}
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static void m5206_timer_trigger(void *opaque)
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{
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m5206_timer_state *s = (m5206_timer_state *)opaque;
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s->ter |= TER_REF;
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m5206_timer_update(s);
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}
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static uint32_t m5206_timer_read(m5206_timer_state *s, uint32_t addr)
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{
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switch (addr) {
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case 0:
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return s->tmr;
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case 4:
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return s->trr;
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case 8:
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return s->tcr;
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case 0xc:
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return s->trr - ptimer_get_count(s->timer);
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case 0x11:
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return s->ter;
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default:
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return 0;
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}
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}
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static void m5206_timer_write(m5206_timer_state *s, uint32_t addr, uint32_t val)
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{
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switch (addr) {
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case 0:
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if ((s->tmr & TMR_RST) != 0 && (val & TMR_RST) == 0) {
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m5206_timer_reset(s);
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}
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s->tmr = val;
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m5206_timer_recalibrate(s);
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break;
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case 4:
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s->trr = val;
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m5206_timer_recalibrate(s);
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break;
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case 8:
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s->tcr = val;
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break;
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case 0xc:
|
2019-10-21 16:06:00 +02:00
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ptimer_transaction_begin(s->timer);
|
2007-05-23 21:58:11 +02:00
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ptimer_set_count(s->timer, val);
|
2019-10-21 16:06:00 +02:00
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ptimer_transaction_commit(s->timer);
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2007-05-23 21:58:11 +02:00
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break;
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case 0x11:
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s->ter &= ~val;
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break;
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default:
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break;
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}
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m5206_timer_update(s);
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}
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static m5206_timer_state *m5206_timer_init(qemu_irq irq)
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{
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m5206_timer_state *s;
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|
2017-10-07 01:49:18 +02:00
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s = g_new0(m5206_timer_state, 1);
|
2019-10-21 16:06:00 +02:00
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s->timer = ptimer_init(m5206_timer_trigger, s, PTIMER_POLICY_DEFAULT);
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2007-05-23 21:58:11 +02:00
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s->irq = irq;
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m5206_timer_reset(s);
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return s;
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}
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/* System Integration Module. */
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typedef struct {
|
2020-08-19 08:52:01 +02:00
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SysBusDevice parent_obj;
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|
2013-01-18 14:10:34 +01:00
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M68kCPU *cpu;
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2011-11-24 14:31:12 +01:00
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MemoryRegion iomem;
|
2007-05-23 21:58:11 +02:00
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m5206_timer_state *timer[2];
|
2007-06-03 13:13:39 +02:00
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void *uart[2];
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2007-05-23 21:58:11 +02:00
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uint8_t scr;
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uint8_t icr[14];
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uint16_t imr; /* 1 == interrupt is masked. */
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uint16_t ipr;
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uint8_t rsr;
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uint8_t swivr;
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uint8_t par;
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/* Include the UART vector registers here. */
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uint8_t uivr[2];
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} m5206_mbar_state;
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|
2020-08-19 08:52:01 +02:00
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#define MCF5206_MBAR(obj) OBJECT_CHECK(m5206_mbar_state, (obj), TYPE_MCF5206_MBAR)
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|
2007-05-23 21:58:11 +02:00
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/* Interrupt controller. */
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static int m5206_find_pending_irq(m5206_mbar_state *s)
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{
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int level;
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int vector;
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uint16_t active;
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int i;
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level = 0;
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vector = 0;
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active = s->ipr & ~s->imr;
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if (!active)
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return 0;
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for (i = 1; i < 14; i++) {
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if (active & (1 << i)) {
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if ((s->icr[i] & 0x1f) > level) {
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level = s->icr[i] & 0x1f;
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vector = i;
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}
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}
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}
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if (level < 4)
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vector = 0;
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return vector;
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}
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static void m5206_mbar_update(m5206_mbar_state *s)
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{
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int irq;
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int vector;
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int level;
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irq = m5206_find_pending_irq(s);
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if (irq) {
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int tmp;
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tmp = s->icr[irq];
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level = (tmp >> 2) & 7;
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if (tmp & 0x80) {
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/* Autovector. */
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vector = 24 + level;
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} else {
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switch (irq) {
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case 8: /* SWT */
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vector = s->swivr;
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break;
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case 12: /* UART1 */
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vector = s->uivr[0];
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break;
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case 13: /* UART2 */
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vector = s->uivr[1];
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break;
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default:
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/* Unknown vector. */
|
2020-05-26 11:40:52 +02:00
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qemu_log_mask(LOG_UNIMP, "%s: Unhandled vector for IRQ %d\n",
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__func__, irq);
|
2007-05-23 21:58:11 +02:00
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vector = 0xf;
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break;
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}
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}
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} else {
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level = 0;
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vector = 0;
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}
|
2013-01-18 14:20:52 +01:00
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m68k_set_irq_level(s->cpu, level, vector);
|
2007-05-23 21:58:11 +02:00
|
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}
|
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static void m5206_mbar_set_irq(void *opaque, int irq, int level)
|
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|
|
{
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|
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
|
|
|
|
if (level) {
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|
|
s->ipr |= 1 << irq;
|
|
|
|
} else {
|
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|
|
s->ipr &= ~(1 << irq);
|
|
|
|
}
|
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|
|
m5206_mbar_update(s);
|
|
|
|
}
|
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|
|
|
|
|
|
/* System Integration Module. */
|
|
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|
|
2020-08-19 08:52:01 +02:00
|
|
|
static void m5206_mbar_reset(DeviceState *dev)
|
2007-05-23 21:58:11 +02:00
|
|
|
{
|
2020-08-19 08:52:01 +02:00
|
|
|
m5206_mbar_state *s = MCF5206_MBAR(dev);
|
|
|
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|
2007-05-23 21:58:11 +02:00
|
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|
s->scr = 0xc0;
|
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|
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s->icr[1] = 0x04;
|
|
|
|
s->icr[2] = 0x08;
|
|
|
|
s->icr[3] = 0x0c;
|
|
|
|
s->icr[4] = 0x10;
|
|
|
|
s->icr[5] = 0x14;
|
|
|
|
s->icr[6] = 0x18;
|
|
|
|
s->icr[7] = 0x1c;
|
|
|
|
s->icr[8] = 0x1c;
|
|
|
|
s->icr[9] = 0x80;
|
|
|
|
s->icr[10] = 0x80;
|
|
|
|
s->icr[11] = 0x80;
|
|
|
|
s->icr[12] = 0x00;
|
|
|
|
s->icr[13] = 0x00;
|
|
|
|
s->imr = 0x3ffe;
|
|
|
|
s->rsr = 0x80;
|
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|
|
s->swivr = 0x0f;
|
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|
|
s->par = 0;
|
|
|
|
}
|
|
|
|
|
2011-11-24 14:31:13 +01:00
|
|
|
static uint64_t m5206_mbar_read(m5206_mbar_state *s,
|
2020-05-26 11:40:51 +02:00
|
|
|
uint16_t offset, unsigned size)
|
2007-05-23 21:58:11 +02:00
|
|
|
{
|
|
|
|
if (offset >= 0x100 && offset < 0x120) {
|
|
|
|
return m5206_timer_read(s->timer[0], offset - 0x100);
|
|
|
|
} else if (offset >= 0x120 && offset < 0x140) {
|
|
|
|
return m5206_timer_read(s->timer[1], offset - 0x120);
|
|
|
|
} else if (offset >= 0x140 && offset < 0x160) {
|
2011-11-24 14:31:13 +01:00
|
|
|
return mcf_uart_read(s->uart[0], offset - 0x140, size);
|
2007-05-23 21:58:11 +02:00
|
|
|
} else if (offset >= 0x180 && offset < 0x1a0) {
|
2011-11-24 14:31:13 +01:00
|
|
|
return mcf_uart_read(s->uart[1], offset - 0x180, size);
|
2007-05-23 21:58:11 +02:00
|
|
|
}
|
|
|
|
switch (offset) {
|
|
|
|
case 0x03: return s->scr;
|
|
|
|
case 0x14 ... 0x20: return s->icr[offset - 0x13];
|
|
|
|
case 0x36: return s->imr;
|
|
|
|
case 0x3a: return s->ipr;
|
|
|
|
case 0x40: return s->rsr;
|
|
|
|
case 0x41: return 0;
|
|
|
|
case 0x42: return s->swivr;
|
|
|
|
case 0x50:
|
|
|
|
/* DRAM mask register. */
|
|
|
|
/* FIXME: currently hardcoded to 128Mb. */
|
|
|
|
{
|
|
|
|
uint32_t mask = ~0;
|
|
|
|
while (mask > ram_size)
|
|
|
|
mask >>= 1;
|
|
|
|
return mask & 0x0ffe0000;
|
|
|
|
}
|
|
|
|
case 0x5c: return 1; /* DRAM bank 1 empty. */
|
|
|
|
case 0xcb: return s->par;
|
|
|
|
case 0x170: return s->uivr[0];
|
|
|
|
case 0x1b0: return s->uivr[1];
|
|
|
|
}
|
2020-05-26 11:40:52 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad MBAR offset 0x%"PRIx16"\n",
|
|
|
|
__func__, offset);
|
2007-05-23 21:58:11 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-05-26 11:40:51 +02:00
|
|
|
static void m5206_mbar_write(m5206_mbar_state *s, uint16_t offset,
|
2011-11-24 14:31:13 +01:00
|
|
|
uint64_t value, unsigned size)
|
2007-05-23 21:58:11 +02:00
|
|
|
{
|
|
|
|
if (offset >= 0x100 && offset < 0x120) {
|
|
|
|
m5206_timer_write(s->timer[0], offset - 0x100, value);
|
|
|
|
return;
|
|
|
|
} else if (offset >= 0x120 && offset < 0x140) {
|
|
|
|
m5206_timer_write(s->timer[1], offset - 0x120, value);
|
|
|
|
return;
|
|
|
|
} else if (offset >= 0x140 && offset < 0x160) {
|
2011-11-24 14:31:13 +01:00
|
|
|
mcf_uart_write(s->uart[0], offset - 0x140, value, size);
|
2007-05-23 21:58:11 +02:00
|
|
|
return;
|
|
|
|
} else if (offset >= 0x180 && offset < 0x1a0) {
|
2011-11-24 14:31:13 +01:00
|
|
|
mcf_uart_write(s->uart[1], offset - 0x180, value, size);
|
2007-05-23 21:58:11 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
switch (offset) {
|
|
|
|
case 0x03:
|
|
|
|
s->scr = value;
|
|
|
|
break;
|
|
|
|
case 0x14 ... 0x20:
|
|
|
|
s->icr[offset - 0x13] = value;
|
|
|
|
m5206_mbar_update(s);
|
|
|
|
break;
|
|
|
|
case 0x36:
|
|
|
|
s->imr = value;
|
|
|
|
m5206_mbar_update(s);
|
|
|
|
break;
|
|
|
|
case 0x40:
|
|
|
|
s->rsr &= ~value;
|
|
|
|
break;
|
|
|
|
case 0x41:
|
|
|
|
/* TODO: implement watchdog. */
|
|
|
|
break;
|
|
|
|
case 0x42:
|
|
|
|
s->swivr = value;
|
|
|
|
break;
|
|
|
|
case 0xcb:
|
|
|
|
s->par = value;
|
|
|
|
break;
|
|
|
|
case 0x170:
|
|
|
|
s->uivr[0] = value;
|
|
|
|
break;
|
|
|
|
case 0x178: case 0x17c: case 0x1c8: case 0x1bc:
|
|
|
|
/* Not implemented: UART Output port bits. */
|
|
|
|
break;
|
|
|
|
case 0x1b0:
|
|
|
|
s->uivr[1] = value;
|
|
|
|
break;
|
|
|
|
default:
|
2020-05-26 11:40:52 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad MBAR offset 0x%"PRIx16"\n",
|
|
|
|
__func__, offset);
|
2007-05-23 21:58:11 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Internal peripherals use a variety of register widths.
|
|
|
|
This lookup table allows a single routine to handle all of them. */
|
2012-12-22 13:59:22 +01:00
|
|
|
static const uint8_t m5206_mbar_width[] =
|
2007-05-23 21:58:11 +02:00
|
|
|
{
|
|
|
|
/* 000-040 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
|
|
|
|
/* 040-080 */ 1, 2, 2, 2, 4, 1, 2, 4, 1, 2, 4, 2, 2, 4, 2, 2,
|
|
|
|
/* 080-0c0 */ 4, 2, 2, 4, 2, 2, 4, 2, 2, 4, 2, 2, 4, 2, 2, 4,
|
|
|
|
/* 0c0-100 */ 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
|
|
/* 100-140 */ 2, 2, 2, 2, 1, 0, 0, 0, 2, 2, 2, 2, 1, 0, 0, 0,
|
|
|
|
/* 140-180 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
|
|
/* 180-1c0 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
|
|
/* 1c0-200 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
|
|
};
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint32_t m5206_mbar_readw(void *opaque, hwaddr offset);
|
|
|
|
static uint32_t m5206_mbar_readl(void *opaque, hwaddr offset);
|
2007-05-23 21:58:11 +02:00
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint32_t m5206_mbar_readb(void *opaque, hwaddr offset)
|
2007-05-23 21:58:11 +02:00
|
|
|
{
|
|
|
|
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
|
|
|
|
offset &= 0x3ff;
|
2012-09-04 19:37:39 +02:00
|
|
|
if (offset >= 0x200) {
|
2020-06-11 07:58:07 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "Bad MBAR read offset 0x%" HWADDR_PRIX,
|
|
|
|
offset);
|
|
|
|
return 0;
|
2007-05-23 21:58:11 +02:00
|
|
|
}
|
|
|
|
if (m5206_mbar_width[offset >> 2] > 1) {
|
|
|
|
uint16_t val;
|
|
|
|
val = m5206_mbar_readw(opaque, offset & ~1);
|
|
|
|
if ((offset & 1) == 0) {
|
|
|
|
val >>= 8;
|
|
|
|
}
|
|
|
|
return val & 0xff;
|
|
|
|
}
|
2011-11-24 14:31:13 +01:00
|
|
|
return m5206_mbar_read(s, offset, 1);
|
2007-05-23 21:58:11 +02:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint32_t m5206_mbar_readw(void *opaque, hwaddr offset)
|
2007-05-23 21:58:11 +02:00
|
|
|
{
|
|
|
|
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
|
|
|
|
int width;
|
|
|
|
offset &= 0x3ff;
|
2012-09-04 19:37:39 +02:00
|
|
|
if (offset >= 0x200) {
|
2020-06-11 07:58:07 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "Bad MBAR read offset 0x%" HWADDR_PRIX,
|
|
|
|
offset);
|
|
|
|
return 0;
|
2007-05-23 21:58:11 +02:00
|
|
|
}
|
|
|
|
width = m5206_mbar_width[offset >> 2];
|
|
|
|
if (width > 2) {
|
|
|
|
uint32_t val;
|
|
|
|
val = m5206_mbar_readl(opaque, offset & ~3);
|
|
|
|
if ((offset & 3) == 0)
|
|
|
|
val >>= 16;
|
|
|
|
return val & 0xffff;
|
|
|
|
} else if (width < 2) {
|
|
|
|
uint16_t val;
|
|
|
|
val = m5206_mbar_readb(opaque, offset) << 8;
|
|
|
|
val |= m5206_mbar_readb(opaque, offset + 1);
|
|
|
|
return val;
|
|
|
|
}
|
2011-11-24 14:31:13 +01:00
|
|
|
return m5206_mbar_read(s, offset, 2);
|
2007-05-23 21:58:11 +02:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint32_t m5206_mbar_readl(void *opaque, hwaddr offset)
|
2007-05-23 21:58:11 +02:00
|
|
|
{
|
|
|
|
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
|
|
|
|
int width;
|
|
|
|
offset &= 0x3ff;
|
2012-09-04 19:37:39 +02:00
|
|
|
if (offset >= 0x200) {
|
2020-06-11 07:58:07 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "Bad MBAR read offset 0x%" HWADDR_PRIX,
|
|
|
|
offset);
|
|
|
|
return 0;
|
2007-05-23 21:58:11 +02:00
|
|
|
}
|
|
|
|
width = m5206_mbar_width[offset >> 2];
|
|
|
|
if (width < 4) {
|
|
|
|
uint32_t val;
|
|
|
|
val = m5206_mbar_readw(opaque, offset) << 16;
|
|
|
|
val |= m5206_mbar_readw(opaque, offset + 2);
|
|
|
|
return val;
|
|
|
|
}
|
2011-11-24 14:31:13 +01:00
|
|
|
return m5206_mbar_read(s, offset, 4);
|
2007-05-23 21:58:11 +02:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void m5206_mbar_writew(void *opaque, hwaddr offset,
|
2007-05-23 21:58:11 +02:00
|
|
|
uint32_t value);
|
2012-10-23 12:30:10 +02:00
|
|
|
static void m5206_mbar_writel(void *opaque, hwaddr offset,
|
2007-05-23 21:58:11 +02:00
|
|
|
uint32_t value);
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void m5206_mbar_writeb(void *opaque, hwaddr offset,
|
2007-05-23 21:58:11 +02:00
|
|
|
uint32_t value)
|
|
|
|
{
|
|
|
|
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
|
|
|
|
int width;
|
|
|
|
offset &= 0x3ff;
|
2012-09-04 19:37:39 +02:00
|
|
|
if (offset >= 0x200) {
|
2020-06-11 07:58:07 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "Bad MBAR write offset 0x%" HWADDR_PRIX,
|
|
|
|
offset);
|
|
|
|
return;
|
2007-05-23 21:58:11 +02:00
|
|
|
}
|
|
|
|
width = m5206_mbar_width[offset >> 2];
|
|
|
|
if (width > 1) {
|
|
|
|
uint32_t tmp;
|
|
|
|
tmp = m5206_mbar_readw(opaque, offset & ~1);
|
|
|
|
if (offset & 1) {
|
|
|
|
tmp = (tmp & 0xff00) | value;
|
|
|
|
} else {
|
|
|
|
tmp = (tmp & 0x00ff) | (value << 8);
|
|
|
|
}
|
|
|
|
m5206_mbar_writew(opaque, offset & ~1, tmp);
|
|
|
|
return;
|
|
|
|
}
|
2011-11-24 14:31:13 +01:00
|
|
|
m5206_mbar_write(s, offset, value, 1);
|
2007-05-23 21:58:11 +02:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void m5206_mbar_writew(void *opaque, hwaddr offset,
|
2007-05-23 21:58:11 +02:00
|
|
|
uint32_t value)
|
|
|
|
{
|
|
|
|
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
|
|
|
|
int width;
|
|
|
|
offset &= 0x3ff;
|
2012-09-04 19:37:39 +02:00
|
|
|
if (offset >= 0x200) {
|
2020-06-11 07:58:07 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "Bad MBAR write offset 0x%" HWADDR_PRIX,
|
|
|
|
offset);
|
|
|
|
return;
|
2007-05-23 21:58:11 +02:00
|
|
|
}
|
|
|
|
width = m5206_mbar_width[offset >> 2];
|
|
|
|
if (width > 2) {
|
|
|
|
uint32_t tmp;
|
|
|
|
tmp = m5206_mbar_readl(opaque, offset & ~3);
|
|
|
|
if (offset & 3) {
|
|
|
|
tmp = (tmp & 0xffff0000) | value;
|
|
|
|
} else {
|
|
|
|
tmp = (tmp & 0x0000ffff) | (value << 16);
|
|
|
|
}
|
|
|
|
m5206_mbar_writel(opaque, offset & ~3, tmp);
|
|
|
|
return;
|
|
|
|
} else if (width < 2) {
|
|
|
|
m5206_mbar_writeb(opaque, offset, value >> 8);
|
|
|
|
m5206_mbar_writeb(opaque, offset + 1, value & 0xff);
|
|
|
|
return;
|
|
|
|
}
|
2011-11-24 14:31:13 +01:00
|
|
|
m5206_mbar_write(s, offset, value, 2);
|
2007-05-23 21:58:11 +02:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void m5206_mbar_writel(void *opaque, hwaddr offset,
|
2007-05-23 21:58:11 +02:00
|
|
|
uint32_t value)
|
|
|
|
{
|
|
|
|
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
|
|
|
|
int width;
|
|
|
|
offset &= 0x3ff;
|
2012-09-04 19:37:39 +02:00
|
|
|
if (offset >= 0x200) {
|
2020-06-11 07:58:07 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "Bad MBAR write offset 0x%" HWADDR_PRIX,
|
|
|
|
offset);
|
|
|
|
return;
|
2007-05-23 21:58:11 +02:00
|
|
|
}
|
|
|
|
width = m5206_mbar_width[offset >> 2];
|
|
|
|
if (width < 4) {
|
|
|
|
m5206_mbar_writew(opaque, offset, value >> 16);
|
|
|
|
m5206_mbar_writew(opaque, offset + 2, value & 0xffff);
|
|
|
|
return;
|
|
|
|
}
|
2011-11-24 14:31:13 +01:00
|
|
|
m5206_mbar_write(s, offset, value, 4);
|
2007-05-23 21:58:11 +02:00
|
|
|
}
|
|
|
|
|
2018-06-15 15:57:13 +02:00
|
|
|
static uint64_t m5206_mbar_readfn(void *opaque, hwaddr addr, unsigned size)
|
|
|
|
{
|
|
|
|
switch (size) {
|
|
|
|
case 1:
|
|
|
|
return m5206_mbar_readb(opaque, addr);
|
|
|
|
case 2:
|
|
|
|
return m5206_mbar_readw(opaque, addr);
|
|
|
|
case 4:
|
|
|
|
return m5206_mbar_readl(opaque, addr);
|
|
|
|
default:
|
|
|
|
g_assert_not_reached();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void m5206_mbar_writefn(void *opaque, hwaddr addr,
|
|
|
|
uint64_t value, unsigned size)
|
|
|
|
{
|
|
|
|
switch (size) {
|
|
|
|
case 1:
|
|
|
|
m5206_mbar_writeb(opaque, addr, value);
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
m5206_mbar_writew(opaque, addr, value);
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
m5206_mbar_writel(opaque, addr, value);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
g_assert_not_reached();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-11-24 14:31:12 +01:00
|
|
|
static const MemoryRegionOps m5206_mbar_ops = {
|
2018-06-15 15:57:13 +02:00
|
|
|
.read = m5206_mbar_readfn,
|
|
|
|
.write = m5206_mbar_writefn,
|
|
|
|
.valid.min_access_size = 1,
|
|
|
|
.valid.max_access_size = 4,
|
2011-11-24 14:31:12 +01:00
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2007-05-23 21:58:11 +02:00
|
|
|
};
|
|
|
|
|
2020-08-19 08:52:01 +02:00
|
|
|
static void mcf5206_mbar_realize(DeviceState *dev, Error **errp)
|
2007-05-23 21:58:11 +02:00
|
|
|
{
|
2020-08-19 08:52:01 +02:00
|
|
|
m5206_mbar_state *s = MCF5206_MBAR(dev);
|
2007-05-23 21:58:11 +02:00
|
|
|
qemu_irq *pic;
|
|
|
|
|
2013-06-06 11:41:28 +02:00
|
|
|
memory_region_init_io(&s->iomem, NULL, &m5206_mbar_ops, s,
|
2011-11-24 14:31:12 +01:00
|
|
|
"mbar", 0x00001000);
|
2020-08-19 08:52:01 +02:00
|
|
|
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
|
2007-05-23 21:58:11 +02:00
|
|
|
|
|
|
|
pic = qemu_allocate_irqs(m5206_mbar_set_irq, s, 14);
|
|
|
|
s->timer[0] = m5206_timer_init(pic[9]);
|
|
|
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s->timer[1] = m5206_timer_init(pic[10]);
|
2018-04-20 16:52:43 +02:00
|
|
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s->uart[0] = mcf_uart_init(pic[12], serial_hd(0));
|
|
|
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s->uart[1] = mcf_uart_init(pic[13], serial_hd(1));
|
2020-08-19 08:52:01 +02:00
|
|
|
s->cpu = M68K_CPU(qemu_get_cpu(0));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mcf5206_mbar_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2007-05-23 21:58:11 +02:00
|
|
|
|
2020-08-19 08:52:01 +02:00
|
|
|
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
|
|
|
|
dc->desc = "MCF5206 system integration module";
|
|
|
|
dc->realize = mcf5206_mbar_realize;
|
|
|
|
dc->reset = m5206_mbar_reset;
|
2007-05-23 21:58:11 +02:00
|
|
|
}
|
2020-08-19 08:52:01 +02:00
|
|
|
|
|
|
|
static const TypeInfo mcf5206_mbar_info = {
|
|
|
|
.name = TYPE_MCF5206_MBAR,
|
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(m5206_mbar_state),
|
|
|
|
.class_init = mcf5206_mbar_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void mcf5206_mbar_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&mcf5206_mbar_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(mcf5206_mbar_register_types)
|