367 lines
11 KiB
C
367 lines
11 KiB
C
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/*
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* Copyright (C) 2014-2016 Broadcom Corporation
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* Copyright (c) 2017 Red Hat, Inc.
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* Written by Prem Mallappa, Eric Auger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/boards.h"
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#include "sysemu/sysemu.h"
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#include "hw/sysbus.h"
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#include "hw/qdev-core.h"
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#include "hw/pci/pci.h"
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#include "exec/address-spaces.h"
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#include "trace.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/arm/smmuv3.h"
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#include "smmuv3-internal.h"
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static void smmuv3_init_regs(SMMUv3State *s)
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{
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/**
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* IDR0: stage1 only, AArch64 only, coherent access, 16b ASID,
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* multi-level stream table
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*/
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s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S1P, 1); /* stage 1 supported */
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s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TTF, 2); /* AArch64 PTW only */
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s->idr[0] = FIELD_DP32(s->idr[0], IDR0, COHACC, 1); /* IO coherent */
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s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ASID16, 1); /* 16-bit ASID */
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s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TTENDIAN, 2); /* little endian */
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s->idr[0] = FIELD_DP32(s->idr[0], IDR0, STALL_MODEL, 1); /* No stall */
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/* terminated transaction will always be aborted/error returned */
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s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TERM_MODEL, 1);
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/* 2-level stream table supported */
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s->idr[0] = FIELD_DP32(s->idr[0], IDR0, STLEVEL, 1);
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s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SIDSIZE, SMMU_IDR1_SIDSIZE);
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s->idr[1] = FIELD_DP32(s->idr[1], IDR1, EVENTQS, SMMU_EVENTQS);
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s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS, SMMU_CMDQS);
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/* 4K and 64K granule support */
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s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1);
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s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1);
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s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 bits */
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s->cmdq.base = deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS);
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s->cmdq.prod = 0;
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s->cmdq.cons = 0;
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s->cmdq.entry_size = sizeof(struct Cmd);
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s->eventq.base = deposit64(s->eventq.base, 0, 5, SMMU_EVENTQS);
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s->eventq.prod = 0;
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s->eventq.cons = 0;
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s->eventq.entry_size = sizeof(struct Evt);
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s->features = 0;
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s->sid_split = 0;
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}
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static MemTxResult smmu_write_mmio(void *opaque, hwaddr offset, uint64_t data,
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unsigned size, MemTxAttrs attrs)
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{
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/* not yet implemented */
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return MEMTX_ERROR;
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}
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static MemTxResult smmu_readll(SMMUv3State *s, hwaddr offset,
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uint64_t *data, MemTxAttrs attrs)
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{
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switch (offset) {
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case A_GERROR_IRQ_CFG0:
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*data = s->gerror_irq_cfg0;
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return MEMTX_OK;
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case A_STRTAB_BASE:
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*data = s->strtab_base;
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return MEMTX_OK;
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case A_CMDQ_BASE:
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*data = s->cmdq.base;
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return MEMTX_OK;
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case A_EVENTQ_BASE:
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*data = s->eventq.base;
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return MEMTX_OK;
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default:
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*data = 0;
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qemu_log_mask(LOG_UNIMP,
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"%s Unexpected 64-bit access to 0x%"PRIx64" (RAZ)\n",
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__func__, offset);
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return MEMTX_OK;
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}
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}
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static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset,
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uint64_t *data, MemTxAttrs attrs)
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{
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switch (offset) {
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case A_IDREGS ... A_IDREGS + 0x1f:
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*data = smmuv3_idreg(offset - A_IDREGS);
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return MEMTX_OK;
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case A_IDR0 ... A_IDR5:
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*data = s->idr[(offset - A_IDR0) / 4];
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return MEMTX_OK;
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case A_IIDR:
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*data = s->iidr;
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return MEMTX_OK;
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case A_CR0:
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*data = s->cr[0];
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return MEMTX_OK;
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case A_CR0ACK:
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*data = s->cr0ack;
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return MEMTX_OK;
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case A_CR1:
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*data = s->cr[1];
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return MEMTX_OK;
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case A_CR2:
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*data = s->cr[2];
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return MEMTX_OK;
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case A_STATUSR:
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*data = s->statusr;
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return MEMTX_OK;
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case A_IRQ_CTRL:
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case A_IRQ_CTRL_ACK:
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*data = s->irq_ctrl;
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return MEMTX_OK;
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case A_GERROR:
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*data = s->gerror;
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return MEMTX_OK;
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case A_GERRORN:
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*data = s->gerrorn;
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return MEMTX_OK;
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case A_GERROR_IRQ_CFG0: /* 64b */
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*data = extract64(s->gerror_irq_cfg0, 0, 32);
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return MEMTX_OK;
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case A_GERROR_IRQ_CFG0 + 4:
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*data = extract64(s->gerror_irq_cfg0, 32, 32);
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return MEMTX_OK;
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case A_GERROR_IRQ_CFG1:
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*data = s->gerror_irq_cfg1;
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return MEMTX_OK;
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case A_GERROR_IRQ_CFG2:
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*data = s->gerror_irq_cfg2;
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return MEMTX_OK;
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case A_STRTAB_BASE: /* 64b */
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*data = extract64(s->strtab_base, 0, 32);
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return MEMTX_OK;
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case A_STRTAB_BASE + 4: /* 64b */
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*data = extract64(s->strtab_base, 32, 32);
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return MEMTX_OK;
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case A_STRTAB_BASE_CFG:
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*data = s->strtab_base_cfg;
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return MEMTX_OK;
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case A_CMDQ_BASE: /* 64b */
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*data = extract64(s->cmdq.base, 0, 32);
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return MEMTX_OK;
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case A_CMDQ_BASE + 4:
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*data = extract64(s->cmdq.base, 32, 32);
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return MEMTX_OK;
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case A_CMDQ_PROD:
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*data = s->cmdq.prod;
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return MEMTX_OK;
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case A_CMDQ_CONS:
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*data = s->cmdq.cons;
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return MEMTX_OK;
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case A_EVENTQ_BASE: /* 64b */
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*data = extract64(s->eventq.base, 0, 32);
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return MEMTX_OK;
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case A_EVENTQ_BASE + 4: /* 64b */
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*data = extract64(s->eventq.base, 32, 32);
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return MEMTX_OK;
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case A_EVENTQ_PROD:
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*data = s->eventq.prod;
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return MEMTX_OK;
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case A_EVENTQ_CONS:
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*data = s->eventq.cons;
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return MEMTX_OK;
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default:
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*data = 0;
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qemu_log_mask(LOG_UNIMP,
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"%s unhandled 32-bit access at 0x%"PRIx64" (RAZ)\n",
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__func__, offset);
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return MEMTX_OK;
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}
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}
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static MemTxResult smmu_read_mmio(void *opaque, hwaddr offset, uint64_t *data,
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unsigned size, MemTxAttrs attrs)
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{
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SMMUState *sys = opaque;
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SMMUv3State *s = ARM_SMMUV3(sys);
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MemTxResult r;
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/* CONSTRAINED UNPREDICTABLE choice to have page0/1 be exact aliases */
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offset &= ~0x10000;
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switch (size) {
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case 8:
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r = smmu_readll(s, offset, data, attrs);
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break;
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case 4:
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r = smmu_readl(s, offset, data, attrs);
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break;
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default:
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r = MEMTX_ERROR;
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break;
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}
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trace_smmuv3_read_mmio(offset, *data, size, r);
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return r;
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}
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static const MemoryRegionOps smmu_mem_ops = {
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.read_with_attrs = smmu_read_mmio,
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.write_with_attrs = smmu_write_mmio,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 8,
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},
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.impl = {
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.min_access_size = 4,
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.max_access_size = 8,
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},
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};
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static void smmu_init_irq(SMMUv3State *s, SysBusDevice *dev)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
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sysbus_init_irq(dev, &s->irq[i]);
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}
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}
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static void smmu_reset(DeviceState *dev)
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{
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SMMUv3State *s = ARM_SMMUV3(dev);
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SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s);
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c->parent_reset(dev);
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smmuv3_init_regs(s);
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}
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static void smmu_realize(DeviceState *d, Error **errp)
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{
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SMMUState *sys = ARM_SMMU(d);
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SMMUv3State *s = ARM_SMMUV3(sys);
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SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s);
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SysBusDevice *dev = SYS_BUS_DEVICE(d);
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Error *local_err = NULL;
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c->parent_realize(d, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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memory_region_init_io(&sys->iomem, OBJECT(s),
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&smmu_mem_ops, sys, TYPE_ARM_SMMUV3, 0x20000);
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sys->mrtypename = TYPE_SMMUV3_IOMMU_MEMORY_REGION;
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sysbus_init_mmio(dev, &sys->iomem);
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smmu_init_irq(s, dev);
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}
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static const VMStateDescription vmstate_smmuv3_queue = {
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.name = "smmuv3_queue",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(base, SMMUQueue),
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VMSTATE_UINT32(prod, SMMUQueue),
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VMSTATE_UINT32(cons, SMMUQueue),
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VMSTATE_UINT8(log2size, SMMUQueue),
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},
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};
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static const VMStateDescription vmstate_smmuv3 = {
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.name = "smmuv3",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(features, SMMUv3State),
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VMSTATE_UINT8(sid_size, SMMUv3State),
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VMSTATE_UINT8(sid_split, SMMUv3State),
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VMSTATE_UINT32_ARRAY(cr, SMMUv3State, 3),
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VMSTATE_UINT32(cr0ack, SMMUv3State),
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VMSTATE_UINT32(statusr, SMMUv3State),
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VMSTATE_UINT32(irq_ctrl, SMMUv3State),
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VMSTATE_UINT32(gerror, SMMUv3State),
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VMSTATE_UINT32(gerrorn, SMMUv3State),
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VMSTATE_UINT64(gerror_irq_cfg0, SMMUv3State),
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VMSTATE_UINT32(gerror_irq_cfg1, SMMUv3State),
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VMSTATE_UINT32(gerror_irq_cfg2, SMMUv3State),
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VMSTATE_UINT64(strtab_base, SMMUv3State),
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VMSTATE_UINT32(strtab_base_cfg, SMMUv3State),
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VMSTATE_UINT64(eventq_irq_cfg0, SMMUv3State),
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VMSTATE_UINT32(eventq_irq_cfg1, SMMUv3State),
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VMSTATE_UINT32(eventq_irq_cfg2, SMMUv3State),
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VMSTATE_STRUCT(cmdq, SMMUv3State, 0, vmstate_smmuv3_queue, SMMUQueue),
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VMSTATE_STRUCT(eventq, SMMUv3State, 0, vmstate_smmuv3_queue, SMMUQueue),
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VMSTATE_END_OF_LIST(),
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},
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};
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static void smmuv3_instance_init(Object *obj)
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{
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/* Nothing much to do here as of now */
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}
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static void smmuv3_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SMMUv3Class *c = ARM_SMMUV3_CLASS(klass);
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dc->vmsd = &vmstate_smmuv3;
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device_class_set_parent_reset(dc, smmu_reset, &c->parent_reset);
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c->parent_realize = dc->realize;
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dc->realize = smmu_realize;
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}
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static void smmuv3_iommu_memory_region_class_init(ObjectClass *klass,
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|
void *data)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
static const TypeInfo smmuv3_type_info = {
|
||
|
|
.name = TYPE_ARM_SMMUV3,
|
||
|
|
.parent = TYPE_ARM_SMMU,
|
||
|
|
.instance_size = sizeof(SMMUv3State),
|
||
|
|
.instance_init = smmuv3_instance_init,
|
||
|
|
.class_size = sizeof(SMMUv3Class),
|
||
|
|
.class_init = smmuv3_class_init,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const TypeInfo smmuv3_iommu_memory_region_info = {
|
||
|
|
.parent = TYPE_IOMMU_MEMORY_REGION,
|
||
|
|
.name = TYPE_SMMUV3_IOMMU_MEMORY_REGION,
|
||
|
|
.class_init = smmuv3_iommu_memory_region_class_init,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void smmuv3_register_types(void)
|
||
|
|
{
|
||
|
|
type_register(&smmuv3_type_info);
|
||
|
|
type_register(&smmuv3_iommu_memory_region_info);
|
||
|
|
}
|
||
|
|
|
||
|
|
type_init(smmuv3_register_types)
|
||
|
|
|