2021-01-29 17:46:14 +01:00
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/*
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* Copyright © 2018, 2021 Oracle and/or its affiliates.
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "hw/remote/proxy.h"
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#include "hw/pci/pci.h"
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#include "qapi/error.h"
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#include "io/channel-util.h"
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#include "hw/qdev-properties.h"
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#include "monitor/monitor.h"
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#include "migration/blocker.h"
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#include "qemu/sockets.h"
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2021-01-29 17:46:16 +01:00
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#include "hw/remote/mpqemu-link.h"
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#include "qemu/error-report.h"
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2021-01-29 17:46:18 +01:00
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#include "hw/remote/proxy-memory-listener.h"
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#include "qom/object.h"
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2021-01-29 17:46:19 +01:00
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#include "qemu/event_notifier.h"
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#include "sysemu/kvm.h"
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#include "util/event_notifier-posix.c"
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2021-01-29 17:46:20 +01:00
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static void probe_pci_info(PCIDevice *dev, Error **errp);
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2021-01-29 17:46:19 +01:00
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static void proxy_intx_update(PCIDevice *pci_dev)
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{
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PCIProxyDev *dev = PCI_PROXY_DEV(pci_dev);
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PCIINTxRoute route;
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int pin = pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
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if (dev->virq != -1) {
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kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &dev->intr, dev->virq);
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dev->virq = -1;
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}
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route = pci_device_route_intx_to_irq(pci_dev, pin);
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dev->virq = route.irq;
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if (dev->virq != -1) {
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kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, &dev->intr,
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&dev->resample, dev->virq);
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}
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}
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static void setup_irqfd(PCIProxyDev *dev)
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{
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PCIDevice *pci_dev = PCI_DEVICE(dev);
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MPQemuMsg msg;
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Error *local_err = NULL;
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event_notifier_init(&dev->intr, 0);
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event_notifier_init(&dev->resample, 0);
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memset(&msg, 0, sizeof(MPQemuMsg));
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msg.cmd = MPQEMU_CMD_SET_IRQFD;
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msg.num_fds = 2;
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msg.fds[0] = event_notifier_get_fd(&dev->intr);
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msg.fds[1] = event_notifier_get_fd(&dev->resample);
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msg.size = 0;
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if (!mpqemu_msg_send(&msg, dev->ioc, &local_err)) {
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error_report_err(local_err);
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}
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dev->virq = -1;
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proxy_intx_update(pci_dev);
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pci_device_set_intx_routing_notifier(pci_dev, proxy_intx_update);
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}
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2021-01-29 17:46:14 +01:00
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static void pci_proxy_dev_realize(PCIDevice *device, Error **errp)
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{
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ERRP_GUARD();
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PCIProxyDev *dev = PCI_PROXY_DEV(device);
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2021-01-29 17:46:20 +01:00
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uint8_t *pci_conf = device->config;
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2021-01-29 17:46:14 +01:00
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int fd;
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if (!dev->fd) {
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error_setg(errp, "fd parameter not specified for %s",
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DEVICE(device)->id);
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return;
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}
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fd = monitor_fd_param(monitor_cur(), dev->fd, errp);
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if (fd == -1) {
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error_prepend(errp, "proxy: unable to parse fd %s: ", dev->fd);
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return;
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}
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if (!fd_is_socket(fd)) {
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error_setg(errp, "proxy: fd %d is not a socket", fd);
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close(fd);
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return;
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}
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dev->ioc = qio_channel_new_fd(fd, errp);
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error_setg(&dev->migration_blocker, "%s does not support migration",
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TYPE_PCI_PROXY_DEV);
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migrate_add_blocker(dev->migration_blocker, errp);
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qemu_mutex_init(&dev->io_mutex);
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qio_channel_set_blocking(dev->ioc, true, NULL);
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2021-01-29 17:46:18 +01:00
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2021-01-29 17:46:20 +01:00
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pci_conf[PCI_LATENCY_TIMER] = 0xff;
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pci_conf[PCI_INTERRUPT_PIN] = 0x01;
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2021-01-29 17:46:18 +01:00
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proxy_memory_listener_configure(&dev->proxy_listener, dev->ioc);
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2021-01-29 17:46:19 +01:00
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setup_irqfd(dev);
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2021-01-29 17:46:20 +01:00
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probe_pci_info(PCI_DEVICE(dev), errp);
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2021-01-29 17:46:14 +01:00
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}
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static void pci_proxy_dev_exit(PCIDevice *pdev)
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{
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PCIProxyDev *dev = PCI_PROXY_DEV(pdev);
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if (dev->ioc) {
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qio_channel_close(dev->ioc, NULL);
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}
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migrate_del_blocker(dev->migration_blocker);
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error_free(dev->migration_blocker);
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2021-01-29 17:46:18 +01:00
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proxy_memory_listener_deconfigure(&dev->proxy_listener);
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2021-01-29 17:46:19 +01:00
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event_notifier_cleanup(&dev->intr);
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event_notifier_cleanup(&dev->resample);
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2021-01-29 17:46:14 +01:00
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}
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2021-01-29 17:46:16 +01:00
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static void config_op_send(PCIProxyDev *pdev, uint32_t addr, uint32_t *val,
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int len, unsigned int op)
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{
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MPQemuMsg msg = { 0 };
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uint64_t ret = -EINVAL;
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Error *local_err = NULL;
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msg.cmd = op;
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msg.data.pci_conf_data.addr = addr;
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msg.data.pci_conf_data.val = (op == MPQEMU_CMD_PCI_CFGWRITE) ? *val : 0;
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msg.data.pci_conf_data.len = len;
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msg.size = sizeof(PciConfDataMsg);
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ret = mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err);
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if (local_err) {
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error_report_err(local_err);
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}
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if (ret == UINT64_MAX) {
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error_report("Failed to perform PCI config %s operation",
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(op == MPQEMU_CMD_PCI_CFGREAD) ? "READ" : "WRITE");
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}
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if (op == MPQEMU_CMD_PCI_CFGREAD) {
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*val = (uint32_t)ret;
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}
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}
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static uint32_t pci_proxy_read_config(PCIDevice *d, uint32_t addr, int len)
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{
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uint32_t val;
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config_op_send(PCI_PROXY_DEV(d), addr, &val, len, MPQEMU_CMD_PCI_CFGREAD);
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return val;
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}
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static void pci_proxy_write_config(PCIDevice *d, uint32_t addr, uint32_t val,
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int len)
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{
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/*
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* Some of the functions access the copy of remote device's PCI config
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* space which is cached in the proxy device. Therefore, maintain
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* it updated.
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*/
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pci_default_write_config(d, addr, val, len);
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config_op_send(PCI_PROXY_DEV(d), addr, &val, len, MPQEMU_CMD_PCI_CFGWRITE);
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}
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2021-01-29 17:46:14 +01:00
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static Property proxy_properties[] = {
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DEFINE_PROP_STRING("fd", PCIProxyDev, fd),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void pci_proxy_dev_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->realize = pci_proxy_dev_realize;
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k->exit = pci_proxy_dev_exit;
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2021-01-29 17:46:16 +01:00
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k->config_read = pci_proxy_read_config;
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k->config_write = pci_proxy_write_config;
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2021-01-29 17:46:14 +01:00
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device_class_set_props(dc, proxy_properties);
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}
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static const TypeInfo pci_proxy_dev_type_info = {
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.name = TYPE_PCI_PROXY_DEV,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIProxyDev),
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.class_init = pci_proxy_dev_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void pci_proxy_dev_register_types(void)
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{
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type_register_static(&pci_proxy_dev_type_info);
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}
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type_init(pci_proxy_dev_register_types)
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2021-01-29 17:46:17 +01:00
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static void send_bar_access_msg(PCIProxyDev *pdev, MemoryRegion *mr,
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bool write, hwaddr addr, uint64_t *val,
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unsigned size, bool memory)
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{
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MPQemuMsg msg = { 0 };
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long ret = -EINVAL;
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Error *local_err = NULL;
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msg.size = sizeof(BarAccessMsg);
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msg.data.bar_access.addr = mr->addr + addr;
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msg.data.bar_access.size = size;
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msg.data.bar_access.memory = memory;
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if (write) {
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msg.cmd = MPQEMU_CMD_BAR_WRITE;
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msg.data.bar_access.val = *val;
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} else {
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msg.cmd = MPQEMU_CMD_BAR_READ;
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}
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ret = mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err);
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if (local_err) {
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error_report_err(local_err);
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}
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if (!write) {
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*val = ret;
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}
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}
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static void proxy_bar_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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ProxyMemoryRegion *pmr = opaque;
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send_bar_access_msg(pmr->dev, &pmr->mr, true, addr, &val, size,
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pmr->memory);
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}
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static uint64_t proxy_bar_read(void *opaque, hwaddr addr, unsigned size)
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{
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ProxyMemoryRegion *pmr = opaque;
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uint64_t val;
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send_bar_access_msg(pmr->dev, &pmr->mr, false, addr, &val, size,
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pmr->memory);
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return val;
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}
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const MemoryRegionOps proxy_mr_ops = {
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.read = proxy_bar_read,
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.write = proxy_bar_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 8,
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},
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};
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2021-01-29 17:46:20 +01:00
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static void probe_pci_info(PCIDevice *dev, Error **errp)
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{
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PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
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uint32_t orig_val, new_val, base_class, val;
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PCIProxyDev *pdev = PCI_PROXY_DEV(dev);
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DeviceClass *dc = DEVICE_CLASS(pc);
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uint8_t type;
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int i, size;
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config_op_send(pdev, PCI_VENDOR_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD);
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pc->vendor_id = (uint16_t)val;
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config_op_send(pdev, PCI_DEVICE_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD);
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pc->device_id = (uint16_t)val;
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config_op_send(pdev, PCI_CLASS_DEVICE, &val, 2, MPQEMU_CMD_PCI_CFGREAD);
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pc->class_id = (uint16_t)val;
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config_op_send(pdev, PCI_SUBSYSTEM_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD);
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pc->subsystem_id = (uint16_t)val;
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base_class = pc->class_id >> 4;
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switch (base_class) {
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case PCI_BASE_CLASS_BRIDGE:
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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break;
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case PCI_BASE_CLASS_STORAGE:
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set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
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break;
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case PCI_BASE_CLASS_NETWORK:
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set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
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break;
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case PCI_BASE_CLASS_INPUT:
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set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
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break;
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case PCI_BASE_CLASS_DISPLAY:
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set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
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break;
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case PCI_BASE_CLASS_PROCESSOR:
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set_bit(DEVICE_CATEGORY_CPU, dc->categories);
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break;
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default:
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set_bit(DEVICE_CATEGORY_MISC, dc->categories);
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break;
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}
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for (i = 0; i < PCI_NUM_REGIONS; i++) {
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config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &orig_val, 4,
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MPQEMU_CMD_PCI_CFGREAD);
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new_val = 0xffffffff;
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config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &new_val, 4,
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MPQEMU_CMD_PCI_CFGWRITE);
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config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &new_val, 4,
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MPQEMU_CMD_PCI_CFGREAD);
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size = (~(new_val & 0xFFFFFFF0)) + 1;
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config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &orig_val, 4,
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MPQEMU_CMD_PCI_CFGWRITE);
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type = (new_val & 0x1) ?
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|
|
PCI_BASE_ADDRESS_SPACE_IO : PCI_BASE_ADDRESS_SPACE_MEMORY;
|
|
|
|
|
|
|
|
if (size) {
|
|
|
|
g_autofree char *name;
|
|
|
|
pdev->region[i].dev = pdev;
|
|
|
|
pdev->region[i].present = true;
|
|
|
|
if (type == PCI_BASE_ADDRESS_SPACE_MEMORY) {
|
|
|
|
pdev->region[i].memory = true;
|
|
|
|
}
|
|
|
|
name = g_strdup_printf("bar-region-%d", i);
|
|
|
|
memory_region_init_io(&pdev->region[i].mr, OBJECT(pdev),
|
|
|
|
&proxy_mr_ops, &pdev->region[i],
|
|
|
|
name, size);
|
|
|
|
pci_register_bar(dev, i, type, &pdev->region[i].mr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|