2018-07-30 16:11:32 +02:00
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/*
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* QEMU PowerPC sPAPR IRQ interface
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*
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* Copyright (c) 2018, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/ppc/spapr.h"
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2018-12-11 23:38:12 +01:00
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#include "hw/ppc/spapr_xive.h"
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2018-07-30 16:11:32 +02:00
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#include "hw/ppc/xics.h"
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2018-07-30 16:11:33 +02:00
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#include "sysemu/kvm.h"
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#include "trace.h"
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2018-07-30 16:11:32 +02:00
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void spapr_irq_msi_init(sPAPRMachineState *spapr, uint32_t nr_msis)
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{
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spapr->irq_map_nr = nr_msis;
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spapr->irq_map = bitmap_new(spapr->irq_map_nr);
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}
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int spapr_irq_msi_alloc(sPAPRMachineState *spapr, uint32_t num, bool align,
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Error **errp)
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{
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int irq;
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/*
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* The 'align_mask' parameter of bitmap_find_next_zero_area()
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* should be one less than a power of 2; 0 means no
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* alignment. Adapt the 'align' value of the former allocator
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* to fit the requirements of bitmap_find_next_zero_area()
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*/
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align -= 1;
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irq = bitmap_find_next_zero_area(spapr->irq_map, spapr->irq_map_nr, 0, num,
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align);
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if (irq == spapr->irq_map_nr) {
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error_setg(errp, "can't find a free %d-IRQ block", num);
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return -1;
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}
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bitmap_set(spapr->irq_map, irq, num);
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return irq + SPAPR_IRQ_MSI;
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}
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void spapr_irq_msi_free(sPAPRMachineState *spapr, int irq, uint32_t num)
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{
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bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num);
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}
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void spapr_irq_msi_reset(sPAPRMachineState *spapr)
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{
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bitmap_clear(spapr->irq_map, 0, spapr->irq_map_nr);
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}
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2018-07-30 16:11:33 +02:00
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/*
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* XICS IRQ backend.
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*/
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static ICSState *spapr_ics_create(sPAPRMachineState *spapr,
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const char *type_ics,
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int nr_irqs, Error **errp)
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{
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Error *local_err = NULL;
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Object *obj;
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obj = object_new(type_ics);
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object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
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object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
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&error_abort);
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object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err);
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if (local_err) {
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goto error;
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}
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object_property_set_bool(obj, true, "realized", &local_err);
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if (local_err) {
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goto error;
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}
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return ICS_BASE(obj);
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error:
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error_propagate(errp, local_err);
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return NULL;
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}
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static void spapr_irq_init_xics(sPAPRMachineState *spapr, Error **errp)
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{
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MachineState *machine = MACHINE(spapr);
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sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
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int nr_irqs = smc->irq->nr_irqs;
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Error *local_err = NULL;
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if (kvm_enabled()) {
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if (machine_kernel_irqchip_allowed(machine) &&
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!xics_kvm_init(spapr, &local_err)) {
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spapr->icp_type = TYPE_KVM_ICP;
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spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs,
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&local_err);
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}
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if (machine_kernel_irqchip_required(machine) && !spapr->ics) {
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error_prepend(&local_err,
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"kernel_irqchip requested but unavailable: ");
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goto error;
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}
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error_free(local_err);
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local_err = NULL;
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}
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if (!spapr->ics) {
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xics_spapr_init(spapr);
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spapr->icp_type = TYPE_ICP;
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spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs,
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&local_err);
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}
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error:
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error_propagate(errp, local_err);
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}
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#define ICS_IRQ_FREE(ics, srcno) \
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(!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
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static int spapr_irq_claim_xics(sPAPRMachineState *spapr, int irq, bool lsi,
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Error **errp)
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{
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ICSState *ics = spapr->ics;
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assert(ics);
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if (!ics_valid_irq(ics, irq)) {
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error_setg(errp, "IRQ %d is invalid", irq);
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return -1;
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}
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if (!ICS_IRQ_FREE(ics, irq - ics->offset)) {
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error_setg(errp, "IRQ %d is not free", irq);
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return -1;
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}
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ics_set_irq_type(ics, irq - ics->offset, lsi);
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return 0;
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}
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static void spapr_irq_free_xics(sPAPRMachineState *spapr, int irq, int num)
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{
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ICSState *ics = spapr->ics;
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uint32_t srcno = irq - ics->offset;
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int i;
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if (ics_valid_irq(ics, irq)) {
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trace_spapr_irq_free(0, irq, num);
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for (i = srcno; i < srcno + num; ++i) {
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if (ICS_IRQ_FREE(ics, i)) {
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trace_spapr_irq_free_warn(0, i);
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}
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memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
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}
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}
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}
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static qemu_irq spapr_qirq_xics(sPAPRMachineState *spapr, int irq)
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{
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ICSState *ics = spapr->ics;
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uint32_t srcno = irq - ics->offset;
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if (ics_valid_irq(ics, irq)) {
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return ics->qirqs[srcno];
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}
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return NULL;
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}
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static void spapr_irq_print_info_xics(sPAPRMachineState *spapr, Monitor *mon)
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{
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CPUState *cs;
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CPU_FOREACH(cs) {
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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icp_pic_print_info(ICP(cpu->intc), mon);
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}
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ics_pic_print_info(spapr->ics, mon);
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}
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2018-12-11 23:38:15 +01:00
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static Object *spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr,
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Object *cpu, Error **errp)
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{
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return icp_create(cpu, spapr->icp_type, XICS_FABRIC(spapr), errp);
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}
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2018-12-11 23:38:16 +01:00
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static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id)
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{
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if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
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CPUState *cs;
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CPU_FOREACH(cs) {
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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icp_resend(ICP(cpu->intc));
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}
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}
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return 0;
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}
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2018-09-11 07:55:03 +02:00
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#define SPAPR_IRQ_XICS_NR_IRQS 0x1000
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2018-09-11 07:55:02 +02:00
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#define SPAPR_IRQ_XICS_NR_MSIS \
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(XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI)
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2018-07-30 16:11:33 +02:00
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sPAPRIrq spapr_irq_xics = {
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2018-09-11 07:55:02 +02:00
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.nr_irqs = SPAPR_IRQ_XICS_NR_IRQS,
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.nr_msis = SPAPR_IRQ_XICS_NR_MSIS,
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2018-07-30 16:11:33 +02:00
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.init = spapr_irq_init_xics,
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.claim = spapr_irq_claim_xics,
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.free = spapr_irq_free_xics,
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.qirq = spapr_qirq_xics,
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.print_info = spapr_irq_print_info_xics,
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2018-12-11 23:38:14 +01:00
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.dt_populate = spapr_dt_xics,
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2018-12-11 23:38:15 +01:00
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.cpu_intc_create = spapr_irq_cpu_intc_create_xics,
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2018-12-11 23:38:16 +01:00
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.post_load = spapr_irq_post_load_xics,
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2018-07-30 16:11:33 +02:00
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};
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2018-12-11 23:38:12 +01:00
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/*
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* XIVE IRQ backend.
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*/
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static void spapr_irq_init_xive(sPAPRMachineState *spapr, Error **errp)
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{
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MachineState *machine = MACHINE(spapr);
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sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
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uint32_t nr_servers = spapr_max_server_number(spapr);
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DeviceState *dev;
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int i;
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/* KVM XIVE device not yet available */
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if (kvm_enabled()) {
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if (machine_kernel_irqchip_required(machine)) {
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error_setg(errp, "kernel_irqchip requested. no KVM XIVE support");
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return;
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}
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}
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dev = qdev_create(NULL, TYPE_SPAPR_XIVE);
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qdev_prop_set_uint32(dev, "nr-irqs", smc->irq->nr_irqs);
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/*
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* 8 XIVE END structures per CPU. One for each available priority
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*/
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qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3);
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qdev_init_nofail(dev);
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spapr->xive = SPAPR_XIVE(dev);
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/* Enable the CPU IPIs */
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for (i = 0; i < nr_servers; ++i) {
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spapr_xive_irq_claim(spapr->xive, SPAPR_IRQ_IPI + i, false);
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}
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2018-12-11 23:38:13 +01:00
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spapr_xive_hcall_init(spapr);
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2018-12-11 23:38:12 +01:00
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}
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static int spapr_irq_claim_xive(sPAPRMachineState *spapr, int irq, bool lsi,
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Error **errp)
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{
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if (!spapr_xive_irq_claim(spapr->xive, irq, lsi)) {
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error_setg(errp, "IRQ %d is invalid", irq);
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return -1;
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}
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return 0;
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}
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static void spapr_irq_free_xive(sPAPRMachineState *spapr, int irq, int num)
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{
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int i;
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for (i = irq; i < irq + num; ++i) {
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spapr_xive_irq_free(spapr->xive, i);
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}
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}
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static qemu_irq spapr_qirq_xive(sPAPRMachineState *spapr, int irq)
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{
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return spapr_xive_qirq(spapr->xive, irq);
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}
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static void spapr_irq_print_info_xive(sPAPRMachineState *spapr,
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Monitor *mon)
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{
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CPUState *cs;
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CPU_FOREACH(cs) {
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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xive_tctx_pic_print_info(XIVE_TCTX(cpu->intc), mon);
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}
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spapr_xive_pic_print_info(spapr->xive, mon);
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}
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2018-12-11 23:38:15 +01:00
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static Object *spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr,
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Object *cpu, Error **errp)
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{
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return xive_tctx_create(cpu, XIVE_ROUTER(spapr->xive), errp);
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}
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2018-12-11 23:38:16 +01:00
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static int spapr_irq_post_load_xive(sPAPRMachineState *spapr, int version_id)
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{
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return 0;
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}
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2018-12-11 23:38:12 +01:00
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/*
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* XIVE uses the full IRQ number space. Set it to 8K to be compatible
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* with XICS.
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*/
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#define SPAPR_IRQ_XIVE_NR_IRQS 0x2000
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#define SPAPR_IRQ_XIVE_NR_MSIS (SPAPR_IRQ_XIVE_NR_IRQS - SPAPR_IRQ_MSI)
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sPAPRIrq spapr_irq_xive = {
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.nr_irqs = SPAPR_IRQ_XIVE_NR_IRQS,
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.nr_msis = SPAPR_IRQ_XIVE_NR_MSIS,
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.init = spapr_irq_init_xive,
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.claim = spapr_irq_claim_xive,
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.free = spapr_irq_free_xive,
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.qirq = spapr_qirq_xive,
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.print_info = spapr_irq_print_info_xive,
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2018-12-11 23:38:14 +01:00
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.dt_populate = spapr_dt_xive,
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2018-12-11 23:38:15 +01:00
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.cpu_intc_create = spapr_irq_cpu_intc_create_xive,
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2018-12-11 23:38:16 +01:00
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.post_load = spapr_irq_post_load_xive,
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2018-12-11 23:38:12 +01:00
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};
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2018-07-30 16:11:33 +02:00
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/*
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* sPAPR IRQ frontend routines for devices
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*/
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2018-12-06 00:22:27 +01:00
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void spapr_irq_init(sPAPRMachineState *spapr, Error **errp)
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{
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sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
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/* Initialize the MSI IRQ allocator. */
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if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
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spapr_irq_msi_init(spapr, smc->irq->nr_msis);
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}
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smc->irq->init(spapr, errp);
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}
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2018-07-30 16:11:33 +02:00
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int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp)
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{
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sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
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return smc->irq->claim(spapr, irq, lsi, errp);
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}
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void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num)
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{
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sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
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smc->irq->free(spapr, irq, num);
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}
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qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq)
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{
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sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
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return smc->irq->qirq(spapr, irq);
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}
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2018-12-11 23:38:16 +01:00
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int spapr_irq_post_load(sPAPRMachineState *spapr, int version_id)
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{
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sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
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return smc->irq->post_load(spapr, version_id);
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}
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2018-07-30 16:11:33 +02:00
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/*
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* XICS legacy routines - to deprecate one day
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*/
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static int ics_find_free_block(ICSState *ics, int num, int alignnum)
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{
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int first, i;
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for (first = 0; first < ics->nr_irqs; first += alignnum) {
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if (num > (ics->nr_irqs - first)) {
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return -1;
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}
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for (i = first; i < first + num; ++i) {
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if (!ICS_IRQ_FREE(ics, i)) {
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break;
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}
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}
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if (i == (first + num)) {
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return first;
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}
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}
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return -1;
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}
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int spapr_irq_find(sPAPRMachineState *spapr, int num, bool align, Error **errp)
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{
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ICSState *ics = spapr->ics;
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int first = -1;
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assert(ics);
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/*
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* MSIMesage::data is used for storing VIRQ so
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* it has to be aligned to num to support multiple
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* MSI vectors. MSI-X is not affected by this.
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* The hint is used for the first IRQ, the rest should
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* be allocated continuously.
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*/
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if (align) {
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assert((num == 1) || (num == 2) || (num == 4) ||
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(num == 8) || (num == 16) || (num == 32));
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first = ics_find_free_block(ics, num, num);
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} else {
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first = ics_find_free_block(ics, num, 1);
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}
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if (first < 0) {
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error_setg(errp, "can't find a free %d-IRQ block", num);
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return -1;
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}
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return first + ics->offset;
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}
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2018-09-11 07:55:03 +02:00
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#define SPAPR_IRQ_XICS_LEGACY_NR_IRQS 0x400
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sPAPRIrq spapr_irq_xics_legacy = {
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.nr_irqs = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
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.nr_msis = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
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.init = spapr_irq_init_xics,
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.claim = spapr_irq_claim_xics,
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.free = spapr_irq_free_xics,
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.qirq = spapr_qirq_xics,
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.print_info = spapr_irq_print_info_xics,
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2018-12-11 23:38:14 +01:00
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.dt_populate = spapr_dt_xics,
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2018-12-11 23:38:15 +01:00
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.cpu_intc_create = spapr_irq_cpu_intc_create_xics,
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2018-12-11 23:38:16 +01:00
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.post_load = spapr_irq_post_load_xics,
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2018-09-11 07:55:03 +02:00
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};
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