2013-04-25 16:05:25 +02:00
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QEMU<->ACPI BIOS CPU hotplug interface
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--------------------------------------
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QEMU supports CPU hotplug via ACPI. This document
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describes the interface between QEMU and the ACPI BIOS.
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2016-05-02 11:42:59 +02:00
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ACPI BIOS GPE.2 handler is dedicated for notifying OS about CPU hot-add
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and hot-remove events.
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2013-04-25 16:05:25 +02:00
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2016-05-02 11:42:59 +02:00
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============================================
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Legacy ACPI CPU hotplug interface registers:
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--------------------------------------------
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2014-01-09 17:36:32 +01:00
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CPU present bitmap for:
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ICH9-LPC (IO port 0x0cd8-0xcf7, 1-byte access)
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PIIX-PM (IO port 0xaf00-0xaf1f, 1-byte access)
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2016-05-02 11:42:59 +02:00
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One bit per CPU. Bit position reflects corresponding CPU APIC ID. Read-only.
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The first DWORD in bitmap is used in write mode to switch from legacy
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to new CPU hotplug interface, write 0 into it to do switch.
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2013-04-25 16:05:25 +02:00
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---------------------------------------------------------------
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2016-05-02 11:42:59 +02:00
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QEMU sets corresponding CPU bit on hot-add event and issues SCI
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with GPE.2 event set. CPU present map is read by ACPI BIOS GPE.2 handler
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to notify OS about CPU hot-add events. CPU hot-remove isn't supported.
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=====================================
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ACPI CPU hotplug interface registers:
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-------------------------------------
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Register block base address:
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ICH9-LPC IO port 0x0cd8
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PIIX-PM IO port 0xaf00
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Register block size:
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ACPI_CPU_HOTPLUG_REG_LEN = 12
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2019-12-09 14:08:57 +01:00
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All accesses to registers described below, imply little-endian byte order.
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Reserved resisters behavior:
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- write accesses are ignored
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- read accesses return all bits set to 0.
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The last stored value in 'CPU selector' must refer to a possible CPU, otherwise
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- reads from any register return 0
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- writes to any other register are ignored until valid value is stored into it
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On QEMU start, 'CPU selector' is initialized to a valid value, on reset it
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keeps the current value.
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2016-05-02 11:42:59 +02:00
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read access:
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offset:
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[0x0-0x3] reserved
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[0x4] CPU device status fields: (1 byte access)
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bits:
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0: Device is enabled and may be used by guest
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1: Device insert event, used to distinguish device for which
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no device check event to OSPM was issued.
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It's valid only when bit 0 is set.
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2: Device remove event, used to distinguish device for which
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no device eject request to OSPM was issued.
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3-7: reserved and should be ignored by OSPM
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[0x5-0x7] reserved
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[0x8] Command data: (DWORD access)
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in case of error or unsupported command reads is 0xFFFFFFFF
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current 'Command field' value:
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0: returns PXM value corresponding to device
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write access:
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offset:
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[0x0-0x3] CPU selector: (DWORD access)
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selects active CPU device. All following accesses to other
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registers will read/store data from/to selected CPU.
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[0x4] CPU device control fields: (1 byte access)
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bits:
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0: reserved, OSPM must clear it before writing to register.
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1: if set to 1 clears device insert event, set by OSPM
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after it has emitted device check event for the
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selected CPU device
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2: if set to 1 clears device remove event, set by OSPM
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after it has emitted device eject request for the
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selected CPU device
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3: if set to 1 initiates device eject, set by OSPM when it
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triggers CPU device removal and calls _EJ0 method
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4-7: reserved, OSPM must clear them before writing to register
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[0x5] Command field: (1 byte access)
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value:
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0: selects a CPU device with inserting/removing events and
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following reads from 'Command data' register return
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selected CPU (CPU selector value). If no CPU with events
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found, the current CPU selector doesn't change and
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corresponding insert/remove event flags are not set.
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1: following writes to 'Command data' register set OST event
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register in QEMU
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2: following writes to 'Command data' register set OST status
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register in QEMU
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other values: reserved
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[0x6-0x7] reserved
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[0x8] Command data: (DWORD access)
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current 'Command field' value:
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0: OSPM reads value of CPU selector
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1: stores value into OST event register
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2: stores value into OST status register, triggers
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ACPI_DEVICE_OST QMP event from QEMU to external applications
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with current values of OST event and status registers.
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other values: reserved
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