2006-10-22 02:18:54 +02:00
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/*
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* m68k op helpers
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2007-09-16 23:08:06 +02:00
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*
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2007-05-23 21:58:11 +02:00
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* Copyright (c) 2006-2007 CodeSourcery
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2006-10-22 02:18:54 +02:00
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* Written by Paul Brook
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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2009-07-16 22:47:01 +02:00
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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2006-10-22 02:18:54 +02:00
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*/
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2016-01-26 19:17:23 +01:00
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#include "qemu/osdep.h"
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2006-10-22 02:18:54 +02:00
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#include "cpu.h"
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2016-03-15 13:18:37 +01:00
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#include "exec/exec-all.h"
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2012-12-17 18:19:49 +01:00
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#include "exec/gdbstub.h"
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2006-10-22 02:18:54 +02:00
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2014-04-08 07:31:41 +02:00
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#include "exec/helper-proto.h"
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2008-05-25 00:29:16 +02:00
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#define SIGNBIT (1u << 31)
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2012-04-15 03:30:10 +02:00
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/* Sort alphabetically, except for "any". */
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static gint m68k_cpu_list_compare(gconstpointer a, gconstpointer b)
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2009-05-09 22:21:39 +02:00
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{
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2012-04-15 03:30:10 +02:00
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ObjectClass *class_a = (ObjectClass *)a;
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ObjectClass *class_b = (ObjectClass *)b;
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const char *name_a, *name_b;
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name_a = object_class_get_name(class_a);
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name_b = object_class_get_name(class_b);
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2013-01-27 20:16:17 +01:00
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if (strcmp(name_a, "any-" TYPE_M68K_CPU) == 0) {
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2012-04-15 03:30:10 +02:00
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return 1;
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2013-01-27 20:16:17 +01:00
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} else if (strcmp(name_b, "any-" TYPE_M68K_CPU) == 0) {
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2012-04-15 03:30:10 +02:00
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return -1;
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} else {
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return strcasecmp(name_a, name_b);
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2009-05-09 22:21:39 +02:00
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}
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}
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2012-04-15 03:30:10 +02:00
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static void m68k_cpu_list_entry(gpointer data, gpointer user_data)
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{
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ObjectClass *c = data;
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2012-12-16 02:17:02 +01:00
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CPUListState *s = user_data;
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2013-01-27 20:16:17 +01:00
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const char *typename;
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char *name;
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2012-04-15 03:30:10 +02:00
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2013-01-27 20:16:17 +01:00
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typename = object_class_get_name(c);
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name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_M68K_CPU));
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2012-04-15 03:30:10 +02:00
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(*s->cpu_fprintf)(s->file, "%s\n",
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2013-01-27 20:16:17 +01:00
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name);
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g_free(name);
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2012-04-15 03:30:10 +02:00
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}
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void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf)
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{
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2012-12-16 02:17:02 +01:00
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CPUListState s = {
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2012-04-15 03:30:10 +02:00
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.file = f,
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.cpu_fprintf = cpu_fprintf,
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};
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GSList *list;
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list = object_class_get_list(TYPE_M68K_CPU, false);
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list = g_slist_sort(list, m68k_cpu_list_compare);
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g_slist_foreach(list, m68k_cpu_list_entry, &s);
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g_slist_free(list);
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}
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2012-03-14 01:38:22 +01:00
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static int fpu_gdb_get_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
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2008-10-11 19:55:29 +02:00
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{
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if (n < 8) {
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stfq_p(mem_buf, env->fregs[n]);
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return 8;
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}
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if (n < 11) {
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/* FP control registers (not implemented) */
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memset(mem_buf, 0, 4);
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return 4;
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}
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return 0;
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}
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2012-03-14 01:38:22 +01:00
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static int fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
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2008-10-11 19:55:29 +02:00
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{
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if (n < 8) {
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env->fregs[n] = ldfq_p(mem_buf);
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return 8;
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}
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if (n < 11) {
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/* FP control registers (not implemented) */
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return 4;
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}
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return 0;
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}
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2013-01-18 14:03:58 +01:00
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M68kCPU *cpu_m68k_init(const char *cpu_model)
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2007-11-10 16:15:54 +01:00
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{
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2012-04-15 00:35:50 +02:00
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M68kCPU *cpu;
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2007-11-10 16:15:54 +01:00
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CPUM68KState *env;
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2013-01-21 17:50:15 +01:00
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ObjectClass *oc;
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2007-11-10 16:15:54 +01:00
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2013-01-21 17:50:15 +01:00
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oc = cpu_class_by_name(TYPE_M68K_CPU, cpu_model);
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if (oc == NULL) {
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2012-04-15 03:30:10 +02:00
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return NULL;
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}
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2013-01-21 17:50:15 +01:00
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cpu = M68K_CPU(object_new(object_class_get_name(oc)));
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2012-04-15 00:35:50 +02:00
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env = &cpu->env;
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2007-12-09 03:22:57 +01:00
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2012-04-15 03:30:10 +02:00
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register_m68k_insns(env);
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2013-01-05 15:15:30 +01:00
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object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
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2013-01-18 14:03:58 +01:00
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return cpu;
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2013-01-05 15:15:30 +01:00
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}
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void m68k_cpu_init_gdb(M68kCPU *cpu)
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{
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2013-06-28 21:27:39 +02:00
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CPUState *cs = CPU(cpu);
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2013-01-05 15:15:30 +01:00
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CPUM68KState *env = &cpu->env;
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2012-04-15 03:30:10 +02:00
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if (m68k_feature(env, M68K_FEATURE_CF_FPU)) {
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2013-06-28 21:27:39 +02:00
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gdb_register_coprocessor(cs, fpu_gdb_get_reg, fpu_gdb_set_reg,
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2012-04-15 03:30:10 +02:00
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11, "cf-fp.xml", 18);
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2007-11-10 16:15:54 +01:00
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}
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2012-04-15 03:30:10 +02:00
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/* TODO: Add [E]MAC registers. */
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2007-11-10 16:15:54 +01:00
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}
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2007-05-26 18:52:21 +02:00
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2008-05-25 00:29:16 +02:00
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void HELPER(movec)(CPUM68KState *env, uint32_t reg, uint32_t val)
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2007-05-23 21:58:11 +02:00
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{
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2013-09-03 17:38:47 +02:00
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M68kCPU *cpu = m68k_env_get_cpu(env);
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2007-05-23 21:58:11 +02:00
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switch (reg) {
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case 0x02: /* CACR */
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2007-06-03 13:13:39 +02:00
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env->cacr = val;
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m68k_switch_sp(env);
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break;
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case 0x04: case 0x05: case 0x06: case 0x07: /* ACR[0-3] */
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/* TODO: Implement Access Control Registers. */
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2007-05-23 21:58:11 +02:00
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break;
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case 0x801: /* VBR */
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env->vbr = val;
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break;
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/* TODO: Implement control registers. */
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default:
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2013-09-03 17:38:47 +02:00
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cpu_abort(CPU(cpu), "Unimplemented control register write 0x%x = 0x%x\n",
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2007-05-23 21:58:11 +02:00
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reg, val);
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}
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}
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2008-05-25 00:29:16 +02:00
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void HELPER(set_macsr)(CPUM68KState *env, uint32_t val)
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2007-05-29 16:57:59 +02:00
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{
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uint32_t acc;
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int8_t exthigh;
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uint8_t extlow;
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uint64_t regval;
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int i;
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if ((env->macsr ^ val) & (MACSR_FI | MACSR_SU)) {
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for (i = 0; i < 4; i++) {
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regval = env->macc[i];
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exthigh = regval >> 40;
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if (env->macsr & MACSR_FI) {
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acc = regval >> 8;
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extlow = regval;
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} else {
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acc = regval;
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extlow = regval >> 32;
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}
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if (env->macsr & MACSR_FI) {
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regval = (((uint64_t)acc) << 8) | extlow;
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regval |= ((int64_t)exthigh) << 40;
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} else if (env->macsr & MACSR_SU) {
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regval = acc | (((int64_t)extlow) << 32);
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regval |= ((int64_t)exthigh) << 40;
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} else {
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regval = acc | (((uint64_t)extlow) << 32);
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regval |= ((uint64_t)(uint8_t)exthigh) << 40;
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}
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env->macc[i] = regval;
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}
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}
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env->macsr = val;
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}
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2007-06-03 13:13:39 +02:00
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void m68k_switch_sp(CPUM68KState *env)
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{
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int new_sp;
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env->sp[env->current_sp] = env->aregs[7];
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new_sp = (env->sr & SR_S && env->cacr & M68K_CACR_EUSP)
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? M68K_SSP : M68K_USP;
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env->aregs[7] = env->sp[new_sp];
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env->current_sp = new_sp;
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}
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2007-09-16 23:08:06 +02:00
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#if defined(CONFIG_USER_ONLY)
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2007-05-23 21:58:11 +02:00
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2013-08-26 03:01:33 +02:00
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int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
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int mmu_idx)
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2007-05-23 21:58:11 +02:00
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{
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2013-08-26 03:01:33 +02:00
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M68kCPU *cpu = M68K_CPU(cs);
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2013-08-26 08:31:06 +02:00
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cs->exception_index = EXCP_ACCESS;
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2013-08-26 03:01:33 +02:00
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cpu->env.mmu.ar = address;
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2007-05-23 21:58:11 +02:00
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return 1;
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}
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#else
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2010-03-01 04:46:18 +01:00
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/* MMU */
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/* TODO: This will need fixing once the MMU is implemented. */
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2013-06-29 18:55:54 +02:00
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hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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2010-03-01 04:46:18 +01:00
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{
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return addr;
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}
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2013-08-26 03:01:33 +02:00
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int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
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int mmu_idx)
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2007-05-23 21:58:11 +02:00
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{
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int prot;
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address &= TARGET_PAGE_MASK;
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2010-03-17 03:14:28 +01:00
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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2013-09-03 13:59:37 +02:00
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tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
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2010-03-17 03:14:28 +01:00
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return 0;
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2007-05-23 21:58:11 +02:00
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}
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/* Notify CPU of a pending interrupt. Prioritization and vectoring should
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be handled by the interrupt controller. Real hardware only requests
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the vector when the interrupt is acknowledged by the CPU. For
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simplicitly we calculate it when the interrupt is signalled. */
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2013-01-18 14:20:52 +01:00
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void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector)
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2007-05-23 21:58:11 +02:00
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{
|
2013-01-17 22:30:20 +01:00
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CPUState *cs = CPU(cpu);
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2013-01-18 14:20:52 +01:00
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CPUM68KState *env = &cpu->env;
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2007-05-23 21:58:11 +02:00
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env->pending_level = level;
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env->pending_vector = vector;
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2013-01-17 22:30:20 +01:00
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if (level) {
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2013-01-18 15:03:43 +01:00
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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2013-01-17 22:30:20 +01:00
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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2007-05-23 21:58:11 +02:00
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}
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#endif
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2008-05-25 00:29:16 +02:00
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uint32_t HELPER(bitrev)(uint32_t x)
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{
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x = ((x >> 1) & 0x55555555u) | ((x << 1) & 0xaaaaaaaau);
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x = ((x >> 2) & 0x33333333u) | ((x << 2) & 0xccccccccu);
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x = ((x >> 4) & 0x0f0f0f0fu) | ((x << 4) & 0xf0f0f0f0u);
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return bswap32(x);
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}
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uint32_t HELPER(ff1)(uint32_t x)
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{
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int n;
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for (n = 32; x; n--)
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x >>= 1;
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return n;
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}
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|
2015-08-14 16:59:20 +02:00
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uint32_t HELPER(sats)(uint32_t val, uint32_t v)
|
2008-05-25 00:29:16 +02:00
|
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{
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/* The result has the opposite sign to the original value. */
|
2015-08-14 16:59:20 +02:00
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|
|
if ((int32_t)v < 0) {
|
2008-05-25 00:29:16 +02:00
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val = (((int32_t)val) >> 31) ^ SIGNBIT;
|
2015-08-14 16:59:20 +02:00
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}
|
2008-05-25 00:29:16 +02:00
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return val;
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}
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|
2012-03-14 01:38:22 +01:00
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void HELPER(set_sr)(CPUM68KState *env, uint32_t val)
|
2008-05-25 00:29:16 +02:00
|
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{
|
2015-08-14 16:59:17 +02:00
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|
env->sr = val & 0xffe0;
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|
cpu_m68k_set_ccr(env, val);
|
2008-05-25 00:29:16 +02:00
|
|
|
m68k_switch_sp(env);
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}
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|
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|
2012-03-14 01:38:22 +01:00
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uint32_t HELPER(shl_cc)(CPUM68KState *env, uint32_t val, uint32_t shift)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
2015-08-14 16:59:20 +02:00
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|
|
uint64_t result;
|
2008-05-25 00:29:16 +02:00
|
|
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|
|
shift &= 63;
|
2015-08-14 16:59:20 +02:00
|
|
|
result = (uint64_t)val << shift;
|
|
|
|
|
|
|
|
env->cc_c = (result >> 32) & 1;
|
|
|
|
env->cc_n = result;
|
|
|
|
env->cc_z = result;
|
|
|
|
env->cc_v = 0;
|
|
|
|
env->cc_x = shift ? env->cc_c : env->cc_x;
|
|
|
|
|
2008-05-25 00:29:16 +02:00
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
uint32_t HELPER(shr_cc)(CPUM68KState *env, uint32_t val, uint32_t shift)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
2015-08-14 16:59:20 +02:00
|
|
|
uint64_t temp;
|
2008-05-25 00:29:16 +02:00
|
|
|
uint32_t result;
|
|
|
|
|
|
|
|
shift &= 63;
|
2015-08-14 16:59:20 +02:00
|
|
|
temp = (uint64_t)val << 32 >> shift;
|
|
|
|
result = temp >> 32;
|
|
|
|
|
|
|
|
env->cc_c = (temp >> 31) & 1;
|
|
|
|
env->cc_n = result;
|
|
|
|
env->cc_z = result;
|
|
|
|
env->cc_v = 0;
|
|
|
|
env->cc_x = shift ? env->cc_c : env->cc_x;
|
|
|
|
|
2008-05-25 00:29:16 +02:00
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
uint32_t HELPER(sar_cc)(CPUM68KState *env, uint32_t val, uint32_t shift)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
2015-08-14 16:59:20 +02:00
|
|
|
uint64_t temp;
|
2008-05-25 00:29:16 +02:00
|
|
|
uint32_t result;
|
|
|
|
|
|
|
|
shift &= 63;
|
2015-08-14 16:59:20 +02:00
|
|
|
temp = (int64_t)val << 32 >> shift;
|
|
|
|
result = temp >> 32;
|
|
|
|
|
|
|
|
env->cc_c = (temp >> 31) & 1;
|
|
|
|
env->cc_n = result;
|
|
|
|
env->cc_z = result;
|
|
|
|
env->cc_v = result ^ val;
|
|
|
|
env->cc_x = shift ? env->cc_c : env->cc_x;
|
|
|
|
|
2008-05-25 00:29:16 +02:00
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* FPU helpers. */
|
2012-03-14 01:38:22 +01:00
|
|
|
uint32_t HELPER(f64_to_i32)(CPUM68KState *env, float64 val)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
return float64_to_int32(val, &env->fp_status);
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
float32 HELPER(f64_to_f32)(CPUM68KState *env, float64 val)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
return float64_to_float32(val, &env->fp_status);
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
float64 HELPER(i32_to_f64)(CPUM68KState *env, uint32_t val)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
return int32_to_float64(val, &env->fp_status);
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
float64 HELPER(f32_to_f64)(CPUM68KState *env, float32 val)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
return float32_to_float64(val, &env->fp_status);
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
float64 HELPER(iround_f64)(CPUM68KState *env, float64 val)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
return float64_round_to_int(val, &env->fp_status);
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
float64 HELPER(itrunc_f64)(CPUM68KState *env, float64 val)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
return float64_trunc_to_int(val, &env->fp_status);
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
float64 HELPER(sqrt_f64)(CPUM68KState *env, float64 val)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
return float64_sqrt(val, &env->fp_status);
|
|
|
|
}
|
|
|
|
|
|
|
|
float64 HELPER(abs_f64)(float64 val)
|
|
|
|
{
|
|
|
|
return float64_abs(val);
|
|
|
|
}
|
|
|
|
|
|
|
|
float64 HELPER(chs_f64)(float64 val)
|
|
|
|
{
|
|
|
|
return float64_chs(val);
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
float64 HELPER(add_f64)(CPUM68KState *env, float64 a, float64 b)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
return float64_add(a, b, &env->fp_status);
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
float64 HELPER(sub_f64)(CPUM68KState *env, float64 a, float64 b)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
return float64_sub(a, b, &env->fp_status);
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
float64 HELPER(mul_f64)(CPUM68KState *env, float64 a, float64 b)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
return float64_mul(a, b, &env->fp_status);
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
float64 HELPER(div_f64)(CPUM68KState *env, float64 a, float64 b)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
return float64_div(a, b, &env->fp_status);
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
float64 HELPER(sub_cmp_f64)(CPUM68KState *env, float64 a, float64 b)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
/* ??? This may incorrectly raise exceptions. */
|
|
|
|
/* ??? Should flush denormals to zero. */
|
|
|
|
float64 res;
|
|
|
|
res = float64_sub(a, b, &env->fp_status);
|
softfloat: Implement run-time-configurable meaning of signaling NaN bit
This patch modifies SoftFloat library so that it can be configured in
run-time in relation to the meaning of signaling NaN bit, while, at the
same time, strictly preserving its behavior on all existing platforms.
Background:
In floating-point calculations, there is a need for denoting undefined or
unrepresentable values. This is achieved by defining certain floating-point
numerical values to be NaNs (which stands for "not a number"). For additional
reasons, virtually all modern floating-point unit implementations use two
kinds of NaNs: quiet and signaling. The binary representations of these two
kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally,
the first bit of mantissa).
Up to 2008, standards for floating-point did not specify all details about
binary representation of NaNs. More specifically, the meaning of the bit
that is used for distinguishing between signaling and quiet NaNs was not
strictly prescribed. (IEEE 754-2008 was the first floating-point standard
that defined that meaning clearly, see [1], p. 35) As a result, different
platforms took different approaches, and that presented considerable
challenge for multi-platform emulators like QEMU.
Mips platform represents the most complex case among QEMU-supported
platforms regarding signaling NaN bit. Up to the Release 6 of Mips
architecture, "1" in signaling NaN bit denoted signaling NaN, which is
opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture
adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of
that, Mips architecture for SIMD (also known as MSA, or vector instructions)
also specifies signaling bit in accordance to IEEE standard. MSA unit can be
implemented with both pre-Release 6 and Release 6 main processor units.
QEMU uses SoftFloat library to implement various floating-point-related
instructions on all platforms. The current QEMU implementation allows for
defining meaning of signaling NaN bit during build time, and is implemented
via preprocessor macro called SNAN_BIT_IS_ONE.
On the other hand, the change in this patch enables SoftFloat library to be
configured in run-time. This configuration is meant to occur during CPU
initialization, at the moment when it is definitely known what desired
behavior for particular CPU (or any additional FPUs) is.
The change is implemented so that it is consistent with existing
implementation of similar cases. This means that structure float_status is
used for passing the information about desired signaling NaN bit on each
invocation of SoftFloat functions. The additional field in float_status is
called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE.
IMPORTANT:
This change is not meant to create any change in emulator behavior or
functionality on any platform. It just provides the means for SoftFloat
library to be used in a more flexible way - in other words, it will just
prepare SoftFloat library for usage related to Mips platform and its
specifics regarding signaling bit meaning, which is done in some of
subsequent patches from this series.
Further break down of changes:
1) Added field snan_bit_is_one to the structure float_status, and
correspondent setter function set_snan_bit_is_one().
2) Constants <float16|float32|float64|floatx80|float128>_default_nan
(used both internally and externally) converted to functions
<float16|float32|float64|floatx80|float128>_default_nan(float_status*).
This is necessary since they are dependent on signaling bit meaning.
At the same time, for the sake of code cleanup and simplicity, constants
<floatx80|float128>_default_nan_<low|high> (used only internally within
SoftFloat library) are removed, as not needed.
3) Added a float_status* argument to SoftFloat library functions
XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_),
XXX_maybe_silence_nan(XXX a_). This argument must be present in
order to enable correct invocation of new version of functions
XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128>
here)
4) Updated code for all platforms to reflect changes in SoftFloat library.
This change is twofolds: it includes modifications of SoftFloat library
functions invocations, and an addition of invocation of function
set_snan_bit_is_one() during CPU initialization, with arguments that
are appropriate for each particular platform. It was established that
all platforms zero their main CPU data structures, so snan_bit_is_one(0)
in appropriate places is not added, as it is not needed.
[1] "IEEE Standard for Floating-Point Arithmetic",
IEEE Computer Society, August 29, 2008.
Signed-off-by: Thomas Schwinge <thomas@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Tested-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[leon.alrae@imgtec.com:
* cherry-picked 2 chunks from patch #2 to fix compilation warnings]
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-10 11:57:28 +02:00
|
|
|
if (float64_is_quiet_nan(res, &env->fp_status)) {
|
2008-05-25 00:29:16 +02:00
|
|
|
/* +/-inf compares equal against itself, but sub returns nan. */
|
softfloat: Implement run-time-configurable meaning of signaling NaN bit
This patch modifies SoftFloat library so that it can be configured in
run-time in relation to the meaning of signaling NaN bit, while, at the
same time, strictly preserving its behavior on all existing platforms.
Background:
In floating-point calculations, there is a need for denoting undefined or
unrepresentable values. This is achieved by defining certain floating-point
numerical values to be NaNs (which stands for "not a number"). For additional
reasons, virtually all modern floating-point unit implementations use two
kinds of NaNs: quiet and signaling. The binary representations of these two
kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally,
the first bit of mantissa).
Up to 2008, standards for floating-point did not specify all details about
binary representation of NaNs. More specifically, the meaning of the bit
that is used for distinguishing between signaling and quiet NaNs was not
strictly prescribed. (IEEE 754-2008 was the first floating-point standard
that defined that meaning clearly, see [1], p. 35) As a result, different
platforms took different approaches, and that presented considerable
challenge for multi-platform emulators like QEMU.
Mips platform represents the most complex case among QEMU-supported
platforms regarding signaling NaN bit. Up to the Release 6 of Mips
architecture, "1" in signaling NaN bit denoted signaling NaN, which is
opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture
adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of
that, Mips architecture for SIMD (also known as MSA, or vector instructions)
also specifies signaling bit in accordance to IEEE standard. MSA unit can be
implemented with both pre-Release 6 and Release 6 main processor units.
QEMU uses SoftFloat library to implement various floating-point-related
instructions on all platforms. The current QEMU implementation allows for
defining meaning of signaling NaN bit during build time, and is implemented
via preprocessor macro called SNAN_BIT_IS_ONE.
On the other hand, the change in this patch enables SoftFloat library to be
configured in run-time. This configuration is meant to occur during CPU
initialization, at the moment when it is definitely known what desired
behavior for particular CPU (or any additional FPUs) is.
The change is implemented so that it is consistent with existing
implementation of similar cases. This means that structure float_status is
used for passing the information about desired signaling NaN bit on each
invocation of SoftFloat functions. The additional field in float_status is
called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE.
IMPORTANT:
This change is not meant to create any change in emulator behavior or
functionality on any platform. It just provides the means for SoftFloat
library to be used in a more flexible way - in other words, it will just
prepare SoftFloat library for usage related to Mips platform and its
specifics regarding signaling bit meaning, which is done in some of
subsequent patches from this series.
Further break down of changes:
1) Added field snan_bit_is_one to the structure float_status, and
correspondent setter function set_snan_bit_is_one().
2) Constants <float16|float32|float64|floatx80|float128>_default_nan
(used both internally and externally) converted to functions
<float16|float32|float64|floatx80|float128>_default_nan(float_status*).
This is necessary since they are dependent on signaling bit meaning.
At the same time, for the sake of code cleanup and simplicity, constants
<floatx80|float128>_default_nan_<low|high> (used only internally within
SoftFloat library) are removed, as not needed.
3) Added a float_status* argument to SoftFloat library functions
XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_),
XXX_maybe_silence_nan(XXX a_). This argument must be present in
order to enable correct invocation of new version of functions
XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128>
here)
4) Updated code for all platforms to reflect changes in SoftFloat library.
This change is twofolds: it includes modifications of SoftFloat library
functions invocations, and an addition of invocation of function
set_snan_bit_is_one() during CPU initialization, with arguments that
are appropriate for each particular platform. It was established that
all platforms zero their main CPU data structures, so snan_bit_is_one(0)
in appropriate places is not added, as it is not needed.
[1] "IEEE Standard for Floating-Point Arithmetic",
IEEE Computer Society, August 29, 2008.
Signed-off-by: Thomas Schwinge <thomas@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Tested-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[leon.alrae@imgtec.com:
* cherry-picked 2 chunks from patch #2 to fix compilation warnings]
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-10 11:57:28 +02:00
|
|
|
if (!float64_is_quiet_nan(a, &env->fp_status)
|
|
|
|
&& !float64_is_quiet_nan(b, &env->fp_status)) {
|
2008-05-25 00:29:16 +02:00
|
|
|
res = float64_zero;
|
|
|
|
if (float64_lt_quiet(a, res, &env->fp_status))
|
|
|
|
res = float64_chs(res);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
uint32_t HELPER(compare_f64)(CPUM68KState *env, float64 val)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
return float64_compare_quiet(val, float64_zero, &env->fp_status);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* MAC unit. */
|
|
|
|
/* FIXME: The MAC unit implementation is a bit of a mess. Some helpers
|
|
|
|
take values, others take register numbers and manipulate the contents
|
|
|
|
in-place. */
|
2012-03-14 01:38:22 +01:00
|
|
|
void HELPER(mac_move)(CPUM68KState *env, uint32_t dest, uint32_t src)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
uint32_t mask;
|
|
|
|
env->macc[dest] = env->macc[src];
|
|
|
|
mask = MACSR_PAV0 << dest;
|
|
|
|
if (env->macsr & (MACSR_PAV0 << src))
|
|
|
|
env->macsr |= mask;
|
|
|
|
else
|
|
|
|
env->macsr &= ~mask;
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
uint64_t HELPER(macmuls)(CPUM68KState *env, uint32_t op1, uint32_t op2)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
int64_t product;
|
|
|
|
int64_t res;
|
|
|
|
|
|
|
|
product = (uint64_t)op1 * op2;
|
|
|
|
res = (product << 24) >> 24;
|
|
|
|
if (res != product) {
|
|
|
|
env->macsr |= MACSR_V;
|
|
|
|
if (env->macsr & MACSR_OMC) {
|
|
|
|
/* Make sure the accumulate operation overflows. */
|
|
|
|
if (product < 0)
|
|
|
|
res = ~(1ll << 50);
|
|
|
|
else
|
|
|
|
res = 1ll << 50;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
uint64_t HELPER(macmulu)(CPUM68KState *env, uint32_t op1, uint32_t op2)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
uint64_t product;
|
|
|
|
|
|
|
|
product = (uint64_t)op1 * op2;
|
|
|
|
if (product & (0xffffffull << 40)) {
|
|
|
|
env->macsr |= MACSR_V;
|
|
|
|
if (env->macsr & MACSR_OMC) {
|
|
|
|
/* Make sure the accumulate operation overflows. */
|
|
|
|
product = 1ll << 50;
|
|
|
|
} else {
|
|
|
|
product &= ((1ull << 40) - 1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return product;
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
uint64_t HELPER(macmulf)(CPUM68KState *env, uint32_t op1, uint32_t op2)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
uint64_t product;
|
|
|
|
uint32_t remainder;
|
|
|
|
|
|
|
|
product = (uint64_t)op1 * op2;
|
|
|
|
if (env->macsr & MACSR_RT) {
|
|
|
|
remainder = product & 0xffffff;
|
|
|
|
product >>= 24;
|
|
|
|
if (remainder > 0x800000)
|
|
|
|
product++;
|
|
|
|
else if (remainder == 0x800000)
|
|
|
|
product += (product & 1);
|
|
|
|
} else {
|
|
|
|
product >>= 24;
|
|
|
|
}
|
|
|
|
return product;
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
void HELPER(macsats)(CPUM68KState *env, uint32_t acc)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
int64_t tmp;
|
|
|
|
int64_t result;
|
|
|
|
tmp = env->macc[acc];
|
|
|
|
result = ((tmp << 16) >> 16);
|
|
|
|
if (result != tmp) {
|
|
|
|
env->macsr |= MACSR_V;
|
|
|
|
}
|
|
|
|
if (env->macsr & MACSR_V) {
|
|
|
|
env->macsr |= MACSR_PAV0 << acc;
|
|
|
|
if (env->macsr & MACSR_OMC) {
|
2011-04-28 17:20:38 +02:00
|
|
|
/* The result is saturated to 32 bits, despite overflow occurring
|
2008-05-25 00:29:16 +02:00
|
|
|
at 48 bits. Seems weird, but that's what the hardware docs
|
|
|
|
say. */
|
|
|
|
result = (result >> 63) ^ 0x7fffffff;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
env->macc[acc] = result;
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
void HELPER(macsatu)(CPUM68KState *env, uint32_t acc)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
uint64_t val;
|
|
|
|
|
|
|
|
val = env->macc[acc];
|
|
|
|
if (val & (0xffffull << 48)) {
|
|
|
|
env->macsr |= MACSR_V;
|
|
|
|
}
|
|
|
|
if (env->macsr & MACSR_V) {
|
|
|
|
env->macsr |= MACSR_PAV0 << acc;
|
|
|
|
if (env->macsr & MACSR_OMC) {
|
|
|
|
if (val > (1ull << 53))
|
|
|
|
val = 0;
|
|
|
|
else
|
|
|
|
val = (1ull << 48) - 1;
|
|
|
|
} else {
|
|
|
|
val &= ((1ull << 48) - 1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
env->macc[acc] = val;
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
void HELPER(macsatf)(CPUM68KState *env, uint32_t acc)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
int64_t sum;
|
|
|
|
int64_t result;
|
|
|
|
|
|
|
|
sum = env->macc[acc];
|
|
|
|
result = (sum << 16) >> 16;
|
|
|
|
if (result != sum) {
|
|
|
|
env->macsr |= MACSR_V;
|
|
|
|
}
|
|
|
|
if (env->macsr & MACSR_V) {
|
|
|
|
env->macsr |= MACSR_PAV0 << acc;
|
|
|
|
if (env->macsr & MACSR_OMC) {
|
|
|
|
result = (result >> 63) ^ 0x7fffffffffffll;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
env->macc[acc] = result;
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
void HELPER(mac_set_flags)(CPUM68KState *env, uint32_t acc)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
uint64_t val;
|
|
|
|
val = env->macc[acc];
|
2010-04-23 21:22:22 +02:00
|
|
|
if (val == 0) {
|
2008-05-25 00:29:16 +02:00
|
|
|
env->macsr |= MACSR_Z;
|
2010-04-23 21:22:22 +02:00
|
|
|
} else if (val & (1ull << 47)) {
|
2008-05-25 00:29:16 +02:00
|
|
|
env->macsr |= MACSR_N;
|
2010-04-23 21:22:22 +02:00
|
|
|
}
|
2008-05-25 00:29:16 +02:00
|
|
|
if (env->macsr & (MACSR_PAV0 << acc)) {
|
|
|
|
env->macsr |= MACSR_V;
|
|
|
|
}
|
|
|
|
if (env->macsr & MACSR_FI) {
|
|
|
|
val = ((int64_t)val) >> 40;
|
|
|
|
if (val != 0 && val != -1)
|
|
|
|
env->macsr |= MACSR_EV;
|
|
|
|
} else if (env->macsr & MACSR_SU) {
|
|
|
|
val = ((int64_t)val) >> 32;
|
|
|
|
if (val != 0 && val != -1)
|
|
|
|
env->macsr |= MACSR_EV;
|
|
|
|
} else {
|
|
|
|
if ((val >> 32) != 0)
|
|
|
|
env->macsr |= MACSR_EV;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-01-16 17:23:50 +01:00
|
|
|
#define EXTSIGN(val, index) ( \
|
|
|
|
(index == 0) ? (int8_t)(val) : ((index == 1) ? (int16_t)(val) : (val)) \
|
|
|
|
)
|
2015-08-14 16:59:20 +02:00
|
|
|
|
|
|
|
#define COMPUTE_CCR(op, x, n, z, v, c) { \
|
|
|
|
switch (op) { \
|
|
|
|
case CC_OP_FLAGS: \
|
|
|
|
/* Everything in place. */ \
|
|
|
|
break; \
|
2016-01-16 17:23:50 +01:00
|
|
|
case CC_OP_ADDB: \
|
|
|
|
case CC_OP_ADDW: \
|
|
|
|
case CC_OP_ADDL: \
|
2015-08-14 16:59:20 +02:00
|
|
|
res = n; \
|
|
|
|
src2 = v; \
|
2016-01-16 17:23:50 +01:00
|
|
|
src1 = EXTSIGN(res - src2, op - CC_OP_ADDB); \
|
2015-08-14 16:59:20 +02:00
|
|
|
c = x; \
|
|
|
|
z = n; \
|
|
|
|
v = (res ^ src1) & ~(src1 ^ src2); \
|
|
|
|
break; \
|
2016-01-16 17:23:50 +01:00
|
|
|
case CC_OP_SUBB: \
|
|
|
|
case CC_OP_SUBW: \
|
|
|
|
case CC_OP_SUBL: \
|
2015-08-14 16:59:20 +02:00
|
|
|
res = n; \
|
|
|
|
src2 = v; \
|
2016-01-16 17:23:50 +01:00
|
|
|
src1 = EXTSIGN(res + src2, op - CC_OP_SUBB); \
|
2015-08-14 16:59:20 +02:00
|
|
|
c = x; \
|
|
|
|
z = n; \
|
|
|
|
v = (res ^ src1) & (src1 ^ src2); \
|
|
|
|
break; \
|
2016-01-16 17:23:50 +01:00
|
|
|
case CC_OP_CMPB: \
|
|
|
|
case CC_OP_CMPW: \
|
|
|
|
case CC_OP_CMPL: \
|
2015-08-14 16:59:20 +02:00
|
|
|
src1 = n; \
|
|
|
|
src2 = v; \
|
2016-01-16 17:23:50 +01:00
|
|
|
res = EXTSIGN(src1 - src2, op - CC_OP_CMPB); \
|
2015-08-14 16:59:20 +02:00
|
|
|
n = res; \
|
|
|
|
z = res; \
|
|
|
|
c = src1 < src2; \
|
|
|
|
v = (res ^ src1) & (src1 ^ src2); \
|
|
|
|
break; \
|
|
|
|
case CC_OP_LOGIC: \
|
|
|
|
c = v = 0; \
|
|
|
|
z = n; \
|
|
|
|
break; \
|
|
|
|
default: \
|
|
|
|
cpu_abort(CPU(m68k_env_get_cpu(env)), "Bad CC_OP %d", op); \
|
|
|
|
} \
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
uint32_t cpu_m68k_get_ccr(CPUM68KState *env)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
2015-08-14 16:59:20 +02:00
|
|
|
uint32_t x, c, n, z, v;
|
|
|
|
uint32_t res, src1, src2;
|
|
|
|
|
|
|
|
x = env->cc_x;
|
|
|
|
n = env->cc_n;
|
|
|
|
z = env->cc_z;
|
|
|
|
v = env->cc_v;
|
2016-01-16 17:23:50 +01:00
|
|
|
c = env->cc_c;
|
2015-08-14 16:59:20 +02:00
|
|
|
|
|
|
|
COMPUTE_CCR(env->cc_op, x, n, z, v, c);
|
|
|
|
|
|
|
|
n = n >> 31;
|
|
|
|
z = (z == 0);
|
2016-01-16 17:23:50 +01:00
|
|
|
v = v >> 31;
|
2015-08-14 16:59:20 +02:00
|
|
|
|
|
|
|
return x * CCF_X + n * CCF_N + z * CCF_Z + v * CCF_V + c * CCF_C;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t HELPER(get_ccr)(CPUM68KState *env)
|
|
|
|
{
|
|
|
|
return cpu_m68k_get_ccr(env);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t ccr)
|
|
|
|
{
|
|
|
|
env->cc_x = (ccr & CCF_X ? 1 : 0);
|
|
|
|
env->cc_n = (ccr & CCF_N ? -1 : 0);
|
|
|
|
env->cc_z = (ccr & CCF_Z ? 0 : 1);
|
|
|
|
env->cc_v = (ccr & CCF_V ? -1 : 0);
|
|
|
|
env->cc_c = (ccr & CCF_C ? 1 : 0);
|
|
|
|
env->cc_op = CC_OP_FLAGS;
|
|
|
|
}
|
|
|
|
|
|
|
|
void HELPER(set_ccr)(CPUM68KState *env, uint32_t ccr)
|
|
|
|
{
|
|
|
|
cpu_m68k_set_ccr(env, ccr);
|
|
|
|
}
|
|
|
|
|
|
|
|
void HELPER(flush_flags)(CPUM68KState *env, uint32_t cc_op)
|
|
|
|
{
|
|
|
|
uint32_t res, src1, src2;
|
|
|
|
|
|
|
|
COMPUTE_CCR(cc_op, env->cc_x, env->cc_n, env->cc_z, env->cc_v, env->cc_c);
|
|
|
|
env->cc_op = CC_OP_FLAGS;
|
2008-05-25 00:29:16 +02:00
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
uint32_t HELPER(get_macf)(CPUM68KState *env, uint64_t val)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
int rem;
|
|
|
|
uint32_t result;
|
|
|
|
|
|
|
|
if (env->macsr & MACSR_SU) {
|
|
|
|
/* 16-bit rounding. */
|
|
|
|
rem = val & 0xffffff;
|
|
|
|
val = (val >> 24) & 0xffffu;
|
|
|
|
if (rem > 0x800000)
|
|
|
|
val++;
|
|
|
|
else if (rem == 0x800000)
|
|
|
|
val += (val & 1);
|
|
|
|
} else if (env->macsr & MACSR_RT) {
|
|
|
|
/* 32-bit rounding. */
|
|
|
|
rem = val & 0xff;
|
|
|
|
val >>= 8;
|
|
|
|
if (rem > 0x80)
|
|
|
|
val++;
|
|
|
|
else if (rem == 0x80)
|
|
|
|
val += (val & 1);
|
|
|
|
} else {
|
|
|
|
/* No rounding. */
|
|
|
|
val >>= 8;
|
|
|
|
}
|
|
|
|
if (env->macsr & MACSR_OMC) {
|
|
|
|
/* Saturate. */
|
|
|
|
if (env->macsr & MACSR_SU) {
|
|
|
|
if (val != (uint16_t) val) {
|
|
|
|
result = ((val >> 63) ^ 0x7fff) & 0xffff;
|
|
|
|
} else {
|
|
|
|
result = val & 0xffff;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (val != (uint32_t)val) {
|
|
|
|
result = ((uint32_t)(val >> 63) & 0x7fffffff);
|
|
|
|
} else {
|
|
|
|
result = (uint32_t)val;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* No saturation. */
|
|
|
|
if (env->macsr & MACSR_SU) {
|
|
|
|
result = val & 0xffff;
|
|
|
|
} else {
|
|
|
|
result = (uint32_t)val;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t HELPER(get_macs)(uint64_t val)
|
|
|
|
{
|
|
|
|
if (val == (int32_t)val) {
|
|
|
|
return (int32_t)val;
|
|
|
|
} else {
|
|
|
|
return (val >> 61) ^ ~SIGNBIT;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t HELPER(get_macu)(uint64_t val)
|
|
|
|
{
|
|
|
|
if ((val >> 32) == 0) {
|
|
|
|
return (uint32_t)val;
|
|
|
|
} else {
|
|
|
|
return 0xffffffffu;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
uint32_t HELPER(get_mac_extf)(CPUM68KState *env, uint32_t acc)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
uint32_t val;
|
|
|
|
val = env->macc[acc] & 0x00ff;
|
2016-07-15 17:29:22 +02:00
|
|
|
val |= (env->macc[acc] >> 32) & 0xff00;
|
2008-05-25 00:29:16 +02:00
|
|
|
val |= (env->macc[acc + 1] << 16) & 0x00ff0000;
|
|
|
|
val |= (env->macc[acc + 1] >> 16) & 0xff000000;
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
uint32_t HELPER(get_mac_exti)(CPUM68KState *env, uint32_t acc)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
uint32_t val;
|
|
|
|
val = (env->macc[acc] >> 32) & 0xffff;
|
|
|
|
val |= (env->macc[acc + 1] >> 16) & 0xffff0000;
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
void HELPER(set_mac_extf)(CPUM68KState *env, uint32_t val, uint32_t acc)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
int64_t res;
|
|
|
|
int32_t tmp;
|
|
|
|
res = env->macc[acc] & 0xffffffff00ull;
|
|
|
|
tmp = (int16_t)(val & 0xff00);
|
|
|
|
res |= ((int64_t)tmp) << 32;
|
|
|
|
res |= val & 0xff;
|
|
|
|
env->macc[acc] = res;
|
|
|
|
res = env->macc[acc + 1] & 0xffffffff00ull;
|
|
|
|
tmp = (val & 0xff000000);
|
|
|
|
res |= ((int64_t)tmp) << 16;
|
|
|
|
res |= (val >> 16) & 0xff;
|
|
|
|
env->macc[acc + 1] = res;
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
void HELPER(set_mac_exts)(CPUM68KState *env, uint32_t val, uint32_t acc)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
int64_t res;
|
|
|
|
int32_t tmp;
|
|
|
|
res = (uint32_t)env->macc[acc];
|
|
|
|
tmp = (int16_t)val;
|
|
|
|
res |= ((int64_t)tmp) << 32;
|
|
|
|
env->macc[acc] = res;
|
|
|
|
res = (uint32_t)env->macc[acc + 1];
|
|
|
|
tmp = val & 0xffff0000;
|
|
|
|
res |= (int64_t)tmp << 16;
|
|
|
|
env->macc[acc + 1] = res;
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:22 +01:00
|
|
|
void HELPER(set_mac_extu)(CPUM68KState *env, uint32_t val, uint32_t acc)
|
2008-05-25 00:29:16 +02:00
|
|
|
{
|
|
|
|
uint64_t res;
|
|
|
|
res = (uint32_t)env->macc[acc];
|
|
|
|
res |= ((uint64_t)(val & 0xffff)) << 32;
|
|
|
|
env->macc[acc] = res;
|
|
|
|
res = (uint32_t)env->macc[acc + 1];
|
|
|
|
res |= (uint64_t)(val & 0xffff0000) << 16;
|
|
|
|
env->macc[acc + 1] = res;
|
|
|
|
}
|