2004-09-30 23:55:55 +02:00
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#include "exec.h"
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2007-10-28 15:35:04 +01:00
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#include "host-utils.h"
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2008-02-24 15:10:06 +01:00
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#include "helper.h"
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2004-09-30 23:55:55 +02:00
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2005-07-23 16:27:54 +02:00
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//#define DEBUG_PCALL
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2004-12-20 00:18:01 +01:00
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//#define DEBUG_MMU
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2007-10-14 18:29:21 +02:00
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//#define DEBUG_MXCC
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2007-05-07 20:05:05 +02:00
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//#define DEBUG_UNALIGNED
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2007-05-17 21:30:10 +02:00
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//#define DEBUG_UNASSIGNED
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2007-12-28 19:50:23 +01:00
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//#define DEBUG_ASI
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2004-12-20 00:18:01 +01:00
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2007-10-14 18:29:21 +02:00
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#ifdef DEBUG_MMU
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#define DPRINTF_MMU(fmt, args...) \
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do { printf("MMU: " fmt , ##args); } while (0)
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#else
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#define DPRINTF_MMU(fmt, args...)
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#endif
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#ifdef DEBUG_MXCC
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#define DPRINTF_MXCC(fmt, args...) \
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do { printf("MXCC: " fmt , ##args); } while (0)
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#else
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#define DPRINTF_MXCC(fmt, args...)
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#endif
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2007-12-28 19:50:23 +01:00
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#ifdef DEBUG_ASI
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#define DPRINTF_ASI(fmt, args...) \
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do { printf("ASI: " fmt , ##args); } while (0)
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#else
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#define DPRINTF_ASI(fmt, args...)
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#endif
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2005-02-08 00:10:53 +01:00
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void raise_exception(int tt)
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{
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env->exception_index = tt;
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cpu_loop_exit();
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2007-09-17 10:09:54 +02:00
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}
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2005-02-08 00:10:53 +01:00
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2008-02-24 15:10:06 +01:00
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void helper_trap(target_ulong nb_trap)
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2007-04-06 22:03:29 +02:00
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{
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2008-02-24 15:10:06 +01:00
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env->exception_index = TT_TRAP + (nb_trap & 0x7f);
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cpu_loop_exit();
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}
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void helper_trapcc(target_ulong nb_trap, target_ulong do_trap)
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{
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if (do_trap) {
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env->exception_index = TT_TRAP + (nb_trap & 0x7f);
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cpu_loop_exit();
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}
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}
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2008-03-04 21:00:18 +01:00
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void helper_check_ieee_exceptions(void)
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2008-02-24 15:10:06 +01:00
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{
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target_ulong status;
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status = get_float_exception_flags(&env->fp_status);
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if (status) {
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2007-09-20 16:54:22 +02:00
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/* Copy IEEE 754 flags into FSR */
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2008-02-24 15:10:06 +01:00
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if (status & float_flag_invalid)
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2007-09-20 16:54:22 +02:00
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env->fsr |= FSR_NVC;
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2008-02-24 15:10:06 +01:00
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if (status & float_flag_overflow)
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2007-09-20 16:54:22 +02:00
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env->fsr |= FSR_OFC;
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2008-02-24 15:10:06 +01:00
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if (status & float_flag_underflow)
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2007-09-20 16:54:22 +02:00
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env->fsr |= FSR_UFC;
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2008-02-24 15:10:06 +01:00
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if (status & float_flag_divbyzero)
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2007-09-20 16:54:22 +02:00
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env->fsr |= FSR_DZC;
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2008-02-24 15:10:06 +01:00
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if (status & float_flag_inexact)
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2007-09-20 16:54:22 +02:00
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env->fsr |= FSR_NXC;
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2008-02-24 15:10:06 +01:00
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if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
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2007-09-20 16:54:22 +02:00
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/* Unmasked exception, generate a trap */
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env->fsr |= FSR_FTT_IEEE_EXCP;
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raise_exception(TT_FP_EXCP);
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2008-02-24 15:10:06 +01:00
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} else {
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2007-09-20 16:54:22 +02:00
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/* Accumulate exceptions */
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env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
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}
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2008-02-24 15:10:06 +01:00
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}
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2007-04-06 22:03:29 +02:00
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}
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2008-03-04 21:00:18 +01:00
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void helper_clear_float_exceptions(void)
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{
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set_float_exception_flags(0, &env->fp_status);
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}
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2004-10-10 19:46:24 +02:00
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#ifdef USE_INT_TO_FLOAT_HELPERS
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void do_fitos(void)
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{
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2006-12-06 16:51:39 +01:00
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FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
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2004-10-10 19:46:24 +02:00
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}
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void do_fitod(void)
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{
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2006-12-06 16:51:39 +01:00
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DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
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2004-10-10 19:46:24 +02:00
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}
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2007-11-28 19:08:28 +01:00
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#if defined(CONFIG_USER_ONLY)
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void do_fitoq(void)
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{
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QT0 = int32_to_float128(*((int32_t *)&FT1), &env->fp_status);
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}
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#endif
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2007-10-20 09:07:47 +02:00
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#ifdef TARGET_SPARC64
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void do_fxtos(void)
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{
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FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
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}
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void do_fxtod(void)
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{
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DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
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}
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2007-11-28 19:08:28 +01:00
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#if defined(CONFIG_USER_ONLY)
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void do_fxtoq(void)
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{
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QT0 = int64_to_float128(*((int32_t *)&DT1), &env->fp_status);
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}
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#endif
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2007-10-20 09:07:47 +02:00
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#endif
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2004-10-10 19:46:24 +02:00
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#endif
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2008-03-04 21:00:18 +01:00
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void helper_fabss(void)
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2004-09-30 23:55:55 +02:00
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{
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2005-03-13 18:01:47 +01:00
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FT0 = float32_abs(FT1);
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2004-09-30 23:55:55 +02:00
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}
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2005-07-02 16:31:34 +02:00
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#ifdef TARGET_SPARC64
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2008-03-04 21:00:18 +01:00
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void helper_fabsd(void)
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2005-07-02 16:31:34 +02:00
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{
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DT0 = float64_abs(DT1);
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}
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2007-11-25 19:40:20 +01:00
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#if defined(CONFIG_USER_ONLY)
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2008-03-04 21:00:18 +01:00
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void helper_fabsq(void)
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2007-11-25 19:40:20 +01:00
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{
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QT0 = float128_abs(QT1);
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}
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#endif
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2005-07-02 16:31:34 +02:00
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#endif
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2008-03-04 21:00:18 +01:00
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void helper_fsqrts(void)
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2004-09-30 23:55:55 +02:00
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{
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2005-03-13 18:01:47 +01:00
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FT0 = float32_sqrt(FT1, &env->fp_status);
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2004-09-30 23:55:55 +02:00
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}
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2008-03-04 21:00:18 +01:00
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void helper_fsqrtd(void)
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2004-09-30 23:55:55 +02:00
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{
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2005-03-13 18:01:47 +01:00
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DT0 = float64_sqrt(DT1, &env->fp_status);
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2004-09-30 23:55:55 +02:00
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}
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2007-11-25 19:40:20 +01:00
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#if defined(CONFIG_USER_ONLY)
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2008-03-04 21:00:18 +01:00
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void helper_fsqrtq(void)
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2007-11-25 19:40:20 +01:00
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{
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QT0 = float128_sqrt(QT1, &env->fp_status);
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}
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#endif
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2007-04-06 22:03:29 +02:00
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#define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
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2008-03-04 21:00:18 +01:00
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void glue(helper_, name) (void) \
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2006-06-21 20:37:05 +02:00
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{ \
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2008-02-24 15:10:06 +01:00
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target_ulong new_fsr; \
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\
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2006-06-21 20:37:05 +02:00
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
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switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
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case float_relation_unordered: \
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2008-02-24 15:10:06 +01:00
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new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
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2007-04-06 22:03:29 +02:00
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if ((env->fsr & FSR_NVM) || TRAP) { \
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2008-02-24 15:10:06 +01:00
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env->fsr |= new_fsr; \
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2007-04-06 22:03:29 +02:00
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env->fsr |= FSR_NVC; \
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env->fsr |= FSR_FTT_IEEE_EXCP; \
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2006-06-21 20:37:05 +02:00
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raise_exception(TT_FP_EXCP); \
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} else { \
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env->fsr |= FSR_NVA; \
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} \
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break; \
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case float_relation_less: \
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2008-02-24 15:10:06 +01:00
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new_fsr = FSR_FCC0 << FS; \
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2006-06-21 20:37:05 +02:00
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break; \
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case float_relation_greater: \
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2008-02-24 15:10:06 +01:00
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new_fsr = FSR_FCC1 << FS; \
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2006-06-21 20:37:05 +02:00
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break; \
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default: \
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2008-02-24 15:10:06 +01:00
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new_fsr = 0; \
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2006-06-21 20:37:05 +02:00
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break; \
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} \
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2008-02-24 15:10:06 +01:00
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env->fsr |= new_fsr; \
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2004-09-30 23:55:55 +02:00
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}
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2007-04-06 22:03:29 +02:00
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GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0);
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GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
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GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1);
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GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
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2005-07-02 16:31:34 +02:00
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2007-11-25 19:40:20 +01:00
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#ifdef CONFIG_USER_ONLY
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GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
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GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
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#endif
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2005-07-02 16:31:34 +02:00
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#ifdef TARGET_SPARC64
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2007-04-06 22:03:29 +02:00
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GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0);
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GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
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GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0);
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GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
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GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0);
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GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
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GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1);
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GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
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2005-07-02 16:31:34 +02:00
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2007-04-06 22:03:29 +02:00
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GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1);
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GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
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2005-07-02 16:31:34 +02:00
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2007-04-06 22:03:29 +02:00
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GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1);
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GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
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2007-11-25 19:40:20 +01:00
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#ifdef CONFIG_USER_ONLY
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GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
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GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
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GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
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GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
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GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
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GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
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#endif
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2005-07-02 16:31:34 +02:00
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#endif
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2008-02-24 15:10:06 +01:00
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#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && defined(DEBUG_MXCC)
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2007-10-14 18:29:21 +02:00
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static void dump_mxcc(CPUState *env)
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{
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printf("mxccdata: %016llx %016llx %016llx %016llx\n",
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env->mxccdata[0], env->mxccdata[1], env->mxccdata[2], env->mxccdata[3]);
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printf("mxccregs: %016llx %016llx %016llx %016llx\n"
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" %016llx %016llx %016llx %016llx\n",
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env->mxccregs[0], env->mxccregs[1], env->mxccregs[2], env->mxccregs[3],
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env->mxccregs[4], env->mxccregs[5], env->mxccregs[6], env->mxccregs[7]);
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}
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#endif
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2008-02-24 15:10:06 +01:00
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#if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
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&& defined(DEBUG_ASI)
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static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
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uint64_t r1)
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2007-12-28 19:50:23 +01:00
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{
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switch (size)
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{
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case 1:
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2008-02-24 15:10:06 +01:00
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DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
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addr, asi, r1 & 0xff);
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2007-12-28 19:50:23 +01:00
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break;
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case 2:
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2008-02-24 15:10:06 +01:00
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DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
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addr, asi, r1 & 0xffff);
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2007-12-28 19:50:23 +01:00
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break;
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case 4:
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2008-02-24 15:10:06 +01:00
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DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
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addr, asi, r1 & 0xffffffff);
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2007-12-28 19:50:23 +01:00
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break;
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case 8:
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2008-02-24 15:10:06 +01:00
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DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
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addr, asi, r1);
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2007-12-28 19:50:23 +01:00
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break;
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}
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}
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#endif
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2008-02-24 15:10:06 +01:00
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#ifndef TARGET_SPARC64
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#ifndef CONFIG_USER_ONLY
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uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
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2004-09-30 23:55:55 +02:00
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{
|
2008-02-24 15:10:06 +01:00
|
|
|
uint64_t ret = 0;
|
2007-12-28 19:50:23 +01:00
|
|
|
#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
|
2008-02-24 15:10:06 +01:00
|
|
|
uint32_t last_addr = addr;
|
2007-10-14 18:29:21 +02:00
|
|
|
#endif
|
2004-12-20 00:18:01 +01:00
|
|
|
|
|
|
|
switch (asi) {
|
2007-05-17 21:30:10 +02:00
|
|
|
case 2: /* SuperSparc MXCC registers */
|
2008-02-24 15:10:06 +01:00
|
|
|
switch (addr) {
|
2007-10-14 18:29:21 +02:00
|
|
|
case 0x01c00a00: /* MXCC control register */
|
2008-02-24 15:10:06 +01:00
|
|
|
if (size == 8)
|
|
|
|
ret = env->mxccregs[3];
|
|
|
|
else
|
|
|
|
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
2007-10-14 18:29:21 +02:00
|
|
|
break;
|
|
|
|
case 0x01c00a04: /* MXCC control register */
|
|
|
|
if (size == 4)
|
|
|
|
ret = env->mxccregs[3];
|
|
|
|
else
|
2008-02-24 15:10:06 +01:00
|
|
|
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
2007-10-14 18:29:21 +02:00
|
|
|
break;
|
2007-11-17 09:18:59 +01:00
|
|
|
case 0x01c00c00: /* Module reset register */
|
|
|
|
if (size == 8) {
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = env->mxccregs[5];
|
2007-11-17 09:18:59 +01:00
|
|
|
// should we do something here?
|
|
|
|
} else
|
2008-02-24 15:10:06 +01:00
|
|
|
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
2007-11-17 09:18:59 +01:00
|
|
|
break;
|
2007-10-14 18:29:21 +02:00
|
|
|
case 0x01c00f00: /* MBus port address register */
|
2008-02-24 15:10:06 +01:00
|
|
|
if (size == 8)
|
|
|
|
ret = env->mxccregs[7];
|
|
|
|
else
|
|
|
|
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
2007-10-14 18:29:21 +02:00
|
|
|
break;
|
|
|
|
default:
|
2008-02-24 15:10:06 +01:00
|
|
|
DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
|
2007-10-14 18:29:21 +02:00
|
|
|
break;
|
|
|
|
}
|
2008-02-24 15:10:06 +01:00
|
|
|
DPRINTF_MXCC("asi = %d, size = %d, sign = %d, addr = %08x -> ret = %08x,"
|
|
|
|
"addr = %08x\n", asi, size, sign, last_addr, ret, addr);
|
2007-10-14 18:29:21 +02:00
|
|
|
#ifdef DEBUG_MXCC
|
|
|
|
dump_mxcc(env);
|
|
|
|
#endif
|
2007-05-17 21:30:10 +02:00
|
|
|
break;
|
2004-09-30 23:55:55 +02:00
|
|
|
case 3: /* MMU probe */
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
|
|
|
int mmulev;
|
|
|
|
|
2008-02-24 15:10:06 +01:00
|
|
|
mmulev = (addr >> 8) & 15;
|
2007-09-20 16:54:22 +02:00
|
|
|
if (mmulev > 4)
|
|
|
|
ret = 0;
|
2008-02-24 15:10:06 +01:00
|
|
|
else
|
|
|
|
ret = mmu_probe(env, addr, mmulev);
|
|
|
|
DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
|
|
|
|
addr, mmulev, ret);
|
2007-09-20 16:54:22 +02:00
|
|
|
}
|
|
|
|
break;
|
2004-09-30 23:55:55 +02:00
|
|
|
case 4: /* read MMU regs */
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
2008-02-24 15:10:06 +01:00
|
|
|
int reg = (addr >> 8) & 0x1f;
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2007-09-20 16:54:22 +02:00
|
|
|
ret = env->mmuregs[reg];
|
|
|
|
if (reg == 3) /* Fault status cleared on read */
|
2007-11-25 13:43:10 +01:00
|
|
|
env->mmuregs[3] = 0;
|
|
|
|
else if (reg == 0x13) /* Fault status read */
|
|
|
|
ret = env->mmuregs[3];
|
|
|
|
else if (reg == 0x14) /* Fault address read */
|
|
|
|
ret = env->mmuregs[4];
|
2008-02-24 15:10:06 +01:00
|
|
|
DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
|
2007-09-20 16:54:22 +02:00
|
|
|
}
|
|
|
|
break;
|
2008-01-01 18:07:39 +01:00
|
|
|
case 5: // Turbosparc ITLB Diagnostic
|
|
|
|
case 6: // Turbosparc DTLB Diagnostic
|
|
|
|
case 7: // Turbosparc IOTLB Diagnostic
|
|
|
|
break;
|
2007-05-17 21:30:10 +02:00
|
|
|
case 9: /* Supervisor code access */
|
|
|
|
switch(size) {
|
|
|
|
case 1:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldub_code(addr);
|
2007-05-17 21:30:10 +02:00
|
|
|
break;
|
|
|
|
case 2:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = lduw_code(addr & ~1);
|
2007-05-17 21:30:10 +02:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case 4:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldl_code(addr & ~3);
|
2007-05-17 21:30:10 +02:00
|
|
|
break;
|
|
|
|
case 8:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldq_code(addr & ~7);
|
2007-05-17 21:30:10 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
2007-09-21 21:10:53 +02:00
|
|
|
case 0xa: /* User data access */
|
|
|
|
switch(size) {
|
|
|
|
case 1:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldub_user(addr);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
case 2:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = lduw_user(addr & ~1);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case 4:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldl_user(addr & ~3);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
case 8:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldq_user(addr & ~7);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 0xb: /* Supervisor data access */
|
|
|
|
switch(size) {
|
|
|
|
case 1:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldub_kernel(addr);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
case 2:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = lduw_kernel(addr & ~1);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case 4:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldl_kernel(addr & ~3);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
case 8:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldq_kernel(addr & ~7);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
2007-05-17 21:30:10 +02:00
|
|
|
case 0xc: /* I-cache tag */
|
|
|
|
case 0xd: /* I-cache data */
|
|
|
|
case 0xe: /* D-cache tag */
|
|
|
|
case 0xf: /* D-cache data */
|
|
|
|
break;
|
|
|
|
case 0x20: /* MMU passthrough */
|
2005-10-30 21:49:44 +01:00
|
|
|
switch(size) {
|
|
|
|
case 1:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldub_phys(addr);
|
2005-10-30 21:49:44 +01:00
|
|
|
break;
|
|
|
|
case 2:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = lduw_phys(addr & ~1);
|
2005-10-30 21:49:44 +01:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case 4:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldl_phys(addr & ~3);
|
2005-10-30 21:49:44 +01:00
|
|
|
break;
|
2005-11-11 01:24:58 +01:00
|
|
|
case 8:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldq_phys(addr & ~7);
|
2007-09-20 16:54:22 +02:00
|
|
|
break;
|
2005-10-30 21:49:44 +01:00
|
|
|
}
|
2007-09-20 16:54:22 +02:00
|
|
|
break;
|
2007-12-28 21:57:43 +01:00
|
|
|
case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
|
2007-05-19 14:58:30 +02:00
|
|
|
switch(size) {
|
|
|
|
case 1:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldub_phys((target_phys_addr_t)addr
|
2007-05-19 14:58:30 +02:00
|
|
|
| ((target_phys_addr_t)(asi & 0xf) << 32));
|
|
|
|
break;
|
|
|
|
case 2:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = lduw_phys((target_phys_addr_t)(addr & ~1)
|
2007-05-19 14:58:30 +02:00
|
|
|
| ((target_phys_addr_t)(asi & 0xf) << 32));
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case 4:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldl_phys((target_phys_addr_t)(addr & ~3)
|
2007-05-19 14:58:30 +02:00
|
|
|
| ((target_phys_addr_t)(asi & 0xf) << 32));
|
|
|
|
break;
|
|
|
|
case 8:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldq_phys((target_phys_addr_t)(addr & ~7)
|
2007-05-19 14:58:30 +02:00
|
|
|
| ((target_phys_addr_t)(asi & 0xf) << 32));
|
2007-09-20 16:54:22 +02:00
|
|
|
break;
|
2007-05-19 14:58:30 +02:00
|
|
|
}
|
2007-09-20 16:54:22 +02:00
|
|
|
break;
|
2008-01-01 18:07:39 +01:00
|
|
|
case 0x30: // Turbosparc secondary cache diagnostic
|
|
|
|
case 0x31: // Turbosparc RAM snoop
|
|
|
|
case 0x32: // Turbosparc page table descriptor diagnostic
|
2007-12-10 20:58:20 +01:00
|
|
|
case 0x39: /* data cache diagnostic register */
|
|
|
|
ret = 0;
|
|
|
|
break;
|
2008-01-01 18:07:39 +01:00
|
|
|
case 8: /* User code access, XXX */
|
2004-09-30 23:55:55 +02:00
|
|
|
default:
|
2008-02-24 15:10:06 +01:00
|
|
|
do_unassigned_access(addr, 0, 0, asi);
|
2007-09-20 16:54:22 +02:00
|
|
|
ret = 0;
|
|
|
|
break;
|
2004-09-30 23:55:55 +02:00
|
|
|
}
|
2007-09-21 21:10:53 +02:00
|
|
|
if (sign) {
|
|
|
|
switch(size) {
|
|
|
|
case 1:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = (int8_t) ret;
|
2007-09-23 13:40:57 +02:00
|
|
|
break;
|
2007-09-21 21:10:53 +02:00
|
|
|
case 2:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = (int16_t) ret;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
ret = (int32_t) ret;
|
2007-09-23 13:40:57 +02:00
|
|
|
break;
|
2007-09-21 21:10:53 +02:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2007-12-28 19:50:23 +01:00
|
|
|
#ifdef DEBUG_ASI
|
2008-02-24 15:10:06 +01:00
|
|
|
dump_asi("read ", last_addr, asi, size, ret);
|
2007-12-28 19:50:23 +01:00
|
|
|
#endif
|
2008-02-24 15:10:06 +01:00
|
|
|
return ret;
|
2004-09-30 23:55:55 +02:00
|
|
|
}
|
|
|
|
|
2008-02-24 15:10:06 +01:00
|
|
|
void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
|
2004-09-30 23:55:55 +02:00
|
|
|
{
|
|
|
|
switch(asi) {
|
2007-05-17 21:30:10 +02:00
|
|
|
case 2: /* SuperSparc MXCC registers */
|
2008-02-24 15:10:06 +01:00
|
|
|
switch (addr) {
|
2007-10-14 18:29:21 +02:00
|
|
|
case 0x01c00000: /* MXCC stream data register 0 */
|
|
|
|
if (size == 8)
|
2008-02-24 15:10:06 +01:00
|
|
|
env->mxccdata[0] = val;
|
2007-10-14 18:29:21 +02:00
|
|
|
else
|
2008-02-24 15:10:06 +01:00
|
|
|
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
2007-10-14 18:29:21 +02:00
|
|
|
break;
|
|
|
|
case 0x01c00008: /* MXCC stream data register 1 */
|
|
|
|
if (size == 8)
|
2008-02-24 15:10:06 +01:00
|
|
|
env->mxccdata[1] = val;
|
2007-10-14 18:29:21 +02:00
|
|
|
else
|
2008-02-24 15:10:06 +01:00
|
|
|
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
2007-10-14 18:29:21 +02:00
|
|
|
break;
|
|
|
|
case 0x01c00010: /* MXCC stream data register 2 */
|
|
|
|
if (size == 8)
|
2008-02-24 15:10:06 +01:00
|
|
|
env->mxccdata[2] = val;
|
2007-10-14 18:29:21 +02:00
|
|
|
else
|
2008-02-24 15:10:06 +01:00
|
|
|
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
2007-10-14 18:29:21 +02:00
|
|
|
break;
|
|
|
|
case 0x01c00018: /* MXCC stream data register 3 */
|
|
|
|
if (size == 8)
|
2008-02-24 15:10:06 +01:00
|
|
|
env->mxccdata[3] = val;
|
2007-10-14 18:29:21 +02:00
|
|
|
else
|
2008-02-24 15:10:06 +01:00
|
|
|
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
2007-10-14 18:29:21 +02:00
|
|
|
break;
|
|
|
|
case 0x01c00100: /* MXCC stream source */
|
|
|
|
if (size == 8)
|
2008-02-24 15:10:06 +01:00
|
|
|
env->mxccregs[0] = val;
|
2007-10-14 18:29:21 +02:00
|
|
|
else
|
2008-02-24 15:10:06 +01:00
|
|
|
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
2007-10-14 18:29:21 +02:00
|
|
|
env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0);
|
|
|
|
env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 8);
|
|
|
|
env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16);
|
|
|
|
env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 24);
|
|
|
|
break;
|
|
|
|
case 0x01c00200: /* MXCC stream destination */
|
|
|
|
if (size == 8)
|
2008-02-24 15:10:06 +01:00
|
|
|
env->mxccregs[1] = val;
|
2007-10-14 18:29:21 +02:00
|
|
|
else
|
2008-02-24 15:10:06 +01:00
|
|
|
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
2007-10-14 18:29:21 +02:00
|
|
|
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]);
|
|
|
|
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, env->mxccdata[1]);
|
|
|
|
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]);
|
|
|
|
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, env->mxccdata[3]);
|
|
|
|
break;
|
|
|
|
case 0x01c00a00: /* MXCC control register */
|
|
|
|
if (size == 8)
|
2008-02-24 15:10:06 +01:00
|
|
|
env->mxccregs[3] = val;
|
2007-10-14 18:29:21 +02:00
|
|
|
else
|
2008-02-24 15:10:06 +01:00
|
|
|
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
2007-10-14 18:29:21 +02:00
|
|
|
break;
|
|
|
|
case 0x01c00a04: /* MXCC control register */
|
|
|
|
if (size == 4)
|
2008-02-24 15:10:06 +01:00
|
|
|
env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL) | val;
|
2007-10-14 18:29:21 +02:00
|
|
|
else
|
2008-02-24 15:10:06 +01:00
|
|
|
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
2007-10-14 18:29:21 +02:00
|
|
|
break;
|
|
|
|
case 0x01c00e00: /* MXCC error register */
|
2007-11-17 09:19:57 +01:00
|
|
|
// writing a 1 bit clears the error
|
2007-10-14 18:29:21 +02:00
|
|
|
if (size == 8)
|
2008-02-24 15:10:06 +01:00
|
|
|
env->mxccregs[6] &= ~val;
|
2007-10-14 18:29:21 +02:00
|
|
|
else
|
2008-02-24 15:10:06 +01:00
|
|
|
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
2007-10-14 18:29:21 +02:00
|
|
|
break;
|
|
|
|
case 0x01c00f00: /* MBus port address register */
|
|
|
|
if (size == 8)
|
2008-02-24 15:10:06 +01:00
|
|
|
env->mxccregs[7] = val;
|
2007-10-14 18:29:21 +02:00
|
|
|
else
|
2008-02-24 15:10:06 +01:00
|
|
|
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
2007-10-14 18:29:21 +02:00
|
|
|
break;
|
|
|
|
default:
|
2008-02-24 15:10:06 +01:00
|
|
|
DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
|
2007-10-14 18:29:21 +02:00
|
|
|
break;
|
|
|
|
}
|
2008-02-24 15:10:06 +01:00
|
|
|
DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi, size, addr, val);
|
2007-10-14 18:29:21 +02:00
|
|
|
#ifdef DEBUG_MXCC
|
|
|
|
dump_mxcc(env);
|
|
|
|
#endif
|
2007-05-17 21:30:10 +02:00
|
|
|
break;
|
2004-09-30 23:55:55 +02:00
|
|
|
case 3: /* MMU flush */
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
|
|
|
int mmulev;
|
2004-12-20 00:18:01 +01:00
|
|
|
|
2008-02-24 15:10:06 +01:00
|
|
|
mmulev = (addr >> 8) & 15;
|
2007-10-14 18:29:21 +02:00
|
|
|
DPRINTF_MMU("mmu flush level %d\n", mmulev);
|
2007-09-20 16:54:22 +02:00
|
|
|
switch (mmulev) {
|
|
|
|
case 0: // flush page
|
2008-02-24 15:10:06 +01:00
|
|
|
tlb_flush_page(env, addr & 0xfffff000);
|
2007-09-20 16:54:22 +02:00
|
|
|
break;
|
|
|
|
case 1: // flush segment (256k)
|
|
|
|
case 2: // flush region (16M)
|
|
|
|
case 3: // flush context (4G)
|
|
|
|
case 4: // flush entire
|
|
|
|
tlb_flush(env, 1);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2005-02-22 20:14:33 +01:00
|
|
|
#ifdef DEBUG_MMU
|
2007-09-20 16:54:22 +02:00
|
|
|
dump_mmu(env);
|
2005-02-22 20:14:33 +01:00
|
|
|
#endif
|
2007-09-20 16:54:22 +02:00
|
|
|
}
|
2007-12-28 19:50:23 +01:00
|
|
|
break;
|
2004-09-30 23:55:55 +02:00
|
|
|
case 4: /* write MMU regs */
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
2008-02-24 15:10:06 +01:00
|
|
|
int reg = (addr >> 8) & 0x1f;
|
2007-09-20 16:54:22 +02:00
|
|
|
uint32_t oldreg;
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2007-09-20 16:54:22 +02:00
|
|
|
oldreg = env->mmuregs[reg];
|
2005-02-22 20:14:33 +01:00
|
|
|
switch(reg) {
|
2008-02-11 19:27:33 +01:00
|
|
|
case 0: // Control Register
|
2007-11-25 13:43:10 +01:00
|
|
|
env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
|
2008-02-24 15:10:06 +01:00
|
|
|
(val & 0x00ffffff);
|
2007-09-20 16:54:22 +02:00
|
|
|
// Mappings generated during no-fault mode or MMU
|
|
|
|
// disabled mode are invalid in normal mode
|
2007-11-25 13:43:10 +01:00
|
|
|
if ((oldreg & (MMU_E | MMU_NF | env->mmu_bm)) !=
|
|
|
|
(env->mmuregs[reg] & (MMU_E | MMU_NF | env->mmu_bm)))
|
2005-02-22 20:14:33 +01:00
|
|
|
tlb_flush(env, 1);
|
|
|
|
break;
|
2008-02-11 19:27:33 +01:00
|
|
|
case 1: // Context Table Pointer Register
|
2008-02-24 15:10:06 +01:00
|
|
|
env->mmuregs[reg] = val & env->mmu_ctpr_mask;
|
2008-02-11 19:27:33 +01:00
|
|
|
break;
|
|
|
|
case 2: // Context Register
|
2008-02-24 15:10:06 +01:00
|
|
|
env->mmuregs[reg] = val & env->mmu_cxr_mask;
|
2005-02-22 20:14:33 +01:00
|
|
|
if (oldreg != env->mmuregs[reg]) {
|
|
|
|
/* we flush when the MMU context changes because
|
|
|
|
QEMU has no MMU context support */
|
|
|
|
tlb_flush(env, 1);
|
|
|
|
}
|
|
|
|
break;
|
2008-02-11 19:27:33 +01:00
|
|
|
case 3: // Synchronous Fault Status Register with Clear
|
|
|
|
case 4: // Synchronous Fault Address Register
|
|
|
|
break;
|
|
|
|
case 0x10: // TLB Replacement Control Register
|
2008-02-24 15:10:06 +01:00
|
|
|
env->mmuregs[reg] = val & env->mmu_trcr_mask;
|
2005-02-22 20:14:33 +01:00
|
|
|
break;
|
2008-02-11 19:27:33 +01:00
|
|
|
case 0x13: // Synchronous Fault Status Register with Read and Clear
|
2008-02-24 15:10:06 +01:00
|
|
|
env->mmuregs[3] = val & env->mmu_sfsr_mask;
|
2007-11-25 13:43:10 +01:00
|
|
|
break;
|
2008-02-11 19:27:33 +01:00
|
|
|
case 0x14: // Synchronous Fault Address Register
|
2008-02-24 15:10:06 +01:00
|
|
|
env->mmuregs[4] = val;
|
2007-11-25 13:43:10 +01:00
|
|
|
break;
|
2005-02-22 20:14:33 +01:00
|
|
|
default:
|
2008-02-24 15:10:06 +01:00
|
|
|
env->mmuregs[reg] = val;
|
2005-02-22 20:14:33 +01:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (oldreg != env->mmuregs[reg]) {
|
2007-10-14 18:29:21 +02:00
|
|
|
DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
|
2005-02-22 20:14:33 +01:00
|
|
|
}
|
2007-10-14 18:29:21 +02:00
|
|
|
#ifdef DEBUG_MMU
|
2007-09-20 16:54:22 +02:00
|
|
|
dump_mmu(env);
|
2005-02-22 20:14:33 +01:00
|
|
|
#endif
|
2007-09-20 16:54:22 +02:00
|
|
|
}
|
2007-12-28 19:50:23 +01:00
|
|
|
break;
|
2008-01-01 18:07:39 +01:00
|
|
|
case 5: // Turbosparc ITLB Diagnostic
|
|
|
|
case 6: // Turbosparc DTLB Diagnostic
|
|
|
|
case 7: // Turbosparc IOTLB Diagnostic
|
|
|
|
break;
|
2007-09-21 21:10:53 +02:00
|
|
|
case 0xa: /* User data access */
|
|
|
|
switch(size) {
|
|
|
|
case 1:
|
2008-02-24 15:10:06 +01:00
|
|
|
stb_user(addr, val);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
case 2:
|
2008-02-24 15:10:06 +01:00
|
|
|
stw_user(addr & ~1, val);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case 4:
|
2008-02-24 15:10:06 +01:00
|
|
|
stl_user(addr & ~3, val);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
case 8:
|
2008-02-24 15:10:06 +01:00
|
|
|
stq_user(addr & ~7, val);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 0xb: /* Supervisor data access */
|
|
|
|
switch(size) {
|
|
|
|
case 1:
|
2008-02-24 15:10:06 +01:00
|
|
|
stb_kernel(addr, val);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
case 2:
|
2008-02-24 15:10:06 +01:00
|
|
|
stw_kernel(addr & ~1, val);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case 4:
|
2008-02-24 15:10:06 +01:00
|
|
|
stl_kernel(addr & ~3, val);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
case 8:
|
2008-02-24 15:10:06 +01:00
|
|
|
stq_kernel(addr & ~7, val);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
2007-05-17 21:30:10 +02:00
|
|
|
case 0xc: /* I-cache tag */
|
|
|
|
case 0xd: /* I-cache data */
|
|
|
|
case 0xe: /* D-cache tag */
|
|
|
|
case 0xf: /* D-cache data */
|
|
|
|
case 0x10: /* I/D-cache flush page */
|
|
|
|
case 0x11: /* I/D-cache flush segment */
|
|
|
|
case 0x12: /* I/D-cache flush region */
|
|
|
|
case 0x13: /* I/D-cache flush context */
|
|
|
|
case 0x14: /* I/D-cache flush user */
|
|
|
|
break;
|
2004-12-20 00:18:01 +01:00
|
|
|
case 0x17: /* Block copy, sta access */
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
2008-02-24 15:10:06 +01:00
|
|
|
// val = src
|
|
|
|
// addr = dst
|
2007-09-20 16:54:22 +02:00
|
|
|
// copy 32 bytes
|
2007-05-17 21:30:10 +02:00
|
|
|
unsigned int i;
|
2008-02-24 15:10:06 +01:00
|
|
|
uint32_t src = val & ~3, dst = addr & ~3, temp;
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2007-05-17 21:30:10 +02:00
|
|
|
for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
|
|
|
|
temp = ldl_kernel(src);
|
|
|
|
stl_kernel(dst, temp);
|
|
|
|
}
|
2007-09-20 16:54:22 +02:00
|
|
|
}
|
2007-12-28 19:50:23 +01:00
|
|
|
break;
|
2004-12-20 00:18:01 +01:00
|
|
|
case 0x1f: /* Block fill, stda access */
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
2008-02-24 15:10:06 +01:00
|
|
|
// addr = dst
|
|
|
|
// fill 32 bytes with val
|
2007-05-17 21:30:10 +02:00
|
|
|
unsigned int i;
|
2008-02-24 15:10:06 +01:00
|
|
|
uint32_t dst = addr & 7;
|
2007-05-17 21:30:10 +02:00
|
|
|
|
|
|
|
for (i = 0; i < 32; i += 8, dst += 8)
|
|
|
|
stq_kernel(dst, val);
|
2007-09-20 16:54:22 +02:00
|
|
|
}
|
2007-12-28 19:50:23 +01:00
|
|
|
break;
|
2007-05-17 21:30:10 +02:00
|
|
|
case 0x20: /* MMU passthrough */
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
2005-10-30 21:49:44 +01:00
|
|
|
switch(size) {
|
|
|
|
case 1:
|
2008-02-24 15:10:06 +01:00
|
|
|
stb_phys(addr, val);
|
2005-10-30 21:49:44 +01:00
|
|
|
break;
|
|
|
|
case 2:
|
2008-02-24 15:10:06 +01:00
|
|
|
stw_phys(addr & ~1, val);
|
2005-10-30 21:49:44 +01:00
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
default:
|
2008-02-24 15:10:06 +01:00
|
|
|
stl_phys(addr & ~3, val);
|
2005-10-30 21:49:44 +01:00
|
|
|
break;
|
2005-11-11 01:24:58 +01:00
|
|
|
case 8:
|
2008-02-24 15:10:06 +01:00
|
|
|
stq_phys(addr & ~7, val);
|
2005-11-11 01:24:58 +01:00
|
|
|
break;
|
2005-10-30 21:49:44 +01:00
|
|
|
}
|
2007-09-20 16:54:22 +02:00
|
|
|
}
|
2007-12-28 19:50:23 +01:00
|
|
|
break;
|
2008-01-01 18:07:39 +01:00
|
|
|
case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
2007-05-19 14:58:30 +02:00
|
|
|
switch(size) {
|
|
|
|
case 1:
|
2008-02-24 15:10:06 +01:00
|
|
|
stb_phys((target_phys_addr_t)addr
|
|
|
|
| ((target_phys_addr_t)(asi & 0xf) << 32), val);
|
2007-05-19 14:58:30 +02:00
|
|
|
break;
|
|
|
|
case 2:
|
2008-02-24 15:10:06 +01:00
|
|
|
stw_phys((target_phys_addr_t)(addr & ~1)
|
|
|
|
| ((target_phys_addr_t)(asi & 0xf) << 32), val);
|
2007-05-19 14:58:30 +02:00
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
default:
|
2008-02-24 15:10:06 +01:00
|
|
|
stl_phys((target_phys_addr_t)(addr & ~3)
|
|
|
|
| ((target_phys_addr_t)(asi & 0xf) << 32), val);
|
2007-05-19 14:58:30 +02:00
|
|
|
break;
|
|
|
|
case 8:
|
2008-02-24 15:10:06 +01:00
|
|
|
stq_phys((target_phys_addr_t)(addr & ~7)
|
|
|
|
| ((target_phys_addr_t)(asi & 0xf) << 32), val);
|
2007-05-19 14:58:30 +02:00
|
|
|
break;
|
|
|
|
}
|
2007-09-20 16:54:22 +02:00
|
|
|
}
|
2007-12-28 19:50:23 +01:00
|
|
|
break;
|
2008-01-01 18:07:39 +01:00
|
|
|
case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
|
|
|
|
case 0x31: // store buffer data, Ross RT620 I-cache flush or
|
|
|
|
// Turbosparc snoop RAM
|
|
|
|
case 0x32: // store buffer control or Turbosparc page table descriptor diagnostic
|
2007-05-17 21:30:10 +02:00
|
|
|
case 0x36: /* I-cache flash clear */
|
|
|
|
case 0x37: /* D-cache flash clear */
|
2007-12-10 20:58:20 +01:00
|
|
|
case 0x38: /* breakpoint diagnostics */
|
|
|
|
case 0x4c: /* breakpoint action */
|
2007-05-17 21:30:10 +02:00
|
|
|
break;
|
2008-01-01 18:07:39 +01:00
|
|
|
case 8: /* User code access, XXX */
|
2007-05-17 21:30:10 +02:00
|
|
|
case 9: /* Supervisor code access, XXX */
|
2004-09-30 23:55:55 +02:00
|
|
|
default:
|
2008-02-24 15:10:06 +01:00
|
|
|
do_unassigned_access(addr, 1, 0, asi);
|
2007-12-28 19:50:23 +01:00
|
|
|
break;
|
2004-09-30 23:55:55 +02:00
|
|
|
}
|
2007-12-28 19:50:23 +01:00
|
|
|
#ifdef DEBUG_ASI
|
2008-02-24 15:10:06 +01:00
|
|
|
dump_asi("write", addr, asi, size, val);
|
2007-12-28 19:50:23 +01:00
|
|
|
#endif
|
2004-09-30 23:55:55 +02:00
|
|
|
}
|
|
|
|
|
2007-09-21 21:10:53 +02:00
|
|
|
#endif /* CONFIG_USER_ONLY */
|
|
|
|
#else /* TARGET_SPARC64 */
|
|
|
|
|
|
|
|
#ifdef CONFIG_USER_ONLY
|
2008-02-24 15:10:06 +01:00
|
|
|
uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
|
2007-09-21 21:10:53 +02:00
|
|
|
{
|
|
|
|
uint64_t ret = 0;
|
2008-02-24 15:10:06 +01:00
|
|
|
#if defined(DEBUG_ASI)
|
|
|
|
target_ulong last_addr = addr;
|
|
|
|
#endif
|
2007-09-21 21:10:53 +02:00
|
|
|
|
|
|
|
if (asi < 0x80)
|
|
|
|
raise_exception(TT_PRIV_ACT);
|
|
|
|
|
|
|
|
switch (asi) {
|
|
|
|
case 0x80: // Primary
|
|
|
|
case 0x82: // Primary no-fault
|
|
|
|
case 0x88: // Primary LE
|
|
|
|
case 0x8a: // Primary no-fault LE
|
|
|
|
{
|
|
|
|
switch(size) {
|
|
|
|
case 1:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldub_raw(addr);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
case 2:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = lduw_raw(addr & ~1);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
case 4:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldl_raw(addr & ~3);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case 8:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldq_raw(addr & ~7);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 0x81: // Secondary
|
|
|
|
case 0x83: // Secondary no-fault
|
|
|
|
case 0x89: // Secondary LE
|
|
|
|
case 0x8b: // Secondary no-fault LE
|
|
|
|
// XXX
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Convert from little endian */
|
|
|
|
switch (asi) {
|
|
|
|
case 0x88: // Primary LE
|
|
|
|
case 0x89: // Secondary LE
|
|
|
|
case 0x8a: // Primary no-fault LE
|
|
|
|
case 0x8b: // Secondary no-fault LE
|
|
|
|
switch(size) {
|
|
|
|
case 2:
|
|
|
|
ret = bswap16(ret);
|
2007-09-23 13:40:57 +02:00
|
|
|
break;
|
2007-09-21 21:10:53 +02:00
|
|
|
case 4:
|
|
|
|
ret = bswap32(ret);
|
2007-09-23 13:40:57 +02:00
|
|
|
break;
|
2007-09-21 21:10:53 +02:00
|
|
|
case 8:
|
|
|
|
ret = bswap64(ret);
|
2007-09-23 13:40:57 +02:00
|
|
|
break;
|
2007-09-21 21:10:53 +02:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Convert to signed number */
|
|
|
|
if (sign) {
|
|
|
|
switch(size) {
|
|
|
|
case 1:
|
|
|
|
ret = (int8_t) ret;
|
2007-09-23 13:40:57 +02:00
|
|
|
break;
|
2007-09-21 21:10:53 +02:00
|
|
|
case 2:
|
|
|
|
ret = (int16_t) ret;
|
2007-09-23 13:40:57 +02:00
|
|
|
break;
|
2007-09-21 21:10:53 +02:00
|
|
|
case 4:
|
|
|
|
ret = (int32_t) ret;
|
2007-09-23 13:40:57 +02:00
|
|
|
break;
|
2007-09-21 21:10:53 +02:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2008-02-24 15:10:06 +01:00
|
|
|
#ifdef DEBUG_ASI
|
|
|
|
dump_asi("read ", last_addr, asi, size, ret);
|
|
|
|
#endif
|
|
|
|
return ret;
|
2007-09-21 21:10:53 +02:00
|
|
|
}
|
|
|
|
|
2008-02-24 15:10:06 +01:00
|
|
|
void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
|
2007-09-21 21:10:53 +02:00
|
|
|
{
|
2008-02-24 15:10:06 +01:00
|
|
|
#ifdef DEBUG_ASI
|
|
|
|
dump_asi("write", addr, asi, size, val);
|
|
|
|
#endif
|
2007-09-21 21:10:53 +02:00
|
|
|
if (asi < 0x80)
|
|
|
|
raise_exception(TT_PRIV_ACT);
|
|
|
|
|
|
|
|
/* Convert to little endian */
|
|
|
|
switch (asi) {
|
|
|
|
case 0x88: // Primary LE
|
|
|
|
case 0x89: // Secondary LE
|
|
|
|
switch(size) {
|
|
|
|
case 2:
|
2008-02-24 15:10:06 +01:00
|
|
|
addr = bswap16(addr);
|
2007-09-23 13:40:57 +02:00
|
|
|
break;
|
2007-09-21 21:10:53 +02:00
|
|
|
case 4:
|
2008-02-24 15:10:06 +01:00
|
|
|
addr = bswap32(addr);
|
2007-09-23 13:40:57 +02:00
|
|
|
break;
|
2007-09-21 21:10:53 +02:00
|
|
|
case 8:
|
2008-02-24 15:10:06 +01:00
|
|
|
addr = bswap64(addr);
|
2007-09-23 13:40:57 +02:00
|
|
|
break;
|
2007-09-21 21:10:53 +02:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch(asi) {
|
|
|
|
case 0x80: // Primary
|
|
|
|
case 0x88: // Primary LE
|
|
|
|
{
|
|
|
|
switch(size) {
|
|
|
|
case 1:
|
2008-02-24 15:10:06 +01:00
|
|
|
stb_raw(addr, val);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
case 2:
|
2008-02-24 15:10:06 +01:00
|
|
|
stw_raw(addr & ~1, val);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
case 4:
|
2008-02-24 15:10:06 +01:00
|
|
|
stl_raw(addr & ~3, val);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
default:
|
2008-02-24 15:10:06 +01:00
|
|
|
stq_raw(addr & ~7, val);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 0x81: // Secondary
|
|
|
|
case 0x89: // Secondary LE
|
|
|
|
// XXX
|
|
|
|
return;
|
|
|
|
|
|
|
|
case 0x82: // Primary no-fault, RO
|
|
|
|
case 0x83: // Secondary no-fault, RO
|
|
|
|
case 0x8a: // Primary no-fault LE, RO
|
|
|
|
case 0x8b: // Secondary no-fault LE, RO
|
|
|
|
default:
|
2008-02-24 15:10:06 +01:00
|
|
|
do_unassigned_access(addr, 1, 0, 1);
|
2007-09-21 21:10:53 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#else /* CONFIG_USER_ONLY */
|
2005-07-02 16:31:34 +02:00
|
|
|
|
2008-02-24 15:10:06 +01:00
|
|
|
uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
|
2005-07-02 16:31:34 +02:00
|
|
|
{
|
2005-07-23 16:27:54 +02:00
|
|
|
uint64_t ret = 0;
|
2008-02-24 15:10:06 +01:00
|
|
|
#if defined(DEBUG_ASI)
|
|
|
|
target_ulong last_addr = addr;
|
|
|
|
#endif
|
2005-07-02 16:31:34 +02:00
|
|
|
|
2007-10-14 19:07:21 +02:00
|
|
|
if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
|
2007-10-20 09:09:08 +02:00
|
|
|
|| (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
|
2007-09-20 16:54:22 +02:00
|
|
|
raise_exception(TT_PRIV_ACT);
|
2005-07-02 16:31:34 +02:00
|
|
|
|
|
|
|
switch (asi) {
|
2007-09-21 21:10:53 +02:00
|
|
|
case 0x10: // As if user primary
|
|
|
|
case 0x18: // As if user primary LE
|
|
|
|
case 0x80: // Primary
|
|
|
|
case 0x82: // Primary no-fault
|
|
|
|
case 0x88: // Primary LE
|
|
|
|
case 0x8a: // Primary no-fault LE
|
|
|
|
if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
|
2007-10-14 19:07:21 +02:00
|
|
|
if (env->hpstate & HS_PRIV) {
|
|
|
|
switch(size) {
|
|
|
|
case 1:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldub_hypv(addr);
|
2007-10-14 19:07:21 +02:00
|
|
|
break;
|
|
|
|
case 2:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = lduw_hypv(addr & ~1);
|
2007-10-14 19:07:21 +02:00
|
|
|
break;
|
|
|
|
case 4:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldl_hypv(addr & ~3);
|
2007-10-14 19:07:21 +02:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case 8:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldq_hypv(addr & ~7);
|
2007-10-14 19:07:21 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
switch(size) {
|
|
|
|
case 1:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldub_kernel(addr);
|
2007-10-14 19:07:21 +02:00
|
|
|
break;
|
|
|
|
case 2:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = lduw_kernel(addr & ~1);
|
2007-10-14 19:07:21 +02:00
|
|
|
break;
|
|
|
|
case 4:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldl_kernel(addr & ~3);
|
2007-10-14 19:07:21 +02:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case 8:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldq_kernel(addr & ~7);
|
2007-10-14 19:07:21 +02:00
|
|
|
break;
|
|
|
|
}
|
2007-09-21 21:10:53 +02:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
switch(size) {
|
|
|
|
case 1:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldub_user(addr);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
case 2:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = lduw_user(addr & ~1);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
case 4:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldl_user(addr & ~3);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case 8:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldq_user(addr & ~7);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
2005-07-02 16:31:34 +02:00
|
|
|
case 0x14: // Bypass
|
|
|
|
case 0x15: // Bypass, non-cacheable
|
2007-09-21 21:10:53 +02:00
|
|
|
case 0x1c: // Bypass LE
|
|
|
|
case 0x1d: // Bypass, non-cacheable LE
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
2005-10-30 21:49:44 +01:00
|
|
|
switch(size) {
|
|
|
|
case 1:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldub_phys(addr);
|
2005-10-30 21:49:44 +01:00
|
|
|
break;
|
|
|
|
case 2:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = lduw_phys(addr & ~1);
|
2005-10-30 21:49:44 +01:00
|
|
|
break;
|
|
|
|
case 4:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldl_phys(addr & ~3);
|
2005-10-30 21:49:44 +01:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case 8:
|
2008-02-24 15:10:06 +01:00
|
|
|
ret = ldq_phys(addr & ~7);
|
2005-10-30 21:49:44 +01:00
|
|
|
break;
|
|
|
|
}
|
2007-09-20 16:54:22 +02:00
|
|
|
break;
|
|
|
|
}
|
2005-07-23 16:27:54 +02:00
|
|
|
case 0x04: // Nucleus
|
|
|
|
case 0x0c: // Nucleus Little Endian (LE)
|
|
|
|
case 0x11: // As if user secondary
|
|
|
|
case 0x19: // As if user secondary LE
|
|
|
|
case 0x24: // Nucleus quad LDD 128 bit atomic
|
|
|
|
case 0x2c: // Nucleus quad LDD 128 bit atomic
|
|
|
|
case 0x4a: // UPA config
|
2007-09-21 21:10:53 +02:00
|
|
|
case 0x81: // Secondary
|
2005-07-23 16:27:54 +02:00
|
|
|
case 0x83: // Secondary no-fault
|
|
|
|
case 0x89: // Secondary LE
|
|
|
|
case 0x8b: // Secondary no-fault LE
|
2007-09-20 16:54:22 +02:00
|
|
|
// XXX
|
|
|
|
break;
|
2005-07-02 16:31:34 +02:00
|
|
|
case 0x45: // LSU
|
2007-09-20 16:54:22 +02:00
|
|
|
ret = env->lsu;
|
|
|
|
break;
|
2005-07-02 16:31:34 +02:00
|
|
|
case 0x50: // I-MMU regs
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
2008-02-24 15:10:06 +01:00
|
|
|
int reg = (addr >> 3) & 0xf;
|
2005-07-02 16:31:34 +02:00
|
|
|
|
2007-09-20 16:54:22 +02:00
|
|
|
ret = env->immuregs[reg];
|
|
|
|
break;
|
|
|
|
}
|
2005-07-02 16:31:34 +02:00
|
|
|
case 0x51: // I-MMU 8k TSB pointer
|
|
|
|
case 0x52: // I-MMU 64k TSB pointer
|
|
|
|
case 0x55: // I-MMU data access
|
2007-09-20 16:54:22 +02:00
|
|
|
// XXX
|
|
|
|
break;
|
2005-07-23 16:27:54 +02:00
|
|
|
case 0x56: // I-MMU tag read
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
for (i = 0; i < 64; i++) {
|
|
|
|
// Valid, ctx match, vaddr match
|
|
|
|
if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
|
2008-02-24 15:10:06 +01:00
|
|
|
env->itlb_tag[i] == addr) {
|
2007-09-20 16:54:22 +02:00
|
|
|
ret = env->itlb_tag[i];
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2005-07-02 16:31:34 +02:00
|
|
|
case 0x58: // D-MMU regs
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
2008-02-24 15:10:06 +01:00
|
|
|
int reg = (addr >> 3) & 0xf;
|
2005-07-02 16:31:34 +02:00
|
|
|
|
2007-09-20 16:54:22 +02:00
|
|
|
ret = env->dmmuregs[reg];
|
|
|
|
break;
|
|
|
|
}
|
2005-07-23 16:27:54 +02:00
|
|
|
case 0x5e: // D-MMU tag read
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
for (i = 0; i < 64; i++) {
|
|
|
|
// Valid, ctx match, vaddr match
|
|
|
|
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
|
2008-02-24 15:10:06 +01:00
|
|
|
env->dtlb_tag[i] == addr) {
|
2007-09-20 16:54:22 +02:00
|
|
|
ret = env->dtlb_tag[i];
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2005-07-02 16:31:34 +02:00
|
|
|
case 0x59: // D-MMU 8k TSB pointer
|
|
|
|
case 0x5a: // D-MMU 64k TSB pointer
|
|
|
|
case 0x5b: // D-MMU data pointer
|
|
|
|
case 0x5d: // D-MMU data access
|
2005-07-23 16:27:54 +02:00
|
|
|
case 0x48: // Interrupt dispatch, RO
|
|
|
|
case 0x49: // Interrupt data receive
|
|
|
|
case 0x7f: // Incoming interrupt vector, RO
|
2007-09-20 16:54:22 +02:00
|
|
|
// XXX
|
|
|
|
break;
|
2005-07-02 16:31:34 +02:00
|
|
|
case 0x54: // I-MMU data in, WO
|
|
|
|
case 0x57: // I-MMU demap, WO
|
|
|
|
case 0x5c: // D-MMU data in, WO
|
|
|
|
case 0x5f: // D-MMU demap, WO
|
2005-07-23 16:27:54 +02:00
|
|
|
case 0x77: // Interrupt vector, WO
|
2005-07-02 16:31:34 +02:00
|
|
|
default:
|
2008-02-24 15:10:06 +01:00
|
|
|
do_unassigned_access(addr, 0, 0, 1);
|
2007-09-20 16:54:22 +02:00
|
|
|
ret = 0;
|
|
|
|
break;
|
2005-07-02 16:31:34 +02:00
|
|
|
}
|
2007-09-21 21:10:53 +02:00
|
|
|
|
|
|
|
/* Convert from little endian */
|
|
|
|
switch (asi) {
|
|
|
|
case 0x0c: // Nucleus Little Endian (LE)
|
|
|
|
case 0x18: // As if user primary LE
|
|
|
|
case 0x19: // As if user secondary LE
|
|
|
|
case 0x1c: // Bypass LE
|
|
|
|
case 0x1d: // Bypass, non-cacheable LE
|
|
|
|
case 0x88: // Primary LE
|
|
|
|
case 0x89: // Secondary LE
|
|
|
|
case 0x8a: // Primary no-fault LE
|
|
|
|
case 0x8b: // Secondary no-fault LE
|
|
|
|
switch(size) {
|
|
|
|
case 2:
|
|
|
|
ret = bswap16(ret);
|
2007-09-23 13:40:57 +02:00
|
|
|
break;
|
2007-09-21 21:10:53 +02:00
|
|
|
case 4:
|
|
|
|
ret = bswap32(ret);
|
2007-09-23 13:40:57 +02:00
|
|
|
break;
|
2007-09-21 21:10:53 +02:00
|
|
|
case 8:
|
|
|
|
ret = bswap64(ret);
|
2007-09-23 13:40:57 +02:00
|
|
|
break;
|
2007-09-21 21:10:53 +02:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Convert to signed number */
|
|
|
|
if (sign) {
|
|
|
|
switch(size) {
|
|
|
|
case 1:
|
|
|
|
ret = (int8_t) ret;
|
2007-09-23 13:40:57 +02:00
|
|
|
break;
|
2007-09-21 21:10:53 +02:00
|
|
|
case 2:
|
|
|
|
ret = (int16_t) ret;
|
2007-09-23 13:40:57 +02:00
|
|
|
break;
|
2007-09-21 21:10:53 +02:00
|
|
|
case 4:
|
|
|
|
ret = (int32_t) ret;
|
2007-09-23 13:40:57 +02:00
|
|
|
break;
|
2007-09-21 21:10:53 +02:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2008-02-24 15:10:06 +01:00
|
|
|
#ifdef DEBUG_ASI
|
|
|
|
dump_asi("read ", last_addr, asi, size, ret);
|
|
|
|
#endif
|
|
|
|
return ret;
|
2005-07-02 16:31:34 +02:00
|
|
|
}
|
|
|
|
|
2008-02-24 15:10:06 +01:00
|
|
|
void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
|
2005-07-02 16:31:34 +02:00
|
|
|
{
|
2008-02-24 15:10:06 +01:00
|
|
|
#ifdef DEBUG_ASI
|
|
|
|
dump_asi("write", addr, asi, size, val);
|
|
|
|
#endif
|
2007-10-14 19:07:21 +02:00
|
|
|
if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
|
2007-10-20 09:09:08 +02:00
|
|
|
|| (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
|
2007-09-20 16:54:22 +02:00
|
|
|
raise_exception(TT_PRIV_ACT);
|
2005-07-02 16:31:34 +02:00
|
|
|
|
2007-09-21 21:10:53 +02:00
|
|
|
/* Convert to little endian */
|
|
|
|
switch (asi) {
|
|
|
|
case 0x0c: // Nucleus Little Endian (LE)
|
|
|
|
case 0x18: // As if user primary LE
|
|
|
|
case 0x19: // As if user secondary LE
|
|
|
|
case 0x1c: // Bypass LE
|
|
|
|
case 0x1d: // Bypass, non-cacheable LE
|
|
|
|
case 0x88: // Primary LE
|
|
|
|
case 0x89: // Secondary LE
|
|
|
|
switch(size) {
|
|
|
|
case 2:
|
2008-02-24 15:10:06 +01:00
|
|
|
addr = bswap16(addr);
|
2007-09-23 13:40:57 +02:00
|
|
|
break;
|
2007-09-21 21:10:53 +02:00
|
|
|
case 4:
|
2008-02-24 15:10:06 +01:00
|
|
|
addr = bswap32(addr);
|
2007-09-23 13:40:57 +02:00
|
|
|
break;
|
2007-09-21 21:10:53 +02:00
|
|
|
case 8:
|
2008-02-24 15:10:06 +01:00
|
|
|
addr = bswap64(addr);
|
2007-09-23 13:40:57 +02:00
|
|
|
break;
|
2007-09-21 21:10:53 +02:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2005-07-02 16:31:34 +02:00
|
|
|
switch(asi) {
|
2007-09-21 21:10:53 +02:00
|
|
|
case 0x10: // As if user primary
|
|
|
|
case 0x18: // As if user primary LE
|
|
|
|
case 0x80: // Primary
|
|
|
|
case 0x88: // Primary LE
|
|
|
|
if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
|
2007-10-14 19:07:21 +02:00
|
|
|
if (env->hpstate & HS_PRIV) {
|
|
|
|
switch(size) {
|
|
|
|
case 1:
|
2008-02-24 15:10:06 +01:00
|
|
|
stb_hypv(addr, val);
|
2007-10-14 19:07:21 +02:00
|
|
|
break;
|
|
|
|
case 2:
|
2008-02-24 15:10:06 +01:00
|
|
|
stw_hypv(addr & ~1, val);
|
2007-10-14 19:07:21 +02:00
|
|
|
break;
|
|
|
|
case 4:
|
2008-02-24 15:10:06 +01:00
|
|
|
stl_hypv(addr & ~3, val);
|
2007-10-14 19:07:21 +02:00
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
default:
|
2008-02-24 15:10:06 +01:00
|
|
|
stq_hypv(addr & ~7, val);
|
2007-10-14 19:07:21 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
switch(size) {
|
|
|
|
case 1:
|
2008-02-24 15:10:06 +01:00
|
|
|
stb_kernel(addr, val);
|
2007-10-14 19:07:21 +02:00
|
|
|
break;
|
|
|
|
case 2:
|
2008-02-24 15:10:06 +01:00
|
|
|
stw_kernel(addr & ~1, val);
|
2007-10-14 19:07:21 +02:00
|
|
|
break;
|
|
|
|
case 4:
|
2008-02-24 15:10:06 +01:00
|
|
|
stl_kernel(addr & ~3, val);
|
2007-10-14 19:07:21 +02:00
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
default:
|
2008-02-24 15:10:06 +01:00
|
|
|
stq_kernel(addr & ~7, val);
|
2007-10-14 19:07:21 +02:00
|
|
|
break;
|
|
|
|
}
|
2007-09-21 21:10:53 +02:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
switch(size) {
|
|
|
|
case 1:
|
2008-02-24 15:10:06 +01:00
|
|
|
stb_user(addr, val);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
case 2:
|
2008-02-24 15:10:06 +01:00
|
|
|
stw_user(addr & ~1, val);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
case 4:
|
2008-02-24 15:10:06 +01:00
|
|
|
stl_user(addr & ~3, val);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
default:
|
2008-02-24 15:10:06 +01:00
|
|
|
stq_user(addr & ~7, val);
|
2007-09-21 21:10:53 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
2005-07-02 16:31:34 +02:00
|
|
|
case 0x14: // Bypass
|
|
|
|
case 0x15: // Bypass, non-cacheable
|
2007-09-21 21:10:53 +02:00
|
|
|
case 0x1c: // Bypass LE
|
|
|
|
case 0x1d: // Bypass, non-cacheable LE
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
2005-10-30 21:49:44 +01:00
|
|
|
switch(size) {
|
|
|
|
case 1:
|
2008-02-24 15:10:06 +01:00
|
|
|
stb_phys(addr, val);
|
2005-10-30 21:49:44 +01:00
|
|
|
break;
|
|
|
|
case 2:
|
2008-02-24 15:10:06 +01:00
|
|
|
stw_phys(addr & ~1, val);
|
2005-10-30 21:49:44 +01:00
|
|
|
break;
|
|
|
|
case 4:
|
2008-02-24 15:10:06 +01:00
|
|
|
stl_phys(addr & ~3, val);
|
2005-10-30 21:49:44 +01:00
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
default:
|
2008-02-24 15:10:06 +01:00
|
|
|
stq_phys(addr & ~7, val);
|
2005-10-30 21:49:44 +01:00
|
|
|
break;
|
|
|
|
}
|
2007-09-20 16:54:22 +02:00
|
|
|
}
|
|
|
|
return;
|
2005-07-23 16:27:54 +02:00
|
|
|
case 0x04: // Nucleus
|
|
|
|
case 0x0c: // Nucleus Little Endian (LE)
|
|
|
|
case 0x11: // As if user secondary
|
|
|
|
case 0x19: // As if user secondary LE
|
|
|
|
case 0x24: // Nucleus quad LDD 128 bit atomic
|
|
|
|
case 0x2c: // Nucleus quad LDD 128 bit atomic
|
|
|
|
case 0x4a: // UPA config
|
2007-10-01 19:07:58 +02:00
|
|
|
case 0x81: // Secondary
|
2005-07-23 16:27:54 +02:00
|
|
|
case 0x89: // Secondary LE
|
2007-09-20 16:54:22 +02:00
|
|
|
// XXX
|
|
|
|
return;
|
2005-07-02 16:31:34 +02:00
|
|
|
case 0x45: // LSU
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
|
|
|
uint64_t oldreg;
|
|
|
|
|
|
|
|
oldreg = env->lsu;
|
2008-02-24 15:10:06 +01:00
|
|
|
env->lsu = val & (DMMU_E | IMMU_E);
|
2007-09-20 16:54:22 +02:00
|
|
|
// Mappings generated during D/I MMU disabled mode are
|
|
|
|
// invalid in normal mode
|
|
|
|
if (oldreg != env->lsu) {
|
2007-10-14 18:29:21 +02:00
|
|
|
DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu);
|
2005-07-23 16:27:54 +02:00
|
|
|
#ifdef DEBUG_MMU
|
2007-09-20 16:54:22 +02:00
|
|
|
dump_mmu(env);
|
2005-07-23 16:27:54 +02:00
|
|
|
#endif
|
2007-09-20 16:54:22 +02:00
|
|
|
tlb_flush(env, 1);
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
2005-07-02 16:31:34 +02:00
|
|
|
case 0x50: // I-MMU regs
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
2008-02-24 15:10:06 +01:00
|
|
|
int reg = (addr >> 3) & 0xf;
|
2007-09-20 16:54:22 +02:00
|
|
|
uint64_t oldreg;
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2007-09-20 16:54:22 +02:00
|
|
|
oldreg = env->immuregs[reg];
|
2005-07-02 16:31:34 +02:00
|
|
|
switch(reg) {
|
|
|
|
case 0: // RO
|
|
|
|
case 4:
|
|
|
|
return;
|
|
|
|
case 1: // Not in I-MMU
|
|
|
|
case 2:
|
|
|
|
case 7:
|
|
|
|
case 8:
|
|
|
|
return;
|
|
|
|
case 3: // SFSR
|
2008-02-24 15:10:06 +01:00
|
|
|
if ((val & 1) == 0)
|
|
|
|
val = 0; // Clear SFSR
|
2005-07-02 16:31:34 +02:00
|
|
|
break;
|
|
|
|
case 5: // TSB access
|
|
|
|
case 6: // Tag access
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2008-02-24 15:10:06 +01:00
|
|
|
env->immuregs[reg] = val;
|
2005-07-02 16:31:34 +02:00
|
|
|
if (oldreg != env->immuregs[reg]) {
|
2007-10-14 18:29:21 +02:00
|
|
|
DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
|
2005-07-02 16:31:34 +02:00
|
|
|
}
|
2007-10-14 18:29:21 +02:00
|
|
|
#ifdef DEBUG_MMU
|
2007-09-20 16:54:22 +02:00
|
|
|
dump_mmu(env);
|
2005-07-02 16:31:34 +02:00
|
|
|
#endif
|
2007-09-20 16:54:22 +02:00
|
|
|
return;
|
|
|
|
}
|
2005-07-02 16:31:34 +02:00
|
|
|
case 0x54: // I-MMU data in
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
// Try finding an invalid entry
|
|
|
|
for (i = 0; i < 64; i++) {
|
|
|
|
if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
|
|
|
|
env->itlb_tag[i] = env->immuregs[6];
|
2008-02-24 15:10:06 +01:00
|
|
|
env->itlb_tte[i] = val;
|
2007-09-20 16:54:22 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// Try finding an unlocked entry
|
|
|
|
for (i = 0; i < 64; i++) {
|
|
|
|
if ((env->itlb_tte[i] & 0x40) == 0) {
|
|
|
|
env->itlb_tag[i] = env->immuregs[6];
|
2008-02-24 15:10:06 +01:00
|
|
|
env->itlb_tte[i] = val;
|
2007-09-20 16:54:22 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// error state?
|
|
|
|
return;
|
|
|
|
}
|
2005-07-02 16:31:34 +02:00
|
|
|
case 0x55: // I-MMU data access
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
2008-02-24 15:10:06 +01:00
|
|
|
unsigned int i = (addr >> 3) & 0x3f;
|
2005-07-02 16:31:34 +02:00
|
|
|
|
2007-09-20 16:54:22 +02:00
|
|
|
env->itlb_tag[i] = env->immuregs[6];
|
2008-02-24 15:10:06 +01:00
|
|
|
env->itlb_tte[i] = val;
|
2007-09-20 16:54:22 +02:00
|
|
|
return;
|
|
|
|
}
|
2005-07-02 16:31:34 +02:00
|
|
|
case 0x57: // I-MMU demap
|
2007-09-20 16:54:22 +02:00
|
|
|
// XXX
|
|
|
|
return;
|
2005-07-02 16:31:34 +02:00
|
|
|
case 0x58: // D-MMU regs
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
2008-02-24 15:10:06 +01:00
|
|
|
int reg = (addr >> 3) & 0xf;
|
2007-09-20 16:54:22 +02:00
|
|
|
uint64_t oldreg;
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2007-09-20 16:54:22 +02:00
|
|
|
oldreg = env->dmmuregs[reg];
|
2005-07-02 16:31:34 +02:00
|
|
|
switch(reg) {
|
|
|
|
case 0: // RO
|
|
|
|
case 4:
|
|
|
|
return;
|
|
|
|
case 3: // SFSR
|
2008-02-24 15:10:06 +01:00
|
|
|
if ((val & 1) == 0) {
|
|
|
|
val = 0; // Clear SFSR, Fault address
|
2007-09-20 16:54:22 +02:00
|
|
|
env->dmmuregs[4] = 0;
|
|
|
|
}
|
2008-02-24 15:10:06 +01:00
|
|
|
env->dmmuregs[reg] = val;
|
2005-07-02 16:31:34 +02:00
|
|
|
break;
|
|
|
|
case 1: // Primary context
|
|
|
|
case 2: // Secondary context
|
|
|
|
case 5: // TSB access
|
|
|
|
case 6: // Tag access
|
|
|
|
case 7: // Virtual Watchpoint
|
|
|
|
case 8: // Physical Watchpoint
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2008-02-24 15:10:06 +01:00
|
|
|
env->dmmuregs[reg] = val;
|
2005-07-02 16:31:34 +02:00
|
|
|
if (oldreg != env->dmmuregs[reg]) {
|
2007-10-14 18:29:21 +02:00
|
|
|
DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
|
2005-07-02 16:31:34 +02:00
|
|
|
}
|
2007-10-14 18:29:21 +02:00
|
|
|
#ifdef DEBUG_MMU
|
2007-09-20 16:54:22 +02:00
|
|
|
dump_mmu(env);
|
2005-07-02 16:31:34 +02:00
|
|
|
#endif
|
2007-09-20 16:54:22 +02:00
|
|
|
return;
|
|
|
|
}
|
2005-07-02 16:31:34 +02:00
|
|
|
case 0x5c: // D-MMU data in
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
// Try finding an invalid entry
|
|
|
|
for (i = 0; i < 64; i++) {
|
|
|
|
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
|
|
|
|
env->dtlb_tag[i] = env->dmmuregs[6];
|
2008-02-24 15:10:06 +01:00
|
|
|
env->dtlb_tte[i] = val;
|
2007-09-20 16:54:22 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// Try finding an unlocked entry
|
|
|
|
for (i = 0; i < 64; i++) {
|
|
|
|
if ((env->dtlb_tte[i] & 0x40) == 0) {
|
|
|
|
env->dtlb_tag[i] = env->dmmuregs[6];
|
2008-02-24 15:10:06 +01:00
|
|
|
env->dtlb_tte[i] = val;
|
2007-09-20 16:54:22 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// error state?
|
|
|
|
return;
|
|
|
|
}
|
2005-07-02 16:31:34 +02:00
|
|
|
case 0x5d: // D-MMU data access
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
2008-02-24 15:10:06 +01:00
|
|
|
unsigned int i = (addr >> 3) & 0x3f;
|
2005-07-02 16:31:34 +02:00
|
|
|
|
2007-09-20 16:54:22 +02:00
|
|
|
env->dtlb_tag[i] = env->dmmuregs[6];
|
2008-02-24 15:10:06 +01:00
|
|
|
env->dtlb_tte[i] = val;
|
2007-09-20 16:54:22 +02:00
|
|
|
return;
|
|
|
|
}
|
2005-07-02 16:31:34 +02:00
|
|
|
case 0x5f: // D-MMU demap
|
2005-07-23 16:27:54 +02:00
|
|
|
case 0x49: // Interrupt data receive
|
2007-09-20 16:54:22 +02:00
|
|
|
// XXX
|
|
|
|
return;
|
2005-07-02 16:31:34 +02:00
|
|
|
case 0x51: // I-MMU 8k TSB pointer, RO
|
|
|
|
case 0x52: // I-MMU 64k TSB pointer, RO
|
|
|
|
case 0x56: // I-MMU tag read, RO
|
|
|
|
case 0x59: // D-MMU 8k TSB pointer, RO
|
|
|
|
case 0x5a: // D-MMU 64k TSB pointer, RO
|
|
|
|
case 0x5b: // D-MMU data pointer, RO
|
|
|
|
case 0x5e: // D-MMU tag read, RO
|
2005-07-23 16:27:54 +02:00
|
|
|
case 0x48: // Interrupt dispatch, RO
|
|
|
|
case 0x7f: // Incoming interrupt vector, RO
|
|
|
|
case 0x82: // Primary no-fault, RO
|
|
|
|
case 0x83: // Secondary no-fault, RO
|
|
|
|
case 0x8a: // Primary no-fault LE, RO
|
|
|
|
case 0x8b: // Secondary no-fault LE, RO
|
2005-07-02 16:31:34 +02:00
|
|
|
default:
|
2008-02-24 15:10:06 +01:00
|
|
|
do_unassigned_access(addr, 1, 0, 1);
|
2007-09-20 16:54:22 +02:00
|
|
|
return;
|
2005-07-02 16:31:34 +02:00
|
|
|
}
|
|
|
|
}
|
2007-09-21 21:10:53 +02:00
|
|
|
#endif /* CONFIG_USER_ONLY */
|
2007-09-30 21:38:12 +02:00
|
|
|
|
2008-02-24 15:10:06 +01:00
|
|
|
void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
|
2007-09-30 21:38:12 +02:00
|
|
|
{
|
|
|
|
unsigned int i;
|
2008-02-24 15:10:06 +01:00
|
|
|
target_ulong val;
|
2007-09-30 21:38:12 +02:00
|
|
|
|
|
|
|
switch (asi) {
|
|
|
|
case 0xf0: // Block load primary
|
|
|
|
case 0xf1: // Block load secondary
|
|
|
|
case 0xf8: // Block load primary LE
|
|
|
|
case 0xf9: // Block load secondary LE
|
2007-10-01 19:07:58 +02:00
|
|
|
if (rd & 7) {
|
|
|
|
raise_exception(TT_ILL_INSN);
|
|
|
|
return;
|
|
|
|
}
|
2008-02-24 15:10:06 +01:00
|
|
|
if (addr & 0x3f) {
|
2007-10-01 19:07:58 +02:00
|
|
|
raise_exception(TT_UNALIGNED);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
for (i = 0; i < 16; i++) {
|
2008-02-24 15:10:06 +01:00
|
|
|
*(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4, 0);
|
|
|
|
addr += 4;
|
2007-09-30 21:38:12 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2008-02-24 15:10:06 +01:00
|
|
|
val = helper_ld_asi(addr, asi, size, 0);
|
2007-09-30 21:38:12 +02:00
|
|
|
switch(size) {
|
|
|
|
default:
|
|
|
|
case 4:
|
2008-02-24 15:10:06 +01:00
|
|
|
*((uint32_t *)&FT0) = val;
|
2007-09-30 21:38:12 +02:00
|
|
|
break;
|
|
|
|
case 8:
|
2008-02-24 15:10:06 +01:00
|
|
|
*((int64_t *)&DT0) = val;
|
2007-09-30 21:38:12 +02:00
|
|
|
break;
|
2007-11-25 19:40:20 +01:00
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
|
|
case 16:
|
|
|
|
// XXX
|
|
|
|
break;
|
|
|
|
#endif
|
2007-09-30 21:38:12 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-02-24 15:10:06 +01:00
|
|
|
void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
|
2007-09-30 21:38:12 +02:00
|
|
|
{
|
|
|
|
unsigned int i;
|
2008-02-24 15:10:06 +01:00
|
|
|
target_ulong val = 0;
|
2007-09-30 21:38:12 +02:00
|
|
|
|
|
|
|
switch (asi) {
|
|
|
|
case 0xf0: // Block store primary
|
|
|
|
case 0xf1: // Block store secondary
|
|
|
|
case 0xf8: // Block store primary LE
|
|
|
|
case 0xf9: // Block store secondary LE
|
2007-10-01 19:07:58 +02:00
|
|
|
if (rd & 7) {
|
|
|
|
raise_exception(TT_ILL_INSN);
|
|
|
|
return;
|
|
|
|
}
|
2008-02-24 15:10:06 +01:00
|
|
|
if (addr & 0x3f) {
|
2007-10-01 19:07:58 +02:00
|
|
|
raise_exception(TT_UNALIGNED);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
for (i = 0; i < 16; i++) {
|
2008-02-24 15:10:06 +01:00
|
|
|
val = *(uint32_t *)&env->fpr[rd++];
|
|
|
|
helper_st_asi(addr, val, asi & 0x8f, 4);
|
|
|
|
addr += 4;
|
2007-09-30 21:38:12 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch(size) {
|
|
|
|
default:
|
|
|
|
case 4:
|
2008-02-24 15:10:06 +01:00
|
|
|
val = *((uint32_t *)&FT0);
|
2007-09-30 21:38:12 +02:00
|
|
|
break;
|
|
|
|
case 8:
|
2008-02-24 15:10:06 +01:00
|
|
|
val = *((int64_t *)&DT0);
|
2007-09-30 21:38:12 +02:00
|
|
|
break;
|
2007-11-25 19:40:20 +01:00
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
|
|
case 16:
|
|
|
|
// XXX
|
|
|
|
break;
|
|
|
|
#endif
|
2007-09-30 21:38:12 +02:00
|
|
|
}
|
2008-02-24 15:10:06 +01:00
|
|
|
helper_st_asi(addr, val, asi, size);
|
|
|
|
}
|
|
|
|
|
|
|
|
target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
|
|
|
|
target_ulong val2, uint32_t asi)
|
|
|
|
{
|
|
|
|
target_ulong ret;
|
|
|
|
|
|
|
|
val1 &= 0xffffffffUL;
|
|
|
|
ret = helper_ld_asi(addr, asi, 4, 0);
|
|
|
|
ret &= 0xffffffffUL;
|
|
|
|
if (val1 == ret)
|
|
|
|
helper_st_asi(addr, val2 & 0xffffffffUL, asi, 4);
|
|
|
|
return ret;
|
2007-09-30 21:38:12 +02:00
|
|
|
}
|
|
|
|
|
2008-02-24 15:10:06 +01:00
|
|
|
target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
|
|
|
|
target_ulong val2, uint32_t asi)
|
|
|
|
{
|
|
|
|
target_ulong ret;
|
|
|
|
|
|
|
|
ret = helper_ld_asi(addr, asi, 8, 0);
|
|
|
|
if (val1 == ret)
|
|
|
|
helper_st_asi(addr, val2, asi, 8);
|
|
|
|
return ret;
|
|
|
|
}
|
2007-09-21 21:10:53 +02:00
|
|
|
#endif /* TARGET_SPARC64 */
|
2005-07-02 16:31:34 +02:00
|
|
|
|
|
|
|
#ifndef TARGET_SPARC64
|
2008-02-24 15:10:06 +01:00
|
|
|
void helper_rett(void)
|
2004-09-30 23:55:55 +02:00
|
|
|
{
|
2005-01-30 23:39:04 +01:00
|
|
|
unsigned int cwp;
|
|
|
|
|
2007-04-01 17:15:36 +02:00
|
|
|
if (env->psret == 1)
|
|
|
|
raise_exception(TT_ILL_INSN);
|
|
|
|
|
2004-09-30 23:55:55 +02:00
|
|
|
env->psret = 1;
|
2007-09-16 23:08:06 +02:00
|
|
|
cwp = (env->cwp + 1) & (NWINDOWS - 1);
|
2004-09-30 23:55:55 +02:00
|
|
|
if (env->wim & (1 << cwp)) {
|
|
|
|
raise_exception(TT_WIN_UNF);
|
|
|
|
}
|
|
|
|
set_cwp(cwp);
|
|
|
|
env->psrs = env->psrps;
|
|
|
|
}
|
2005-07-02 16:31:34 +02:00
|
|
|
#endif
|
2004-09-30 23:55:55 +02:00
|
|
|
|
2008-02-24 15:10:06 +01:00
|
|
|
uint64_t helper_pack64(target_ulong high, target_ulong low)
|
|
|
|
{
|
|
|
|
return ((uint64_t)high << 32) | (uint64_t)(low & 0xffffffff);
|
|
|
|
}
|
|
|
|
|
2004-10-04 23:23:09 +02:00
|
|
|
void helper_ldfsr(void)
|
2004-09-30 23:55:55 +02:00
|
|
|
{
|
2005-03-13 18:01:47 +01:00
|
|
|
int rnd_mode;
|
2008-03-15 19:11:06 +01:00
|
|
|
|
|
|
|
PUT_FSR32(env, *((uint32_t *) &FT0));
|
2004-09-30 23:55:55 +02:00
|
|
|
switch (env->fsr & FSR_RD_MASK) {
|
|
|
|
case FSR_RD_NEAREST:
|
2005-03-13 18:01:47 +01:00
|
|
|
rnd_mode = float_round_nearest_even;
|
2007-09-20 16:54:22 +02:00
|
|
|
break;
|
2005-04-06 22:44:48 +02:00
|
|
|
default:
|
2004-09-30 23:55:55 +02:00
|
|
|
case FSR_RD_ZERO:
|
2005-03-13 18:01:47 +01:00
|
|
|
rnd_mode = float_round_to_zero;
|
2007-09-20 16:54:22 +02:00
|
|
|
break;
|
2004-09-30 23:55:55 +02:00
|
|
|
case FSR_RD_POS:
|
2005-03-13 18:01:47 +01:00
|
|
|
rnd_mode = float_round_up;
|
2007-09-20 16:54:22 +02:00
|
|
|
break;
|
2004-09-30 23:55:55 +02:00
|
|
|
case FSR_RD_NEG:
|
2005-03-13 18:01:47 +01:00
|
|
|
rnd_mode = float_round_down;
|
2007-09-20 16:54:22 +02:00
|
|
|
break;
|
2004-09-30 23:55:55 +02:00
|
|
|
}
|
2005-03-13 18:01:47 +01:00
|
|
|
set_float_rounding_mode(rnd_mode, &env->fp_status);
|
2004-09-30 23:55:55 +02:00
|
|
|
}
|
2004-12-20 00:18:01 +01:00
|
|
|
|
2008-03-15 19:11:06 +01:00
|
|
|
void helper_stfsr(void)
|
|
|
|
{
|
|
|
|
*((uint32_t *) &FT0) = GET_FSR32(env);
|
|
|
|
}
|
|
|
|
|
|
|
|
void helper_debug(void)
|
2004-12-20 00:18:01 +01:00
|
|
|
{
|
|
|
|
env->exception_index = EXCP_DEBUG;
|
|
|
|
cpu_loop_exit();
|
|
|
|
}
|
2005-01-30 23:39:04 +01:00
|
|
|
|
2005-07-02 16:31:34 +02:00
|
|
|
#ifndef TARGET_SPARC64
|
2008-02-24 15:10:06 +01:00
|
|
|
void helper_wrpsr(target_ulong new_psr)
|
2005-01-30 23:39:04 +01:00
|
|
|
{
|
2008-02-24 15:10:06 +01:00
|
|
|
if ((new_psr & PSR_CWP) >= NWINDOWS)
|
2007-04-01 17:15:36 +02:00
|
|
|
raise_exception(TT_ILL_INSN);
|
|
|
|
else
|
2008-02-24 15:10:06 +01:00
|
|
|
PUT_PSR(env, new_psr);
|
2005-01-30 23:39:04 +01:00
|
|
|
}
|
|
|
|
|
2008-02-24 15:10:06 +01:00
|
|
|
target_ulong helper_rdpsr(void)
|
2005-01-30 23:39:04 +01:00
|
|
|
{
|
2008-02-24 15:10:06 +01:00
|
|
|
return GET_PSR(env);
|
2005-01-30 23:39:04 +01:00
|
|
|
}
|
2005-07-02 16:31:34 +02:00
|
|
|
|
|
|
|
#else
|
2008-03-18 19:08:25 +01:00
|
|
|
target_ulong helper_rdccr(void)
|
|
|
|
{
|
|
|
|
return GET_CCR(env);
|
|
|
|
}
|
|
|
|
|
|
|
|
void helper_wrccr(target_ulong new_ccr)
|
|
|
|
{
|
|
|
|
PUT_CCR(env, new_ccr);
|
|
|
|
}
|
|
|
|
|
|
|
|
// CWP handling is reversed in V9, but we still use the V8 register
|
|
|
|
// order.
|
|
|
|
target_ulong helper_rdcwp(void)
|
|
|
|
{
|
|
|
|
return GET_CWP64(env);
|
|
|
|
}
|
|
|
|
|
|
|
|
void helper_wrcwp(target_ulong new_cwp)
|
|
|
|
{
|
|
|
|
PUT_CWP64(env, new_cwp);
|
|
|
|
}
|
2005-07-02 16:31:34 +02:00
|
|
|
|
2008-03-18 19:06:54 +01:00
|
|
|
// This function uses non-native bit order
|
|
|
|
#define GET_FIELD(X, FROM, TO) \
|
|
|
|
((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
|
|
|
|
|
|
|
|
// This function uses the order in the manuals, i.e. bit 0 is 2^0
|
|
|
|
#define GET_FIELD_SP(X, FROM, TO) \
|
|
|
|
GET_FIELD(X, 63 - (TO), 63 - (FROM))
|
|
|
|
|
|
|
|
target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
|
|
|
|
{
|
|
|
|
return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) |
|
|
|
|
(GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) |
|
|
|
|
(GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) |
|
|
|
|
(GET_FIELD_SP(pixel_addr, 56, 59) << 13) |
|
|
|
|
(GET_FIELD_SP(pixel_addr, 35, 38) << 9) |
|
|
|
|
(GET_FIELD_SP(pixel_addr, 13, 16) << 5) |
|
|
|
|
(((pixel_addr >> 55) & 1) << 4) |
|
|
|
|
(GET_FIELD_SP(pixel_addr, 33, 34) << 2) |
|
|
|
|
GET_FIELD_SP(pixel_addr, 11, 12);
|
|
|
|
}
|
|
|
|
|
|
|
|
target_ulong helper_alignaddr(target_ulong addr, target_ulong offset)
|
|
|
|
{
|
|
|
|
uint64_t tmp;
|
|
|
|
|
|
|
|
tmp = addr + offset;
|
|
|
|
env->gsr &= ~7ULL;
|
|
|
|
env->gsr |= tmp & 7ULL;
|
|
|
|
return tmp & ~7ULL;
|
|
|
|
}
|
|
|
|
|
2008-02-24 15:10:06 +01:00
|
|
|
target_ulong helper_popc(target_ulong val)
|
2005-07-02 16:31:34 +02:00
|
|
|
{
|
2008-02-24 15:10:06 +01:00
|
|
|
return ctpop64(val);
|
2005-07-02 16:31:34 +02:00
|
|
|
}
|
2005-07-23 16:27:54 +02:00
|
|
|
|
|
|
|
static inline uint64_t *get_gregset(uint64_t pstate)
|
|
|
|
{
|
|
|
|
switch (pstate) {
|
|
|
|
default:
|
|
|
|
case 0:
|
2007-09-20 16:54:22 +02:00
|
|
|
return env->bgregs;
|
2005-07-23 16:27:54 +02:00
|
|
|
case PS_AG:
|
2007-09-20 16:54:22 +02:00
|
|
|
return env->agregs;
|
2005-07-23 16:27:54 +02:00
|
|
|
case PS_MG:
|
2007-09-20 16:54:22 +02:00
|
|
|
return env->mgregs;
|
2005-07-23 16:27:54 +02:00
|
|
|
case PS_IG:
|
2007-09-20 16:54:22 +02:00
|
|
|
return env->igregs;
|
2005-07-23 16:27:54 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-07-08 21:51:24 +02:00
|
|
|
static inline void change_pstate(uint64_t new_pstate)
|
2005-07-23 16:27:54 +02:00
|
|
|
{
|
2007-07-08 21:51:24 +02:00
|
|
|
uint64_t pstate_regs, new_pstate_regs;
|
2005-07-23 16:27:54 +02:00
|
|
|
uint64_t *src, *dst;
|
|
|
|
|
|
|
|
pstate_regs = env->pstate & 0xc01;
|
|
|
|
new_pstate_regs = new_pstate & 0xc01;
|
|
|
|
if (new_pstate_regs != pstate_regs) {
|
2007-09-20 16:54:22 +02:00
|
|
|
// Switch global register bank
|
|
|
|
src = get_gregset(new_pstate_regs);
|
|
|
|
dst = get_gregset(pstate_regs);
|
|
|
|
memcpy32(dst, env->gregs);
|
|
|
|
memcpy32(env->gregs, src);
|
2005-07-23 16:27:54 +02:00
|
|
|
}
|
|
|
|
env->pstate = new_pstate;
|
|
|
|
}
|
|
|
|
|
2008-02-24 15:10:06 +01:00
|
|
|
void helper_wrpstate(target_ulong new_state)
|
2007-07-08 21:51:24 +02:00
|
|
|
{
|
2008-02-24 15:10:06 +01:00
|
|
|
change_pstate(new_state & 0xf3f);
|
2007-07-08 21:51:24 +02:00
|
|
|
}
|
|
|
|
|
2008-02-24 15:10:06 +01:00
|
|
|
void helper_done(void)
|
2005-07-23 16:27:54 +02:00
|
|
|
{
|
|
|
|
env->tl--;
|
2008-03-05 18:59:48 +01:00
|
|
|
env->tsptr = &env->ts[env->tl];
|
|
|
|
env->pc = env->tsptr->tpc;
|
|
|
|
env->npc = env->tsptr->tnpc + 4;
|
|
|
|
PUT_CCR(env, env->tsptr->tstate >> 32);
|
|
|
|
env->asi = (env->tsptr->tstate >> 24) & 0xff;
|
|
|
|
change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
|
|
|
|
PUT_CWP64(env, env->tsptr->tstate & 0xff);
|
2005-07-23 16:27:54 +02:00
|
|
|
}
|
|
|
|
|
2008-02-24 15:10:06 +01:00
|
|
|
void helper_retry(void)
|
2005-07-23 16:27:54 +02:00
|
|
|
{
|
|
|
|
env->tl--;
|
2008-03-05 18:59:48 +01:00
|
|
|
env->tsptr = &env->ts[env->tl];
|
|
|
|
env->pc = env->tsptr->tpc;
|
|
|
|
env->npc = env->tsptr->tnpc;
|
|
|
|
PUT_CCR(env, env->tsptr->tstate >> 32);
|
|
|
|
env->asi = (env->tsptr->tstate >> 24) & 0xff;
|
|
|
|
change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
|
|
|
|
PUT_CWP64(env, env->tsptr->tstate & 0xff);
|
2005-07-23 16:27:54 +02:00
|
|
|
}
|
2005-07-02 16:31:34 +02:00
|
|
|
#endif
|
2005-07-05 00:18:23 +02:00
|
|
|
|
|
|
|
void set_cwp(int new_cwp)
|
|
|
|
{
|
|
|
|
/* put the modified wrap registers at their proper location */
|
|
|
|
if (env->cwp == (NWINDOWS - 1))
|
|
|
|
memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
|
|
|
|
env->cwp = new_cwp;
|
|
|
|
/* put the wrap registers at their temporary location */
|
|
|
|
if (new_cwp == (NWINDOWS - 1))
|
|
|
|
memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
|
|
|
|
env->regwptr = env->regbase + (new_cwp * 16);
|
|
|
|
REGWPTR = env->regwptr;
|
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_set_cwp(CPUState *env1, int new_cwp)
|
|
|
|
{
|
|
|
|
CPUState *saved_env;
|
|
|
|
#ifdef reg_REGWPTR
|
|
|
|
target_ulong *saved_regwptr;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
saved_env = env;
|
|
|
|
#ifdef reg_REGWPTR
|
|
|
|
saved_regwptr = REGWPTR;
|
|
|
|
#endif
|
|
|
|
env = env1;
|
|
|
|
set_cwp(new_cwp);
|
|
|
|
env = saved_env;
|
|
|
|
#ifdef reg_REGWPTR
|
|
|
|
REGWPTR = saved_regwptr;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef TARGET_SPARC64
|
2007-12-30 18:13:01 +01:00
|
|
|
#ifdef DEBUG_PCALL
|
|
|
|
static const char * const excp_names[0x50] = {
|
|
|
|
[TT_TFAULT] = "Instruction Access Fault",
|
|
|
|
[TT_TMISS] = "Instruction Access MMU Miss",
|
|
|
|
[TT_CODE_ACCESS] = "Instruction Access Error",
|
|
|
|
[TT_ILL_INSN] = "Illegal Instruction",
|
|
|
|
[TT_PRIV_INSN] = "Privileged Instruction",
|
|
|
|
[TT_NFPU_INSN] = "FPU Disabled",
|
|
|
|
[TT_FP_EXCP] = "FPU Exception",
|
|
|
|
[TT_TOVF] = "Tag Overflow",
|
|
|
|
[TT_CLRWIN] = "Clean Windows",
|
|
|
|
[TT_DIV_ZERO] = "Division By Zero",
|
|
|
|
[TT_DFAULT] = "Data Access Fault",
|
|
|
|
[TT_DMISS] = "Data Access MMU Miss",
|
|
|
|
[TT_DATA_ACCESS] = "Data Access Error",
|
|
|
|
[TT_DPROT] = "Data Protection Error",
|
|
|
|
[TT_UNALIGNED] = "Unaligned Memory Access",
|
|
|
|
[TT_PRIV_ACT] = "Privileged Action",
|
|
|
|
[TT_EXTINT | 0x1] = "External Interrupt 1",
|
|
|
|
[TT_EXTINT | 0x2] = "External Interrupt 2",
|
|
|
|
[TT_EXTINT | 0x3] = "External Interrupt 3",
|
|
|
|
[TT_EXTINT | 0x4] = "External Interrupt 4",
|
|
|
|
[TT_EXTINT | 0x5] = "External Interrupt 5",
|
|
|
|
[TT_EXTINT | 0x6] = "External Interrupt 6",
|
|
|
|
[TT_EXTINT | 0x7] = "External Interrupt 7",
|
|
|
|
[TT_EXTINT | 0x8] = "External Interrupt 8",
|
|
|
|
[TT_EXTINT | 0x9] = "External Interrupt 9",
|
|
|
|
[TT_EXTINT | 0xa] = "External Interrupt 10",
|
|
|
|
[TT_EXTINT | 0xb] = "External Interrupt 11",
|
|
|
|
[TT_EXTINT | 0xc] = "External Interrupt 12",
|
|
|
|
[TT_EXTINT | 0xd] = "External Interrupt 13",
|
|
|
|
[TT_EXTINT | 0xe] = "External Interrupt 14",
|
|
|
|
[TT_EXTINT | 0xf] = "External Interrupt 15",
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
2005-07-05 00:18:23 +02:00
|
|
|
void do_interrupt(int intno)
|
|
|
|
{
|
|
|
|
#ifdef DEBUG_PCALL
|
|
|
|
if (loglevel & CPU_LOG_INT) {
|
2007-09-20 16:54:22 +02:00
|
|
|
static int count;
|
2007-12-30 18:13:01 +01:00
|
|
|
const char *name;
|
|
|
|
|
|
|
|
if (intno < 0 || intno >= 0x180 || (intno > 0x4f && intno < 0x80))
|
|
|
|
name = "Unknown";
|
|
|
|
else if (intno >= 0x100)
|
|
|
|
name = "Trap Instruction";
|
|
|
|
else if (intno >= 0xc0)
|
|
|
|
name = "Window Fill";
|
|
|
|
else if (intno >= 0x80)
|
|
|
|
name = "Window Spill";
|
|
|
|
else {
|
|
|
|
name = excp_names[intno];
|
|
|
|
if (!name)
|
|
|
|
name = "Unknown";
|
|
|
|
}
|
|
|
|
|
|
|
|
fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
|
|
|
|
" SP=%016" PRIx64 "\n",
|
|
|
|
count, name, intno,
|
2005-07-05 00:18:23 +02:00
|
|
|
env->pc,
|
|
|
|
env->npc, env->regwptr[6]);
|
2007-09-20 16:54:22 +02:00
|
|
|
cpu_dump_state(env, logfile, fprintf, 0);
|
2005-07-05 00:18:23 +02:00
|
|
|
#if 0
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
uint8_t *ptr;
|
|
|
|
|
|
|
|
fprintf(logfile, " code=");
|
|
|
|
ptr = (uint8_t *)env->pc;
|
|
|
|
for(i = 0; i < 16; i++) {
|
|
|
|
fprintf(logfile, " %02x", ldub(ptr + i));
|
|
|
|
}
|
|
|
|
fprintf(logfile, "\n");
|
|
|
|
}
|
2005-07-05 00:18:23 +02:00
|
|
|
#endif
|
2007-09-20 16:54:22 +02:00
|
|
|
count++;
|
2005-07-05 00:18:23 +02:00
|
|
|
}
|
|
|
|
#endif
|
2007-09-16 23:08:06 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2005-07-23 16:27:54 +02:00
|
|
|
if (env->tl == MAXTL) {
|
2005-11-22 00:33:12 +01:00
|
|
|
cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
|
2007-09-20 16:54:22 +02:00
|
|
|
return;
|
2005-07-05 00:18:23 +02:00
|
|
|
}
|
|
|
|
#endif
|
2008-03-05 18:59:48 +01:00
|
|
|
env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
|
|
|
|
((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
|
|
|
|
GET_CWP64(env);
|
|
|
|
env->tsptr->tpc = env->pc;
|
|
|
|
env->tsptr->tnpc = env->npc;
|
|
|
|
env->tsptr->tt = intno;
|
2007-07-08 21:51:24 +02:00
|
|
|
change_pstate(PS_PEF | PS_PRIV | PS_AG);
|
|
|
|
|
|
|
|
if (intno == TT_CLRWIN)
|
|
|
|
set_cwp((env->cwp - 1) & (NWINDOWS - 1));
|
|
|
|
else if ((intno & 0x1c0) == TT_SPILL)
|
|
|
|
set_cwp((env->cwp - env->cansave - 2) & (NWINDOWS - 1));
|
|
|
|
else if ((intno & 0x1c0) == TT_FILL)
|
|
|
|
set_cwp((env->cwp + 1) & (NWINDOWS - 1));
|
2005-07-23 16:27:54 +02:00
|
|
|
env->tbr &= ~0x7fffULL;
|
|
|
|
env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
|
|
|
|
if (env->tl < MAXTL - 1) {
|
2007-09-20 16:54:22 +02:00
|
|
|
env->tl++;
|
2005-07-23 16:27:54 +02:00
|
|
|
} else {
|
2007-09-20 16:54:22 +02:00
|
|
|
env->pstate |= PS_RED;
|
|
|
|
if (env->tl != MAXTL)
|
|
|
|
env->tl++;
|
2005-07-23 16:27:54 +02:00
|
|
|
}
|
2008-03-05 18:59:48 +01:00
|
|
|
env->tsptr = &env->ts[env->tl];
|
2005-07-05 00:18:23 +02:00
|
|
|
env->pc = env->tbr;
|
|
|
|
env->npc = env->pc + 4;
|
|
|
|
env->exception_index = 0;
|
|
|
|
}
|
|
|
|
#else
|
2007-12-30 18:13:01 +01:00
|
|
|
#ifdef DEBUG_PCALL
|
|
|
|
static const char * const excp_names[0x80] = {
|
|
|
|
[TT_TFAULT] = "Instruction Access Fault",
|
|
|
|
[TT_ILL_INSN] = "Illegal Instruction",
|
|
|
|
[TT_PRIV_INSN] = "Privileged Instruction",
|
|
|
|
[TT_NFPU_INSN] = "FPU Disabled",
|
|
|
|
[TT_WIN_OVF] = "Window Overflow",
|
|
|
|
[TT_WIN_UNF] = "Window Underflow",
|
|
|
|
[TT_UNALIGNED] = "Unaligned Memory Access",
|
|
|
|
[TT_FP_EXCP] = "FPU Exception",
|
|
|
|
[TT_DFAULT] = "Data Access Fault",
|
|
|
|
[TT_TOVF] = "Tag Overflow",
|
|
|
|
[TT_EXTINT | 0x1] = "External Interrupt 1",
|
|
|
|
[TT_EXTINT | 0x2] = "External Interrupt 2",
|
|
|
|
[TT_EXTINT | 0x3] = "External Interrupt 3",
|
|
|
|
[TT_EXTINT | 0x4] = "External Interrupt 4",
|
|
|
|
[TT_EXTINT | 0x5] = "External Interrupt 5",
|
|
|
|
[TT_EXTINT | 0x6] = "External Interrupt 6",
|
|
|
|
[TT_EXTINT | 0x7] = "External Interrupt 7",
|
|
|
|
[TT_EXTINT | 0x8] = "External Interrupt 8",
|
|
|
|
[TT_EXTINT | 0x9] = "External Interrupt 9",
|
|
|
|
[TT_EXTINT | 0xa] = "External Interrupt 10",
|
|
|
|
[TT_EXTINT | 0xb] = "External Interrupt 11",
|
|
|
|
[TT_EXTINT | 0xc] = "External Interrupt 12",
|
|
|
|
[TT_EXTINT | 0xd] = "External Interrupt 13",
|
|
|
|
[TT_EXTINT | 0xe] = "External Interrupt 14",
|
|
|
|
[TT_EXTINT | 0xf] = "External Interrupt 15",
|
|
|
|
[TT_TOVF] = "Tag Overflow",
|
|
|
|
[TT_CODE_ACCESS] = "Instruction Access Error",
|
|
|
|
[TT_DATA_ACCESS] = "Data Access Error",
|
|
|
|
[TT_DIV_ZERO] = "Division By Zero",
|
|
|
|
[TT_NCP_INSN] = "Coprocessor Disabled",
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
2005-07-05 00:18:23 +02:00
|
|
|
void do_interrupt(int intno)
|
|
|
|
{
|
|
|
|
int cwp;
|
|
|
|
|
|
|
|
#ifdef DEBUG_PCALL
|
|
|
|
if (loglevel & CPU_LOG_INT) {
|
2007-09-20 16:54:22 +02:00
|
|
|
static int count;
|
2007-12-30 18:13:01 +01:00
|
|
|
const char *name;
|
|
|
|
|
|
|
|
if (intno < 0 || intno >= 0x100)
|
|
|
|
name = "Unknown";
|
|
|
|
else if (intno >= 0x80)
|
|
|
|
name = "Trap Instruction";
|
|
|
|
else {
|
|
|
|
name = excp_names[intno];
|
|
|
|
if (!name)
|
|
|
|
name = "Unknown";
|
|
|
|
}
|
|
|
|
|
|
|
|
fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
|
|
|
|
count, name, intno,
|
2005-07-05 00:18:23 +02:00
|
|
|
env->pc,
|
|
|
|
env->npc, env->regwptr[6]);
|
2007-09-20 16:54:22 +02:00
|
|
|
cpu_dump_state(env, logfile, fprintf, 0);
|
2005-07-05 00:18:23 +02:00
|
|
|
#if 0
|
2007-09-20 16:54:22 +02:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
uint8_t *ptr;
|
|
|
|
|
|
|
|
fprintf(logfile, " code=");
|
|
|
|
ptr = (uint8_t *)env->pc;
|
|
|
|
for(i = 0; i < 16; i++) {
|
|
|
|
fprintf(logfile, " %02x", ldub(ptr + i));
|
|
|
|
}
|
|
|
|
fprintf(logfile, "\n");
|
|
|
|
}
|
2005-07-05 00:18:23 +02:00
|
|
|
#endif
|
2007-09-20 16:54:22 +02:00
|
|
|
count++;
|
2005-07-05 00:18:23 +02:00
|
|
|
}
|
|
|
|
#endif
|
2007-09-16 23:08:06 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2005-07-05 00:18:23 +02:00
|
|
|
if (env->psret == 0) {
|
2005-11-22 00:33:12 +01:00
|
|
|
cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
|
2007-09-20 16:54:22 +02:00
|
|
|
return;
|
2005-07-05 00:18:23 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
env->psret = 0;
|
2007-09-16 23:08:06 +02:00
|
|
|
cwp = (env->cwp - 1) & (NWINDOWS - 1);
|
2005-07-05 00:18:23 +02:00
|
|
|
set_cwp(cwp);
|
|
|
|
env->regwptr[9] = env->pc;
|
|
|
|
env->regwptr[10] = env->npc;
|
|
|
|
env->psrps = env->psrs;
|
|
|
|
env->psrs = 1;
|
|
|
|
env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
|
|
|
|
env->pc = env->tbr;
|
|
|
|
env->npc = env->pc + 4;
|
|
|
|
env->exception_index = 0;
|
|
|
|
}
|
|
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#endif
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2007-09-16 23:08:06 +02:00
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#if !defined(CONFIG_USER_ONLY)
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2005-07-05 00:18:23 +02:00
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2007-04-13 17:46:16 +02:00
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static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
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void *retaddr);
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2005-07-05 00:18:23 +02:00
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#define MMUSUFFIX _mmu
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2007-04-13 17:46:16 +02:00
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#define ALIGNED_ONLY
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2007-10-29 15:39:49 +01:00
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#ifdef __s390__
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# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
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#else
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# define GETPC() (__builtin_return_address(0))
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#endif
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2005-07-05 00:18:23 +02:00
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#define SHIFT 0
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#include "softmmu_template.h"
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#define SHIFT 1
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#include "softmmu_template.h"
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#define SHIFT 2
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#include "softmmu_template.h"
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#define SHIFT 3
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#include "softmmu_template.h"
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2007-04-13 17:46:16 +02:00
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static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
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void *retaddr)
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{
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2007-05-07 20:05:05 +02:00
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#ifdef DEBUG_UNALIGNED
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printf("Unaligned access to 0x%x from 0x%x\n", addr, env->pc);
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#endif
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raise_exception(TT_UNALIGNED);
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2007-04-13 17:46:16 +02:00
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}
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2005-07-05 00:18:23 +02:00
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/* try to fill the TLB and return an exception if error. If retaddr is
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NULL, it means that the function was called in C code (i.e. not
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from generated code or from helper.c) */
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/* XXX: fix it to restore all registers */
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2007-10-14 09:07:08 +02:00
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void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
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2005-07-05 00:18:23 +02:00
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|
{
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|
TranslationBlock *tb;
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int ret;
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|
unsigned long pc;
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CPUState *saved_env;
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/* XXX: hack to restore env in all cases, even if not called from
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|
generated code */
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|
saved_env = env;
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env = cpu_single_env;
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|
2007-10-14 09:07:08 +02:00
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ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
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2005-07-05 00:18:23 +02:00
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|
if (ret) {
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|
if (retaddr) {
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|
/* now we have a real cpu fault */
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|
pc = (unsigned long)retaddr;
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|
tb = tb_find_pc(pc);
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|
if (tb) {
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|
/* the PC is inside the translated code. It means that we have
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|
|
a virtual CPU fault */
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|
cpu_restore_state(tb, env, pc, (void *)T2);
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|
}
|
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|
}
|
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|
|
cpu_loop_exit();
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|
|
}
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|
|
env = saved_env;
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|
}
|
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|
|
|
#endif
|
2007-05-17 21:30:10 +02:00
|
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|
|
|
|
#ifndef TARGET_SPARC64
|
2007-05-19 14:58:30 +02:00
|
|
|
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
|
2007-05-17 21:30:10 +02:00
|
|
|
int is_asi)
|
|
|
|
{
|
|
|
|
CPUState *saved_env;
|
|
|
|
|
|
|
|
/* XXX: hack to restore env in all cases, even if not called from
|
|
|
|
generated code */
|
|
|
|
saved_env = env;
|
|
|
|
env = cpu_single_env;
|
2007-12-28 19:50:23 +01:00
|
|
|
#ifdef DEBUG_UNASSIGNED
|
|
|
|
if (is_asi)
|
|
|
|
printf("Unassigned mem %s access to " TARGET_FMT_plx " asi 0x%02x from "
|
|
|
|
TARGET_FMT_lx "\n",
|
|
|
|
is_exec ? "exec" : is_write ? "write" : "read", addr, is_asi,
|
|
|
|
env->pc);
|
|
|
|
else
|
|
|
|
printf("Unassigned mem %s access to " TARGET_FMT_plx " from "
|
|
|
|
TARGET_FMT_lx "\n",
|
|
|
|
is_exec ? "exec" : is_write ? "write" : "read", addr, env->pc);
|
|
|
|
#endif
|
2007-05-17 21:30:10 +02:00
|
|
|
if (env->mmuregs[3]) /* Fault status register */
|
2007-09-20 16:54:22 +02:00
|
|
|
env->mmuregs[3] = 1; /* overflow (not read before another fault) */
|
2007-05-17 21:30:10 +02:00
|
|
|
if (is_asi)
|
|
|
|
env->mmuregs[3] |= 1 << 16;
|
|
|
|
if (env->psrs)
|
|
|
|
env->mmuregs[3] |= 1 << 5;
|
|
|
|
if (is_exec)
|
|
|
|
env->mmuregs[3] |= 1 << 6;
|
|
|
|
if (is_write)
|
|
|
|
env->mmuregs[3] |= 1 << 7;
|
|
|
|
env->mmuregs[3] |= (5 << 2) | 2;
|
|
|
|
env->mmuregs[4] = addr; /* Fault address register */
|
|
|
|
if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
|
2007-05-27 21:36:00 +02:00
|
|
|
if (is_exec)
|
|
|
|
raise_exception(TT_CODE_ACCESS);
|
|
|
|
else
|
|
|
|
raise_exception(TT_DATA_ACCESS);
|
2007-05-17 21:30:10 +02:00
|
|
|
}
|
|
|
|
env = saved_env;
|
|
|
|
}
|
|
|
|
#else
|
2007-05-19 14:58:30 +02:00
|
|
|
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
|
2007-05-17 21:30:10 +02:00
|
|
|
int is_asi)
|
|
|
|
{
|
|
|
|
#ifdef DEBUG_UNASSIGNED
|
|
|
|
CPUState *saved_env;
|
|
|
|
|
|
|
|
/* XXX: hack to restore env in all cases, even if not called from
|
|
|
|
generated code */
|
|
|
|
saved_env = env;
|
|
|
|
env = cpu_single_env;
|
2007-05-19 14:58:30 +02:00
|
|
|
printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n",
|
2007-05-17 21:30:10 +02:00
|
|
|
addr, env->pc);
|
|
|
|
env = saved_env;
|
|
|
|
#endif
|
2007-05-27 21:36:00 +02:00
|
|
|
if (is_exec)
|
|
|
|
raise_exception(TT_CODE_ACCESS);
|
|
|
|
else
|
|
|
|
raise_exception(TT_DATA_ACCESS);
|
2007-05-17 21:30:10 +02:00
|
|
|
}
|
|
|
|
#endif
|
2007-05-25 20:50:28 +02:00
|
|
|
|