2007-09-16 23:08:06 +02:00
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/*
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2007-06-04 02:31:01 +02:00
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* ColdFire Fast Ethernet Controller emulation.
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*
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* Copyright (c) 2007 CodeSourcery.
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*
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2011-06-26 04:21:35 +02:00
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* This code is licensed under the GPL
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2007-06-04 02:31:01 +02:00
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*/
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2013-02-04 15:40:22 +01:00
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#include "hw/hw.h"
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2012-10-24 08:43:34 +02:00
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#include "net/net.h"
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2013-02-05 17:06:20 +01:00
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#include "hw/m68k/mcf.h"
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2015-06-26 07:27:15 +02:00
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#include "hw/net/mii.h"
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2007-06-04 02:31:01 +02:00
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/* For crc32 */
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#include <zlib.h>
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2012-12-17 18:19:49 +01:00
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#include "exec/address-spaces.h"
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2007-06-04 02:31:01 +02:00
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//#define DEBUG_FEC 1
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#ifdef DEBUG_FEC
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2009-05-13 19:53:17 +02:00
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#define DPRINTF(fmt, ...) \
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do { printf("mcf_fec: " fmt , ## __VA_ARGS__); } while (0)
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2007-06-04 02:31:01 +02:00
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#else
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2009-05-13 19:53:17 +02:00
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#define DPRINTF(fmt, ...) do {} while(0)
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2007-06-04 02:31:01 +02:00
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#endif
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#define FEC_MAX_FRAME_SIZE 2032
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typedef struct {
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2011-11-24 14:31:14 +01:00
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MemoryRegion *sysmem;
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MemoryRegion iomem;
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2007-06-04 02:31:01 +02:00
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qemu_irq *irq;
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2009-11-25 19:49:20 +01:00
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NICState *nic;
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NICConf conf;
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2007-06-04 02:31:01 +02:00
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uint32_t irq_state;
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uint32_t eir;
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uint32_t eimr;
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int rx_enabled;
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uint32_t rx_descriptor;
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uint32_t tx_descriptor;
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uint32_t ecr;
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uint32_t mmfr;
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uint32_t mscr;
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uint32_t rcr;
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uint32_t tcr;
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uint32_t tfwr;
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uint32_t rfsr;
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uint32_t erdsr;
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uint32_t etdsr;
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uint32_t emrbr;
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} mcf_fec_state;
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#define FEC_INT_HB 0x80000000
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#define FEC_INT_BABR 0x40000000
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#define FEC_INT_BABT 0x20000000
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#define FEC_INT_GRA 0x10000000
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#define FEC_INT_TXF 0x08000000
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#define FEC_INT_TXB 0x04000000
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#define FEC_INT_RXF 0x02000000
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#define FEC_INT_RXB 0x01000000
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#define FEC_INT_MII 0x00800000
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#define FEC_INT_EB 0x00400000
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#define FEC_INT_LC 0x00200000
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#define FEC_INT_RL 0x00100000
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#define FEC_INT_UN 0x00080000
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#define FEC_EN 2
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#define FEC_RESET 1
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/* Map interrupt flags onto IRQ lines. */
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#define FEC_NUM_IRQ 13
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static const uint32_t mcf_fec_irq_map[FEC_NUM_IRQ] = {
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FEC_INT_TXF,
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FEC_INT_TXB,
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FEC_INT_UN,
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FEC_INT_RL,
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FEC_INT_RXF,
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FEC_INT_RXB,
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FEC_INT_MII,
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FEC_INT_LC,
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FEC_INT_HB,
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FEC_INT_GRA,
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FEC_INT_EB,
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FEC_INT_BABT,
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FEC_INT_BABR
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};
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/* Buffer Descriptor. */
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typedef struct {
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uint16_t flags;
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uint16_t length;
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uint32_t data;
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} mcf_fec_bd;
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#define FEC_BD_R 0x8000
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#define FEC_BD_E 0x8000
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#define FEC_BD_O1 0x4000
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#define FEC_BD_W 0x2000
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#define FEC_BD_O2 0x1000
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#define FEC_BD_L 0x0800
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#define FEC_BD_TC 0x0400
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#define FEC_BD_ABC 0x0200
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#define FEC_BD_M 0x0100
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#define FEC_BD_BC 0x0080
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#define FEC_BD_MC 0x0040
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#define FEC_BD_LG 0x0020
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#define FEC_BD_NO 0x0010
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#define FEC_BD_CR 0x0004
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#define FEC_BD_OV 0x0002
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#define FEC_BD_TR 0x0001
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static void mcf_fec_read_bd(mcf_fec_bd *bd, uint32_t addr)
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{
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2013-04-12 20:53:58 +02:00
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cpu_physical_memory_read(addr, bd, sizeof(*bd));
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2007-06-04 02:31:01 +02:00
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be16_to_cpus(&bd->flags);
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be16_to_cpus(&bd->length);
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be32_to_cpus(&bd->data);
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}
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static void mcf_fec_write_bd(mcf_fec_bd *bd, uint32_t addr)
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{
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mcf_fec_bd tmp;
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tmp.flags = cpu_to_be16(bd->flags);
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tmp.length = cpu_to_be16(bd->length);
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tmp.data = cpu_to_be32(bd->data);
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2013-04-12 20:53:58 +02:00
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cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
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2007-06-04 02:31:01 +02:00
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}
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static void mcf_fec_update(mcf_fec_state *s)
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{
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uint32_t active;
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uint32_t changed;
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uint32_t mask;
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int i;
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active = s->eir & s->eimr;
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changed = active ^s->irq_state;
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for (i = 0; i < FEC_NUM_IRQ; i++) {
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mask = mcf_fec_irq_map[i];
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if (changed & mask) {
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DPRINTF("IRQ %d = %d\n", i, (active & mask) != 0);
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qemu_set_irq(s->irq[i], (active & mask) != 0);
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}
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}
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s->irq_state = active;
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}
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static void mcf_fec_do_tx(mcf_fec_state *s)
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{
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uint32_t addr;
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mcf_fec_bd bd;
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int frame_size;
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int len;
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uint8_t frame[FEC_MAX_FRAME_SIZE];
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uint8_t *ptr;
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DPRINTF("do_tx\n");
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ptr = frame;
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frame_size = 0;
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addr = s->tx_descriptor;
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while (1) {
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mcf_fec_read_bd(&bd, addr);
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DPRINTF("tx_bd %x flags %04x len %d data %08x\n",
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addr, bd.flags, bd.length, bd.data);
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if ((bd.flags & FEC_BD_R) == 0) {
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/* Run out of descriptors to transmit. */
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break;
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}
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len = bd.length;
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if (frame_size + len > FEC_MAX_FRAME_SIZE) {
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len = FEC_MAX_FRAME_SIZE - frame_size;
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s->eir |= FEC_INT_BABT;
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}
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cpu_physical_memory_read(bd.data, ptr, len);
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ptr += len;
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frame_size += len;
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if (bd.flags & FEC_BD_L) {
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/* Last buffer in frame. */
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DPRINTF("Sending packet\n");
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2013-01-30 12:12:22 +01:00
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qemu_send_packet(qemu_get_queue(s->nic), frame, len);
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2007-06-04 02:31:01 +02:00
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ptr = frame;
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frame_size = 0;
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s->eir |= FEC_INT_TXF;
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}
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s->eir |= FEC_INT_TXB;
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bd.flags &= ~FEC_BD_R;
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/* Write back the modified descriptor. */
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mcf_fec_write_bd(&bd, addr);
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/* Advance to the next descriptor. */
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if ((bd.flags & FEC_BD_W) != 0) {
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addr = s->etdsr;
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} else {
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addr += 8;
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}
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}
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s->tx_descriptor = addr;
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}
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2007-06-08 01:24:56 +02:00
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static void mcf_fec_enable_rx(mcf_fec_state *s)
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2007-06-04 02:31:01 +02:00
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{
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mcf_fec_bd bd;
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mcf_fec_read_bd(&bd, s->rx_descriptor);
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s->rx_enabled = ((bd.flags & FEC_BD_E) != 0);
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if (!s->rx_enabled)
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DPRINTF("RX buffer full\n");
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}
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static void mcf_fec_reset(mcf_fec_state *s)
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{
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s->eir = 0;
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s->eimr = 0;
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s->rx_enabled = 0;
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s->ecr = 0;
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s->mscr = 0;
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s->rcr = 0x05ee0001;
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s->tcr = 0;
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s->tfwr = 0;
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s->rfsr = 0x500;
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}
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2015-06-26 07:27:15 +02:00
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#define MMFR_WRITE_OP (1 << 28)
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#define MMFR_READ_OP (2 << 28)
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#define MMFR_PHYADDR(v) (((v) >> 23) & 0x1f)
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#define MMFR_REGNUM(v) (((v) >> 18) & 0x1f)
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static uint64_t mcf_fec_read_mdio(mcf_fec_state *s)
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{
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uint64_t v;
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if (s->mmfr & MMFR_WRITE_OP)
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return s->mmfr;
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if (MMFR_PHYADDR(s->mmfr) != 1)
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return s->mmfr |= 0xffff;
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switch (MMFR_REGNUM(s->mmfr)) {
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case MII_BMCR:
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v = MII_BMCR_SPEED | MII_BMCR_AUTOEN | MII_BMCR_FD;
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break;
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case MII_BMSR:
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v = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD |
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MII_BMSR_10T_HD | MII_BMSR_MFPS | MII_BMSR_AN_COMP |
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MII_BMSR_AUTONEG | MII_BMSR_LINK_ST;
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break;
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case MII_PHYID1:
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v = DP83848_PHYID1;
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break;
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case MII_PHYID2:
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v = DP83848_PHYID2;
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break;
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case MII_ANAR:
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v = MII_ANAR_TXFD | MII_ANAR_TX | MII_ANAR_10FD |
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MII_ANAR_10 | MII_ANAR_CSMACD;
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break;
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case MII_ANLPAR:
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v = MII_ANLPAR_ACK | MII_ANLPAR_TXFD | MII_ANLPAR_TX |
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MII_ANLPAR_10FD | MII_ANLPAR_10 | MII_ANLPAR_CSMACD;
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break;
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default:
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v = 0xffff;
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break;
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}
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s->mmfr = (s->mmfr & ~0xffff) | v;
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return s->mmfr;
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}
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2012-10-23 12:30:10 +02:00
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static uint64_t mcf_fec_read(void *opaque, hwaddr addr,
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2011-11-24 14:31:14 +01:00
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unsigned size)
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2007-06-04 02:31:01 +02:00
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{
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mcf_fec_state *s = (mcf_fec_state *)opaque;
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switch (addr & 0x3ff) {
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case 0x004: return s->eir;
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case 0x008: return s->eimr;
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case 0x010: return s->rx_enabled ? (1 << 24) : 0; /* RDAR */
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case 0x014: return 0; /* TDAR */
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case 0x024: return s->ecr;
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2015-06-26 07:27:15 +02:00
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case 0x040: return mcf_fec_read_mdio(s);
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2007-06-04 02:31:01 +02:00
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case 0x044: return s->mscr;
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case 0x064: return 0; /* MIBC */
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case 0x084: return s->rcr;
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case 0x0c4: return s->tcr;
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case 0x0e4: /* PALR */
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2009-11-25 19:49:20 +01:00
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return (s->conf.macaddr.a[0] << 24) | (s->conf.macaddr.a[1] << 16)
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| (s->conf.macaddr.a[2] << 8) | s->conf.macaddr.a[3];
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2007-06-04 02:31:01 +02:00
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break;
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case 0x0e8: /* PAUR */
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2009-11-25 19:49:20 +01:00
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return (s->conf.macaddr.a[4] << 24) | (s->conf.macaddr.a[5] << 16) | 0x8808;
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2007-06-04 02:31:01 +02:00
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case 0x0ec: return 0x10000; /* OPD */
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case 0x118: return 0;
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case 0x11c: return 0;
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case 0x120: return 0;
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case 0x124: return 0;
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case 0x144: return s->tfwr;
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case 0x14c: return 0x600;
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case 0x150: return s->rfsr;
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case 0x180: return s->erdsr;
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case 0x184: return s->etdsr;
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case 0x188: return s->emrbr;
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default:
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2009-05-08 03:35:15 +02:00
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hw_error("mcf_fec_read: Bad address 0x%x\n", (int)addr);
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2007-06-04 02:31:01 +02:00
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return 0;
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}
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}
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2012-10-23 12:30:10 +02:00
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static void mcf_fec_write(void *opaque, hwaddr addr,
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2011-11-24 14:31:14 +01:00
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uint64_t value, unsigned size)
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2007-06-04 02:31:01 +02:00
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{
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mcf_fec_state *s = (mcf_fec_state *)opaque;
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switch (addr & 0x3ff) {
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case 0x004:
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s->eir &= ~value;
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break;
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case 0x008:
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s->eimr = value;
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break;
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case 0x010: /* RDAR */
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if ((s->ecr & FEC_EN) && !s->rx_enabled) {
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DPRINTF("RX enable\n");
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mcf_fec_enable_rx(s);
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}
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break;
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case 0x014: /* TDAR */
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if (s->ecr & FEC_EN) {
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mcf_fec_do_tx(s);
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}
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break;
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case 0x024:
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|
|
|
s->ecr = value;
|
|
|
|
if (value & FEC_RESET) {
|
|
|
|
DPRINTF("Reset\n");
|
|
|
|
mcf_fec_reset(s);
|
|
|
|
}
|
|
|
|
if ((s->ecr & FEC_EN) == 0) {
|
|
|
|
s->rx_enabled = 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 0x040:
|
|
|
|
s->mmfr = value;
|
2015-06-26 07:27:15 +02:00
|
|
|
s->eir |= FEC_INT_MII;
|
2007-06-04 02:31:01 +02:00
|
|
|
break;
|
|
|
|
case 0x044:
|
|
|
|
s->mscr = value & 0xfe;
|
|
|
|
break;
|
|
|
|
case 0x064:
|
|
|
|
/* TODO: Implement MIB. */
|
|
|
|
break;
|
|
|
|
case 0x084:
|
|
|
|
s->rcr = value & 0x07ff003f;
|
|
|
|
/* TODO: Implement LOOP mode. */
|
|
|
|
break;
|
|
|
|
case 0x0c4: /* TCR */
|
|
|
|
/* We transmit immediately, so raise GRA immediately. */
|
|
|
|
s->tcr = value;
|
|
|
|
if (value & 1)
|
|
|
|
s->eir |= FEC_INT_GRA;
|
|
|
|
break;
|
|
|
|
case 0x0e4: /* PALR */
|
2009-11-25 19:49:20 +01:00
|
|
|
s->conf.macaddr.a[0] = value >> 24;
|
|
|
|
s->conf.macaddr.a[1] = value >> 16;
|
|
|
|
s->conf.macaddr.a[2] = value >> 8;
|
|
|
|
s->conf.macaddr.a[3] = value;
|
2007-06-04 02:31:01 +02:00
|
|
|
break;
|
|
|
|
case 0x0e8: /* PAUR */
|
2009-11-25 19:49:20 +01:00
|
|
|
s->conf.macaddr.a[4] = value >> 24;
|
|
|
|
s->conf.macaddr.a[5] = value >> 16;
|
2007-06-04 02:31:01 +02:00
|
|
|
break;
|
|
|
|
case 0x0ec:
|
|
|
|
/* OPD */
|
|
|
|
break;
|
|
|
|
case 0x118:
|
|
|
|
case 0x11c:
|
|
|
|
case 0x120:
|
|
|
|
case 0x124:
|
|
|
|
/* TODO: implement MAC hash filtering. */
|
|
|
|
break;
|
|
|
|
case 0x144:
|
|
|
|
s->tfwr = value & 3;
|
|
|
|
break;
|
|
|
|
case 0x14c:
|
|
|
|
/* FRBR writes ignored. */
|
|
|
|
break;
|
|
|
|
case 0x150:
|
|
|
|
s->rfsr = (value & 0x3fc) | 0x400;
|
|
|
|
break;
|
|
|
|
case 0x180:
|
|
|
|
s->erdsr = value & ~3;
|
|
|
|
s->rx_descriptor = s->erdsr;
|
|
|
|
break;
|
|
|
|
case 0x184:
|
|
|
|
s->etdsr = value & ~3;
|
|
|
|
s->tx_descriptor = s->etdsr;
|
|
|
|
break;
|
|
|
|
case 0x188:
|
|
|
|
s->emrbr = value & 0x7f0;
|
|
|
|
break;
|
|
|
|
default:
|
2009-05-08 03:35:15 +02:00
|
|
|
hw_error("mcf_fec_write Bad address 0x%x\n", (int)addr);
|
2007-06-04 02:31:01 +02:00
|
|
|
}
|
|
|
|
mcf_fec_update(s);
|
|
|
|
}
|
|
|
|
|
2012-07-24 17:35:13 +02:00
|
|
|
static int mcf_fec_can_receive(NetClientState *nc)
|
2007-06-04 02:31:01 +02:00
|
|
|
{
|
2013-01-30 12:12:23 +01:00
|
|
|
mcf_fec_state *s = qemu_get_nic_opaque(nc);
|
2007-06-04 02:31:01 +02:00
|
|
|
return s->rx_enabled;
|
|
|
|
}
|
|
|
|
|
2012-07-24 17:35:13 +02:00
|
|
|
static ssize_t mcf_fec_receive(NetClientState *nc, const uint8_t *buf, size_t size)
|
2007-06-04 02:31:01 +02:00
|
|
|
{
|
2013-01-30 12:12:23 +01:00
|
|
|
mcf_fec_state *s = qemu_get_nic_opaque(nc);
|
2007-06-04 02:31:01 +02:00
|
|
|
mcf_fec_bd bd;
|
|
|
|
uint32_t flags = 0;
|
|
|
|
uint32_t addr;
|
|
|
|
uint32_t crc;
|
|
|
|
uint32_t buf_addr;
|
|
|
|
uint8_t *crc_ptr;
|
|
|
|
unsigned int buf_len;
|
|
|
|
|
|
|
|
DPRINTF("do_rx len %d\n", size);
|
|
|
|
if (!s->rx_enabled) {
|
|
|
|
fprintf(stderr, "mcf_fec_receive: Unexpected packet\n");
|
|
|
|
}
|
|
|
|
/* 4 bytes for the CRC. */
|
|
|
|
size += 4;
|
|
|
|
crc = cpu_to_be32(crc32(~0, buf, size));
|
|
|
|
crc_ptr = (uint8_t *)&crc;
|
|
|
|
/* Huge frames are truncted. */
|
|
|
|
if (size > FEC_MAX_FRAME_SIZE) {
|
|
|
|
size = FEC_MAX_FRAME_SIZE;
|
|
|
|
flags |= FEC_BD_TR | FEC_BD_LG;
|
|
|
|
}
|
|
|
|
/* Frames larger than the user limit just set error flags. */
|
|
|
|
if (size > (s->rcr >> 16)) {
|
|
|
|
flags |= FEC_BD_LG;
|
|
|
|
}
|
|
|
|
addr = s->rx_descriptor;
|
|
|
|
while (size > 0) {
|
|
|
|
mcf_fec_read_bd(&bd, addr);
|
|
|
|
if ((bd.flags & FEC_BD_E) == 0) {
|
|
|
|
/* No descriptors available. Bail out. */
|
|
|
|
/* FIXME: This is wrong. We should probably either save the
|
|
|
|
remainder for when more RX buffers are available, or
|
|
|
|
flag an error. */
|
|
|
|
fprintf(stderr, "mcf_fec: Lost end of frame\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
buf_len = (size <= s->emrbr) ? size: s->emrbr;
|
|
|
|
bd.length = buf_len;
|
|
|
|
size -= buf_len;
|
|
|
|
DPRINTF("rx_bd %x length %d\n", addr, bd.length);
|
|
|
|
/* The last 4 bytes are the CRC. */
|
|
|
|
if (size < 4)
|
|
|
|
buf_len += size - 4;
|
|
|
|
buf_addr = bd.data;
|
|
|
|
cpu_physical_memory_write(buf_addr, buf, buf_len);
|
|
|
|
buf += buf_len;
|
|
|
|
if (size < 4) {
|
|
|
|
cpu_physical_memory_write(buf_addr + buf_len, crc_ptr, 4 - size);
|
|
|
|
crc_ptr += 4 - size;
|
|
|
|
}
|
|
|
|
bd.flags &= ~FEC_BD_E;
|
|
|
|
if (size == 0) {
|
|
|
|
/* Last buffer in frame. */
|
|
|
|
bd.flags |= flags | FEC_BD_L;
|
|
|
|
DPRINTF("rx frame flags %04x\n", bd.flags);
|
|
|
|
s->eir |= FEC_INT_RXF;
|
|
|
|
} else {
|
|
|
|
s->eir |= FEC_INT_RXB;
|
|
|
|
}
|
|
|
|
mcf_fec_write_bd(&bd, addr);
|
|
|
|
/* Advance to the next descriptor. */
|
|
|
|
if ((bd.flags & FEC_BD_W) != 0) {
|
|
|
|
addr = s->erdsr;
|
|
|
|
} else {
|
|
|
|
addr += 8;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
s->rx_descriptor = addr;
|
|
|
|
mcf_fec_enable_rx(s);
|
|
|
|
mcf_fec_update(s);
|
2009-05-18 14:40:55 +02:00
|
|
|
return size;
|
2007-06-04 02:31:01 +02:00
|
|
|
}
|
|
|
|
|
2011-11-24 14:31:14 +01:00
|
|
|
static const MemoryRegionOps mcf_fec_ops = {
|
|
|
|
.read = mcf_fec_read,
|
|
|
|
.write = mcf_fec_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2007-06-04 02:31:01 +02:00
|
|
|
};
|
|
|
|
|
2009-11-25 19:49:20 +01:00
|
|
|
static NetClientInfo net_mcf_fec_info = {
|
2012-07-17 16:17:12 +02:00
|
|
|
.type = NET_CLIENT_OPTIONS_KIND_NIC,
|
2009-11-25 19:49:20 +01:00
|
|
|
.size = sizeof(NICState),
|
|
|
|
.can_receive = mcf_fec_can_receive,
|
|
|
|
.receive = mcf_fec_receive,
|
|
|
|
};
|
|
|
|
|
2011-11-24 14:31:14 +01:00
|
|
|
void mcf_fec_init(MemoryRegion *sysmem, NICInfo *nd,
|
2012-10-23 12:30:10 +02:00
|
|
|
hwaddr base, qemu_irq *irq)
|
2007-06-04 02:31:01 +02:00
|
|
|
{
|
|
|
|
mcf_fec_state *s;
|
|
|
|
|
2009-01-13 20:39:36 +01:00
|
|
|
qemu_check_nic_model(nd, "mcf_fec");
|
|
|
|
|
2011-08-21 05:09:37 +02:00
|
|
|
s = (mcf_fec_state *)g_malloc0(sizeof(mcf_fec_state));
|
2011-11-24 14:31:14 +01:00
|
|
|
s->sysmem = sysmem;
|
2007-06-04 02:31:01 +02:00
|
|
|
s->irq = irq;
|
2011-11-24 14:31:14 +01:00
|
|
|
|
2013-06-06 11:41:28 +02:00
|
|
|
memory_region_init_io(&s->iomem, NULL, &mcf_fec_ops, s, "fec", 0x400);
|
2011-11-24 14:31:14 +01:00
|
|
|
memory_region_add_subregion(sysmem, base, &s->iomem);
|
2007-06-04 02:31:01 +02:00
|
|
|
|
2011-07-20 12:20:22 +02:00
|
|
|
s->conf.macaddr = nd->macaddr;
|
2013-01-30 12:12:28 +01:00
|
|
|
s->conf.peers.ncs[0] = nd->netdev;
|
2009-11-25 19:49:20 +01:00
|
|
|
|
|
|
|
s->nic = qemu_new_nic(&net_mcf_fec_info, &s->conf, nd->model, nd->name, s);
|
|
|
|
|
2013-01-30 12:12:22 +01:00
|
|
|
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
|
2007-06-04 02:31:01 +02:00
|
|
|
}
|