2010-05-14 09:28:59 +02:00
|
|
|
/*
|
|
|
|
* PC SMBus implementation
|
|
|
|
* splitted from acpi.c
|
|
|
|
*
|
|
|
|
* Copyright (c) 2006 Fabrice Bellard
|
|
|
|
*
|
|
|
|
* This library is free software; you can redistribute it and/or
|
|
|
|
* modify it under the terms of the GNU Lesser General Public
|
|
|
|
* License version 2 as published by the Free Software Foundation.
|
|
|
|
*
|
|
|
|
* This library is distributed in the hope that it will be useful,
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
|
|
* Lesser General Public License for more details.
|
|
|
|
*
|
|
|
|
* You should have received a copy of the GNU Lesser General Public
|
2010-05-15 19:52:49 +02:00
|
|
|
* License along with this library; if not, see
|
|
|
|
* <http://www.gnu.org/licenses/>.
|
2010-05-14 09:28:59 +02:00
|
|
|
*/
|
2016-01-26 19:17:03 +01:00
|
|
|
#include "qemu/osdep.h"
|
2013-02-04 15:40:22 +01:00
|
|
|
#include "hw/hw.h"
|
2013-02-05 17:06:20 +01:00
|
|
|
#include "hw/i2c/pm_smbus.h"
|
|
|
|
#include "hw/i2c/smbus.h"
|
2010-05-14 09:28:59 +02:00
|
|
|
|
|
|
|
#define SMBHSTSTS 0x00
|
|
|
|
#define SMBHSTCNT 0x02
|
|
|
|
#define SMBHSTCMD 0x03
|
|
|
|
#define SMBHSTADD 0x04
|
|
|
|
#define SMBHSTDAT0 0x05
|
|
|
|
#define SMBHSTDAT1 0x06
|
|
|
|
#define SMBBLKDAT 0x07
|
2018-08-20 22:26:04 +02:00
|
|
|
#define SMBAUXCTL 0x0d
|
2010-05-14 09:28:59 +02:00
|
|
|
|
2018-08-20 22:26:01 +02:00
|
|
|
#define STS_HOST_BUSY (1 << 0)
|
|
|
|
#define STS_INTR (1 << 1)
|
|
|
|
#define STS_DEV_ERR (1 << 2)
|
|
|
|
#define STS_BUS_ERR (1 << 3)
|
|
|
|
#define STS_FAILED (1 << 4)
|
|
|
|
#define STS_SMBALERT (1 << 5)
|
|
|
|
#define STS_INUSE_STS (1 << 6)
|
|
|
|
#define STS_BYTE_DONE (1 << 7)
|
2013-07-07 23:03:02 +02:00
|
|
|
/* Signs of successfully transaction end :
|
|
|
|
* ByteDoneStatus = 1 (STS_BYTE_DONE) and INTR = 1 (STS_INTR )
|
|
|
|
*/
|
|
|
|
|
2018-08-20 22:26:01 +02:00
|
|
|
#define CTL_INTREN (1 << 0)
|
|
|
|
#define CTL_KILL (1 << 1)
|
|
|
|
#define CTL_LAST_BYTE (1 << 5)
|
|
|
|
#define CTL_START (1 << 6)
|
|
|
|
#define CTL_PEC_EN (1 << 7)
|
|
|
|
#define CTL_RETURN_MASK 0x1f
|
|
|
|
|
|
|
|
#define PROT_QUICK 0
|
|
|
|
#define PROT_BYTE 1
|
|
|
|
#define PROT_BYTE_DATA 2
|
|
|
|
#define PROT_WORD_DATA 3
|
|
|
|
#define PROT_PROC_CALL 4
|
|
|
|
#define PROT_BLOCK_DATA 5
|
2018-08-20 22:26:03 +02:00
|
|
|
#define PROT_I2C_BLOCK_READ 6
|
2018-08-20 22:26:01 +02:00
|
|
|
|
2018-08-20 22:26:04 +02:00
|
|
|
#define AUX_PEC (1 << 0)
|
|
|
|
#define AUX_BLK (1 << 1)
|
|
|
|
#define AUX_MASK 0x3
|
|
|
|
|
2018-08-20 22:26:01 +02:00
|
|
|
/*#define DEBUG*/
|
2010-05-14 09:29:21 +02:00
|
|
|
|
|
|
|
#ifdef DEBUG
|
|
|
|
# define SMBUS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
|
|
|
|
#else
|
|
|
|
# define SMBUS_DPRINTF(format, ...) do { } while (0)
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
2010-05-14 09:28:59 +02:00
|
|
|
static void smb_transaction(PMSMBus *s)
|
|
|
|
{
|
|
|
|
uint8_t prot = (s->smb_ctl >> 2) & 0x07;
|
|
|
|
uint8_t read = s->smb_addr & 0x01;
|
|
|
|
uint8_t cmd = s->smb_cmd;
|
|
|
|
uint8_t addr = s->smb_addr >> 1;
|
2013-08-03 00:18:51 +02:00
|
|
|
I2CBus *bus = s->smbus;
|
2014-03-31 18:26:31 +02:00
|
|
|
int ret;
|
2010-05-14 09:28:59 +02:00
|
|
|
|
2010-05-14 09:29:21 +02:00
|
|
|
SMBUS_DPRINTF("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
|
2013-07-07 23:03:02 +02:00
|
|
|
/* Transaction isn't exec if STS_DEV_ERR bit set */
|
|
|
|
if ((s->smb_stat & STS_DEV_ERR) != 0) {
|
2014-03-31 18:26:31 +02:00
|
|
|
goto error;
|
|
|
|
}
|
2018-08-20 22:26:01 +02:00
|
|
|
|
2010-05-14 09:28:59 +02:00
|
|
|
switch(prot) {
|
2018-08-20 22:26:01 +02:00
|
|
|
case PROT_QUICK:
|
2014-03-31 18:26:31 +02:00
|
|
|
ret = smbus_quick_command(bus, addr, read);
|
|
|
|
goto done;
|
2018-08-20 22:26:01 +02:00
|
|
|
case PROT_BYTE:
|
2010-05-14 09:28:59 +02:00
|
|
|
if (read) {
|
2014-03-31 18:26:31 +02:00
|
|
|
ret = smbus_receive_byte(bus, addr);
|
|
|
|
goto data8;
|
2010-05-14 09:28:59 +02:00
|
|
|
} else {
|
2014-03-31 18:26:31 +02:00
|
|
|
ret = smbus_send_byte(bus, addr, cmd);
|
|
|
|
goto done;
|
2010-05-14 09:28:59 +02:00
|
|
|
}
|
2018-08-20 22:26:01 +02:00
|
|
|
case PROT_BYTE_DATA:
|
2010-05-14 09:28:59 +02:00
|
|
|
if (read) {
|
2014-03-31 18:26:31 +02:00
|
|
|
ret = smbus_read_byte(bus, addr, cmd);
|
|
|
|
goto data8;
|
2010-05-14 09:28:59 +02:00
|
|
|
} else {
|
2014-03-31 18:26:31 +02:00
|
|
|
ret = smbus_write_byte(bus, addr, cmd, s->smb_data0);
|
|
|
|
goto done;
|
2010-05-14 09:28:59 +02:00
|
|
|
}
|
|
|
|
break;
|
2018-08-20 22:26:01 +02:00
|
|
|
case PROT_WORD_DATA:
|
2010-05-14 09:28:59 +02:00
|
|
|
if (read) {
|
2014-03-31 18:26:31 +02:00
|
|
|
ret = smbus_read_word(bus, addr, cmd);
|
|
|
|
goto data16;
|
2010-05-14 09:28:59 +02:00
|
|
|
} else {
|
2018-08-20 22:26:01 +02:00
|
|
|
ret = smbus_write_word(bus, addr, cmd,
|
|
|
|
(s->smb_data1 << 8) | s->smb_data0);
|
2014-03-31 18:26:31 +02:00
|
|
|
goto done;
|
2010-05-14 09:28:59 +02:00
|
|
|
}
|
|
|
|
break;
|
2018-08-20 22:26:03 +02:00
|
|
|
case PROT_I2C_BLOCK_READ:
|
2010-05-14 09:28:59 +02:00
|
|
|
if (read) {
|
2018-08-20 22:26:02 +02:00
|
|
|
int xfersize = s->smb_data0;
|
|
|
|
if (xfersize > sizeof(s->smb_data)) {
|
|
|
|
xfersize = sizeof(s->smb_data);
|
|
|
|
}
|
|
|
|
ret = smbus_read_block(bus, addr, s->smb_data1, s->smb_data,
|
|
|
|
xfersize, false, true);
|
2014-03-31 18:26:31 +02:00
|
|
|
goto data8;
|
2010-05-14 09:28:59 +02:00
|
|
|
} else {
|
2018-08-20 22:26:03 +02:00
|
|
|
/* The manual says the behavior is undefined, just set DEV_ERR. */
|
|
|
|
goto error;
|
2010-05-14 09:28:59 +02:00
|
|
|
}
|
|
|
|
break;
|
2018-08-20 22:26:04 +02:00
|
|
|
case PROT_BLOCK_DATA:
|
|
|
|
if (read) {
|
|
|
|
ret = smbus_read_block(bus, addr, cmd, s->smb_data,
|
|
|
|
sizeof(s->smb_data), !s->i2c_enable,
|
|
|
|
!s->i2c_enable);
|
|
|
|
if (ret < 0) {
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
s->smb_index = 0;
|
|
|
|
s->op_done = false;
|
|
|
|
if (s->smb_auxctl & AUX_BLK) {
|
|
|
|
s->smb_stat |= STS_INTR;
|
|
|
|
} else {
|
|
|
|
s->smb_blkdata = s->smb_data[0];
|
|
|
|
s->smb_stat |= STS_HOST_BUSY | STS_BYTE_DONE;
|
|
|
|
}
|
|
|
|
s->smb_data0 = ret;
|
|
|
|
goto out;
|
|
|
|
} else {
|
|
|
|
if (s->smb_auxctl & AUX_BLK) {
|
|
|
|
if (s->smb_index != s->smb_data0) {
|
|
|
|
s->smb_index = 0;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
/* Data is already all written to the queue, just do
|
|
|
|
the operation. */
|
|
|
|
s->smb_index = 0;
|
|
|
|
ret = smbus_write_block(bus, addr, cmd, s->smb_data,
|
|
|
|
s->smb_data0, !s->i2c_enable);
|
|
|
|
if (ret < 0) {
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
s->op_done = true;
|
|
|
|
s->smb_stat |= STS_INTR;
|
|
|
|
s->smb_stat &= ~STS_HOST_BUSY;
|
|
|
|
} else {
|
|
|
|
s->op_done = false;
|
|
|
|
s->smb_stat |= STS_HOST_BUSY | STS_BYTE_DONE;
|
|
|
|
s->smb_data[0] = s->smb_blkdata;
|
|
|
|
s->smb_index = 0;
|
|
|
|
ret = 0;
|
|
|
|
}
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
break;
|
2010-05-14 09:28:59 +02:00
|
|
|
default:
|
|
|
|
goto error;
|
|
|
|
}
|
2014-03-31 18:26:31 +02:00
|
|
|
abort();
|
|
|
|
|
|
|
|
data16:
|
|
|
|
if (ret < 0) {
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
s->smb_data1 = ret >> 8;
|
|
|
|
data8:
|
|
|
|
if (ret < 0) {
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
s->smb_data0 = ret;
|
|
|
|
done:
|
|
|
|
if (ret < 0) {
|
|
|
|
goto error;
|
|
|
|
}
|
2018-08-20 22:26:04 +02:00
|
|
|
s->smb_stat |= STS_INTR;
|
|
|
|
out:
|
2010-05-14 09:28:59 +02:00
|
|
|
return;
|
|
|
|
|
2014-03-31 18:26:31 +02:00
|
|
|
error:
|
2013-07-07 23:03:02 +02:00
|
|
|
s->smb_stat |= STS_DEV_ERR;
|
2014-03-31 18:26:31 +02:00
|
|
|
return;
|
2010-05-14 09:28:59 +02:00
|
|
|
}
|
|
|
|
|
2017-12-10 18:27:03 +01:00
|
|
|
static void smb_transaction_start(PMSMBus *s)
|
|
|
|
{
|
2018-08-20 22:26:07 +02:00
|
|
|
if (s->smb_ctl & CTL_INTREN) {
|
|
|
|
smb_transaction(s);
|
|
|
|
} else {
|
|
|
|
/* Do not execute immediately the command; it will be
|
|
|
|
* executed when guest will read SMB_STAT register. This
|
|
|
|
* is to work around a bug in AMIBIOS (that is working
|
|
|
|
* around another bug in some specific hardware) where
|
|
|
|
* it waits for STS_HOST_BUSY to be set before waiting
|
|
|
|
* checking for status. If STS_HOST_BUSY doesn't get
|
|
|
|
* set, it gets stuck. */
|
|
|
|
s->smb_stat |= STS_HOST_BUSY;
|
|
|
|
}
|
2017-12-10 18:27:03 +01:00
|
|
|
}
|
|
|
|
|
2018-08-20 22:26:06 +02:00
|
|
|
static bool
|
|
|
|
smb_irq_value(PMSMBus *s)
|
|
|
|
{
|
|
|
|
return ((s->smb_stat & ~STS_HOST_BUSY) != 0) && (s->smb_ctl & CTL_INTREN);
|
|
|
|
}
|
|
|
|
|
2012-11-23 14:57:01 +01:00
|
|
|
static void smb_ioport_writeb(void *opaque, hwaddr addr, uint64_t val,
|
|
|
|
unsigned width)
|
2010-05-14 09:28:59 +02:00
|
|
|
{
|
|
|
|
PMSMBus *s = opaque;
|
2012-11-23 14:57:01 +01:00
|
|
|
|
Fix debug print warning
Steps:
1.enable qemu debug print, using simply scprit as below:
grep "//#define DEBUG" * -rl | xargs sed -i "s/\/\/#define DEBUG/#define DEBUG/g"
2. make -j
3. get some warning:
hw/i2c/pm_smbus.c: In function 'smb_ioport_writeb':
hw/i2c/pm_smbus.c:142: warning: format '%04x' expects type 'unsigned int', but argument 2 has type 'hwaddr'
hw/i2c/pm_smbus.c:142: warning: format '%02x' expects type 'unsigned int', but argument 3 has type 'uint64_t'
hw/i2c/pm_smbus.c: In function 'smb_ioport_readb':
hw/i2c/pm_smbus.c:209: warning: format '%04x' expects type 'unsigned int', but argument 2 has type 'hwaddr'
hw/intc/i8259.c: In function 'pic_ioport_read':
hw/intc/i8259.c:373: warning: format '%02x' expects type 'unsigned int', but argument 2 has type 'hwaddr'
hw/input/pckbd.c: In function 'kbd_write_command':
hw/input/pckbd.c:232: warning: format '%02x' expects type 'unsigned int', but argument 2 has type 'uint64_t'
hw/input/pckbd.c: In function 'kbd_write_data':
hw/input/pckbd.c:333: warning: format '%02x' expects type 'unsigned int', but argument 2 has type 'uint64_t'
hw/isa/apm.c: In function 'apm_ioport_writeb':
hw/isa/apm.c:44: warning: format '%x' expects type 'unsigned int', but argument 2 has type 'hwaddr'
hw/isa/apm.c:44: warning: format '%02x' expects type 'unsigned int', but argument 3 has type 'uint64_t'
hw/isa/apm.c: In function 'apm_ioport_readb':
hw/isa/apm.c:67: warning: format '%x' expects type 'unsigned int', but argument 2 has type 'hwaddr'
hw/timer/mc146818rtc.c: In function 'cmos_ioport_write':
hw/timer/mc146818rtc.c:394: warning: format '%02x' expects type 'unsigned int', but argument 3 has type 'uint64_t'
hw/i386/pc.c: In function 'port92_write':
hw/i386/pc.c:479: warning: format '%02x' expects type 'unsigned int', but argument 2 has type 'uint64_t'
Fix them.
Cc: qemu-trivial@nongnu.org
Signed-off-by: Gonglei <arei.gonglei@huawei.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-08-25 04:01:27 +02:00
|
|
|
SMBUS_DPRINTF("SMB writeb port=0x%04" HWADDR_PRIx
|
|
|
|
" val=0x%02" PRIx64 "\n", addr, val);
|
2010-05-14 09:28:59 +02:00
|
|
|
switch(addr) {
|
|
|
|
case SMBHSTSTS:
|
2018-08-20 22:26:04 +02:00
|
|
|
s->smb_stat &= ~(val & ~STS_HOST_BUSY);
|
|
|
|
if (!s->op_done && !(s->smb_auxctl & AUX_BLK)) {
|
|
|
|
uint8_t read = s->smb_addr & 0x01;
|
|
|
|
|
|
|
|
s->smb_index++;
|
2018-12-06 13:18:30 +01:00
|
|
|
if (s->smb_index >= PM_SMBUS_MAX_MSG_SIZE) {
|
|
|
|
s->smb_index = 0;
|
|
|
|
}
|
2018-08-20 22:26:04 +02:00
|
|
|
if (!read && s->smb_index == s->smb_data0) {
|
|
|
|
uint8_t prot = (s->smb_ctl >> 2) & 0x07;
|
|
|
|
uint8_t cmd = s->smb_cmd;
|
|
|
|
uint8_t addr = s->smb_addr >> 1;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (prot == PROT_I2C_BLOCK_READ) {
|
|
|
|
s->smb_stat |= STS_DEV_ERR;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = smbus_write_block(s->smbus, addr, cmd, s->smb_data,
|
|
|
|
s->smb_data0, !s->i2c_enable);
|
|
|
|
if (ret < 0) {
|
|
|
|
s->smb_stat |= STS_DEV_ERR;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
s->op_done = true;
|
|
|
|
s->smb_stat |= STS_INTR;
|
|
|
|
s->smb_stat &= ~STS_HOST_BUSY;
|
|
|
|
} else if (!read) {
|
|
|
|
s->smb_data[s->smb_index] = s->smb_blkdata;
|
|
|
|
s->smb_stat |= STS_BYTE_DONE;
|
|
|
|
} else if (s->smb_ctl & CTL_LAST_BYTE) {
|
|
|
|
s->op_done = true;
|
|
|
|
s->smb_blkdata = s->smb_data[s->smb_index];
|
|
|
|
s->smb_index = 0;
|
|
|
|
s->smb_stat |= STS_INTR;
|
|
|
|
s->smb_stat &= ~STS_HOST_BUSY;
|
|
|
|
} else {
|
|
|
|
s->smb_blkdata = s->smb_data[s->smb_index];
|
|
|
|
s->smb_stat |= STS_BYTE_DONE;
|
|
|
|
}
|
|
|
|
}
|
2010-05-14 09:28:59 +02:00
|
|
|
break;
|
|
|
|
case SMBHSTCNT:
|
2018-08-20 22:26:04 +02:00
|
|
|
s->smb_ctl = val & ~CTL_START; /* CTL_START always reads 0 */
|
|
|
|
if (val & CTL_START) {
|
|
|
|
if (!s->op_done) {
|
|
|
|
s->smb_index = 0;
|
|
|
|
s->op_done = true;
|
|
|
|
}
|
2017-12-10 18:27:03 +01:00
|
|
|
smb_transaction_start(s);
|
2018-08-20 22:26:01 +02:00
|
|
|
}
|
2018-08-20 22:26:04 +02:00
|
|
|
if (s->smb_ctl & CTL_KILL) {
|
|
|
|
s->op_done = true;
|
|
|
|
s->smb_index = 0;
|
|
|
|
s->smb_stat |= STS_FAILED;
|
|
|
|
s->smb_stat &= ~STS_HOST_BUSY;
|
|
|
|
}
|
2010-05-14 09:28:59 +02:00
|
|
|
break;
|
|
|
|
case SMBHSTCMD:
|
|
|
|
s->smb_cmd = val;
|
|
|
|
break;
|
|
|
|
case SMBHSTADD:
|
|
|
|
s->smb_addr = val;
|
|
|
|
break;
|
|
|
|
case SMBHSTDAT0:
|
|
|
|
s->smb_data0 = val;
|
|
|
|
break;
|
|
|
|
case SMBHSTDAT1:
|
|
|
|
s->smb_data1 = val;
|
|
|
|
break;
|
|
|
|
case SMBBLKDAT:
|
2018-08-20 22:26:04 +02:00
|
|
|
if (s->smb_index >= PM_SMBUS_MAX_MSG_SIZE) {
|
2010-05-14 09:28:59 +02:00
|
|
|
s->smb_index = 0;
|
2018-08-20 22:26:04 +02:00
|
|
|
}
|
|
|
|
if (s->smb_auxctl & AUX_BLK) {
|
|
|
|
s->smb_data[s->smb_index++] = val;
|
|
|
|
} else {
|
|
|
|
s->smb_blkdata = val;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case SMBAUXCTL:
|
|
|
|
s->smb_auxctl = val & AUX_MASK;
|
2010-05-14 09:28:59 +02:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2018-08-20 22:26:04 +02:00
|
|
|
|
|
|
|
out:
|
2018-08-20 22:26:06 +02:00
|
|
|
if (s->set_irq) {
|
|
|
|
s->set_irq(s, smb_irq_value(s));
|
|
|
|
}
|
2010-05-14 09:28:59 +02:00
|
|
|
}
|
|
|
|
|
2012-11-23 14:57:01 +01:00
|
|
|
static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width)
|
2010-05-14 09:28:59 +02:00
|
|
|
{
|
|
|
|
PMSMBus *s = opaque;
|
|
|
|
uint32_t val;
|
|
|
|
|
|
|
|
switch(addr) {
|
|
|
|
case SMBHSTSTS:
|
|
|
|
val = s->smb_stat;
|
2017-12-10 18:27:03 +01:00
|
|
|
if (s->smb_stat & STS_HOST_BUSY) {
|
|
|
|
/* execute command now */
|
2018-08-20 22:26:07 +02:00
|
|
|
s->smb_stat &= ~STS_HOST_BUSY;
|
2017-12-10 18:27:03 +01:00
|
|
|
smb_transaction(s);
|
|
|
|
}
|
2010-05-14 09:28:59 +02:00
|
|
|
break;
|
|
|
|
case SMBHSTCNT:
|
2018-08-20 22:26:01 +02:00
|
|
|
val = s->smb_ctl & CTL_RETURN_MASK;
|
2010-05-14 09:28:59 +02:00
|
|
|
break;
|
|
|
|
case SMBHSTCMD:
|
|
|
|
val = s->smb_cmd;
|
|
|
|
break;
|
|
|
|
case SMBHSTADD:
|
|
|
|
val = s->smb_addr;
|
|
|
|
break;
|
|
|
|
case SMBHSTDAT0:
|
|
|
|
val = s->smb_data0;
|
|
|
|
break;
|
|
|
|
case SMBHSTDAT1:
|
|
|
|
val = s->smb_data1;
|
|
|
|
break;
|
|
|
|
case SMBBLKDAT:
|
2018-08-20 22:26:04 +02:00
|
|
|
if (s->smb_index >= PM_SMBUS_MAX_MSG_SIZE) {
|
2010-05-14 09:28:59 +02:00
|
|
|
s->smb_index = 0;
|
2018-08-20 22:26:04 +02:00
|
|
|
}
|
|
|
|
if (s->smb_auxctl & AUX_BLK) {
|
|
|
|
val = s->smb_data[s->smb_index++];
|
|
|
|
if (!s->op_done && s->smb_index == s->smb_data0) {
|
|
|
|
s->op_done = true;
|
|
|
|
s->smb_index = 0;
|
|
|
|
s->smb_stat &= ~STS_HOST_BUSY;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
val = s->smb_blkdata;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case SMBAUXCTL:
|
|
|
|
val = s->smb_auxctl;
|
2010-05-14 09:28:59 +02:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
val = 0;
|
|
|
|
break;
|
|
|
|
}
|
2018-08-20 22:26:01 +02:00
|
|
|
SMBUS_DPRINTF("SMB readb port=0x%04" HWADDR_PRIx " val=0x%02x\n",
|
|
|
|
addr, val);
|
|
|
|
|
2018-08-20 22:26:06 +02:00
|
|
|
if (s->set_irq) {
|
|
|
|
s->set_irq(s, smb_irq_value(s));
|
|
|
|
}
|
|
|
|
|
2010-05-14 09:28:59 +02:00
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2018-08-20 22:26:04 +02:00
|
|
|
static void pm_smbus_reset(PMSMBus *s)
|
|
|
|
{
|
|
|
|
s->op_done = true;
|
|
|
|
s->smb_index = 0;
|
|
|
|
s->smb_stat = 0;
|
|
|
|
}
|
|
|
|
|
2012-11-23 14:57:01 +01:00
|
|
|
static const MemoryRegionOps pm_smbus_ops = {
|
|
|
|
.read = smb_ioport_readb,
|
|
|
|
.write = smb_ioport_writeb,
|
|
|
|
.valid.min_access_size = 1,
|
|
|
|
.valid.max_access_size = 1,
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
|
|
};
|
|
|
|
|
2018-08-20 22:26:08 +02:00
|
|
|
void pm_smbus_init(DeviceState *parent, PMSMBus *smb, bool force_aux_blk)
|
2010-05-14 09:28:59 +02:00
|
|
|
{
|
2018-08-20 22:26:04 +02:00
|
|
|
smb->op_done = true;
|
|
|
|
smb->reset = pm_smbus_reset;
|
2010-05-14 09:28:59 +02:00
|
|
|
smb->smbus = i2c_init_bus(parent, "i2c");
|
2018-08-20 22:26:08 +02:00
|
|
|
if (force_aux_blk) {
|
|
|
|
smb->smb_auxctl |= AUX_BLK;
|
|
|
|
}
|
2013-06-07 03:25:08 +02:00
|
|
|
memory_region_init_io(&smb->io, OBJECT(parent), &pm_smbus_ops, smb,
|
|
|
|
"pm-smbus", 64);
|
2010-05-14 09:28:59 +02:00
|
|
|
}
|