523 lines
16 KiB
C
523 lines
16 KiB
C
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/*
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* QEMU IDE Emulation: PCI Bus support.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "pc.h"
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#include "block.h"
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#include "block_int.h"
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#include "sysemu.h"
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#include "dma.h"
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#include "pci.h"
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#include "ide-internal.h"
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/***********************************************************/
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/* PCI IDE definitions */
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/* CMD646 specific */
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#define MRDMODE 0x71
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#define MRDMODE_INTR_CH0 0x04
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#define MRDMODE_INTR_CH1 0x08
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#define MRDMODE_BLK_CH0 0x10
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#define MRDMODE_BLK_CH1 0x20
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#define UDIDETCR0 0x73
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#define UDIDETCR1 0x7B
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#define IDE_TYPE_PIIX3 0
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#define IDE_TYPE_CMD646 1
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#define IDE_TYPE_PIIX4 2
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typedef struct PCIIDEState {
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PCIDevice dev;
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IDEBus bus[2];
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BMDMAState bmdma[2];
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int type; /* see IDE_TYPE_xxx */
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} PCIIDEState;
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static void cmd646_update_irq(PCIIDEState *d);
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static void ide_map(PCIDevice *pci_dev, int region_num,
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uint32_t addr, uint32_t size, int type)
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{
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PCIIDEState *d = (PCIIDEState *)pci_dev;
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IDEBus *bus;
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if (region_num <= 3) {
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bus = &d->bus[(region_num >> 1)];
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if (region_num & 1) {
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register_ioport_read(addr + 2, 1, 1, ide_status_read, bus);
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register_ioport_write(addr + 2, 1, 1, ide_cmd_write, bus);
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} else {
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register_ioport_write(addr, 8, 1, ide_ioport_write, bus);
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register_ioport_read(addr, 8, 1, ide_ioport_read, bus);
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/* data ports */
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register_ioport_write(addr, 2, 2, ide_data_writew, bus);
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register_ioport_read(addr, 2, 2, ide_data_readw, bus);
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register_ioport_write(addr, 4, 4, ide_data_writel, bus);
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register_ioport_read(addr, 4, 4, ide_data_readl, bus);
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}
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}
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}
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static void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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BMDMAState *bm = opaque;
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, val);
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#endif
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if (!(val & BM_CMD_START)) {
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/* XXX: do it better */
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ide_dma_cancel(bm);
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bm->cmd = val & 0x09;
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} else {
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if (!(bm->status & BM_STATUS_DMAING)) {
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bm->status |= BM_STATUS_DMAING;
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/* start dma transfer if possible */
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if (bm->dma_cb)
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bm->dma_cb(bm, 0);
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}
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bm->cmd = val & 0x09;
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}
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}
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static uint32_t bmdma_readb(void *opaque, uint32_t addr)
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{
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BMDMAState *bm = opaque;
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PCIIDEState *pci_dev;
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uint32_t val;
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switch(addr & 3) {
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case 0:
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val = bm->cmd;
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break;
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case 1:
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pci_dev = bm->pci_dev;
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if (pci_dev->type == IDE_TYPE_CMD646) {
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val = pci_dev->dev.config[MRDMODE];
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} else {
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val = 0xff;
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}
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break;
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case 2:
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val = bm->status;
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break;
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case 3:
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pci_dev = bm->pci_dev;
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if (pci_dev->type == IDE_TYPE_CMD646) {
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if (bm == &pci_dev->bmdma[0])
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val = pci_dev->dev.config[UDIDETCR0];
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else
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val = pci_dev->dev.config[UDIDETCR1];
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} else {
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val = 0xff;
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}
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break;
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default:
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val = 0xff;
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break;
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}
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#ifdef DEBUG_IDE
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printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
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#endif
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return val;
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}
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static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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BMDMAState *bm = opaque;
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PCIIDEState *pci_dev;
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#ifdef DEBUG_IDE
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printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
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#endif
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switch(addr & 3) {
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case 1:
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pci_dev = bm->pci_dev;
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if (pci_dev->type == IDE_TYPE_CMD646) {
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pci_dev->dev.config[MRDMODE] =
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(pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
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cmd646_update_irq(pci_dev);
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}
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break;
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case 2:
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bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
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break;
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case 3:
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pci_dev = bm->pci_dev;
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if (pci_dev->type == IDE_TYPE_CMD646) {
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if (bm == &pci_dev->bmdma[0])
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pci_dev->dev.config[UDIDETCR0] = val;
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else
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pci_dev->dev.config[UDIDETCR1] = val;
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}
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break;
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}
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}
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static uint32_t bmdma_addr_readb(void *opaque, uint32_t addr)
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{
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BMDMAState *bm = opaque;
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uint32_t val;
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val = (bm->addr >> ((addr & 3) * 8)) & 0xff;
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, val);
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#endif
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return val;
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}
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static void bmdma_addr_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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BMDMAState *bm = opaque;
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int shift = (addr & 3) * 8;
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, val);
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#endif
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bm->addr &= ~(0xFF << shift);
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bm->addr |= ((val & 0xFF) << shift) & ~3;
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bm->cur_addr = bm->addr;
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}
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static uint32_t bmdma_addr_readw(void *opaque, uint32_t addr)
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{
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BMDMAState *bm = opaque;
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uint32_t val;
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val = (bm->addr >> ((addr & 3) * 8)) & 0xffff;
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, val);
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#endif
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return val;
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}
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static void bmdma_addr_writew(void *opaque, uint32_t addr, uint32_t val)
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{
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BMDMAState *bm = opaque;
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int shift = (addr & 3) * 8;
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, val);
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#endif
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bm->addr &= ~(0xFFFF << shift);
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bm->addr |= ((val & 0xFFFF) << shift) & ~3;
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bm->cur_addr = bm->addr;
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}
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static uint32_t bmdma_addr_readl(void *opaque, uint32_t addr)
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{
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BMDMAState *bm = opaque;
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uint32_t val;
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val = bm->addr;
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, val);
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#endif
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return val;
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}
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static void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val)
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{
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BMDMAState *bm = opaque;
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, val);
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#endif
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bm->addr = val & ~3;
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bm->cur_addr = bm->addr;
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}
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static void bmdma_map(PCIDevice *pci_dev, int region_num,
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uint32_t addr, uint32_t size, int type)
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{
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PCIIDEState *d = (PCIIDEState *)pci_dev;
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int i;
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for(i = 0;i < 2; i++) {
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BMDMAState *bm = &d->bmdma[i];
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d->bus[i].bmdma = bm;
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bm->pci_dev = DO_UPCAST(PCIIDEState, dev, pci_dev);
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bm->bus = d->bus+i;
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qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm);
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register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
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register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
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register_ioport_read(addr, 4, 1, bmdma_readb, bm);
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register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm);
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register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm);
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register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm);
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register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm);
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register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
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register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
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addr += 8;
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}
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}
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static void pci_ide_save(QEMUFile* f, void *opaque)
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{
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PCIIDEState *d = opaque;
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int i;
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pci_device_save(&d->dev, f);
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for(i = 0; i < 2; i++) {
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BMDMAState *bm = &d->bmdma[i];
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uint8_t ifidx;
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qemu_put_8s(f, &bm->cmd);
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qemu_put_8s(f, &bm->status);
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qemu_put_be32s(f, &bm->addr);
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qemu_put_sbe64s(f, &bm->sector_num);
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qemu_put_be32s(f, &bm->nsector);
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ifidx = bm->unit + 2*i;
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qemu_put_8s(f, &ifidx);
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/* XXX: if a transfer is pending, we do not save it yet */
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}
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/* per IDE interface data */
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for(i = 0; i < 2; i++) {
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idebus_save(f, &d->bus[i]);
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}
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/* per IDE drive data */
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for(i = 0; i < 2; i++) {
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ide_save(f, &d->bus[i].ifs[0]);
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ide_save(f, &d->bus[i].ifs[1]);
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}
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}
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static int pci_ide_load(QEMUFile* f, void *opaque, int version_id)
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{
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PCIIDEState *d = opaque;
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int ret, i;
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if (version_id != 2 && version_id != 3)
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return -EINVAL;
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ret = pci_device_load(&d->dev, f);
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if (ret < 0)
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return ret;
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for(i = 0; i < 2; i++) {
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BMDMAState *bm = &d->bmdma[i];
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uint8_t ifidx;
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qemu_get_8s(f, &bm->cmd);
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qemu_get_8s(f, &bm->status);
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qemu_get_be32s(f, &bm->addr);
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qemu_get_sbe64s(f, &bm->sector_num);
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qemu_get_be32s(f, &bm->nsector);
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qemu_get_8s(f, &ifidx);
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bm->unit = ifidx & 1;
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/* XXX: if a transfer is pending, we do not save it yet */
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}
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/* per IDE interface data */
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for(i = 0; i < 2; i++) {
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idebus_load(f, &d->bus[i], version_id);
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}
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/* per IDE drive data */
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for(i = 0; i < 2; i++) {
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ide_load(f, &d->bus[i].ifs[0], version_id);
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ide_load(f, &d->bus[i].ifs[1], version_id);
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}
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return 0;
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}
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/* XXX: call it also when the MRDMODE is changed from the PCI config
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registers */
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static void cmd646_update_irq(PCIIDEState *d)
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{
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int pci_level;
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pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) &&
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!(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) ||
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((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) &&
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!(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1));
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qemu_set_irq(d->dev.irq[0], pci_level);
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}
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/* the PCI irq level is the logical OR of the two channels */
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static void cmd646_set_irq(void *opaque, int channel, int level)
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{
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PCIIDEState *d = opaque;
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int irq_mask;
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irq_mask = MRDMODE_INTR_CH0 << channel;
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if (level)
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d->dev.config[MRDMODE] |= irq_mask;
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else
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d->dev.config[MRDMODE] &= ~irq_mask;
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cmd646_update_irq(d);
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}
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static void cmd646_reset(void *opaque)
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{
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PCIIDEState *d = opaque;
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unsigned int i;
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for (i = 0; i < 2; i++)
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ide_dma_cancel(&d->bmdma[i]);
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}
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/* CMD646 PCI IDE controller */
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void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
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int secondary_ide_enabled)
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{
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PCIIDEState *d;
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uint8_t *pci_conf;
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qemu_irq *irq;
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d = (PCIIDEState *)pci_register_device(bus, "CMD646 IDE",
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sizeof(PCIIDEState),
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-1,
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NULL, NULL);
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d->type = IDE_TYPE_CMD646;
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pci_conf = d->dev.config;
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pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CMD);
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_CMD_646);
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pci_conf[0x08] = 0x07; // IDE controller revision
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pci_conf[0x09] = 0x8f;
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pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
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pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
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pci_conf[0x51] = 0x04; // enable IDE0
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if (secondary_ide_enabled) {
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/* XXX: if not enabled, really disable the seconday IDE controller */
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pci_conf[0x51] |= 0x08; /* enable IDE1 */
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}
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pci_register_bar((PCIDevice *)d, 0, 0x8,
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PCI_ADDRESS_SPACE_IO, ide_map);
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pci_register_bar((PCIDevice *)d, 1, 0x4,
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PCI_ADDRESS_SPACE_IO, ide_map);
|
||
|
pci_register_bar((PCIDevice *)d, 2, 0x8,
|
||
|
PCI_ADDRESS_SPACE_IO, ide_map);
|
||
|
pci_register_bar((PCIDevice *)d, 3, 0x4,
|
||
|
PCI_ADDRESS_SPACE_IO, ide_map);
|
||
|
pci_register_bar((PCIDevice *)d, 4, 0x10,
|
||
|
PCI_ADDRESS_SPACE_IO, bmdma_map);
|
||
|
|
||
|
pci_conf[0x3d] = 0x01; // interrupt on pin 1
|
||
|
|
||
|
irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
|
||
|
ide_init2(&d->bus[0], hd_table[0], hd_table[1], irq[0]);
|
||
|
ide_init2(&d->bus[1], hd_table[2], hd_table[3], irq[1]);
|
||
|
|
||
|
register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
|
||
|
qemu_register_reset(cmd646_reset, d);
|
||
|
cmd646_reset(d);
|
||
|
}
|
||
|
|
||
|
static void piix3_reset(void *opaque)
|
||
|
{
|
||
|
PCIIDEState *d = opaque;
|
||
|
uint8_t *pci_conf = d->dev.config;
|
||
|
int i;
|
||
|
|
||
|
for (i = 0; i < 2; i++)
|
||
|
ide_dma_cancel(&d->bmdma[i]);
|
||
|
|
||
|
pci_conf[0x04] = 0x00;
|
||
|
pci_conf[0x05] = 0x00;
|
||
|
pci_conf[0x06] = 0x80; /* FBC */
|
||
|
pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
|
||
|
pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
|
||
|
}
|
||
|
|
||
|
/* hd_table must contain 4 block drivers */
|
||
|
/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
|
||
|
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
|
||
|
qemu_irq *pic)
|
||
|
{
|
||
|
PCIIDEState *d;
|
||
|
uint8_t *pci_conf;
|
||
|
int i;
|
||
|
|
||
|
/* register a function 1 of PIIX3 */
|
||
|
d = (PCIIDEState *)pci_register_device(bus, "PIIX3 IDE",
|
||
|
sizeof(PCIIDEState),
|
||
|
devfn,
|
||
|
NULL, NULL);
|
||
|
d->type = IDE_TYPE_PIIX3;
|
||
|
|
||
|
pci_conf = d->dev.config;
|
||
|
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
|
||
|
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_1);
|
||
|
pci_conf[0x09] = 0x80; // legacy ATA mode
|
||
|
pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
|
||
|
pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
|
||
|
|
||
|
qemu_register_reset(piix3_reset, d);
|
||
|
piix3_reset(d);
|
||
|
|
||
|
pci_register_bar((PCIDevice *)d, 4, 0x10,
|
||
|
PCI_ADDRESS_SPACE_IO, bmdma_map);
|
||
|
|
||
|
ide_init2(&d->bus[0], hd_table[0], hd_table[1], isa_reserve_irq(14));
|
||
|
ide_init2(&d->bus[1], hd_table[2], hd_table[3], isa_reserve_irq(15));
|
||
|
ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6);
|
||
|
ide_init_ioport(&d->bus[1], 0x170, 0x376);
|
||
|
|
||
|
for (i = 0; i < 4; i++)
|
||
|
if (hd_table[i])
|
||
|
hd_table[i]->private = &d->dev;
|
||
|
|
||
|
register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
|
||
|
}
|
||
|
|
||
|
/* hd_table must contain 4 block drivers */
|
||
|
/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
|
||
|
void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
|
||
|
qemu_irq *pic)
|
||
|
{
|
||
|
PCIIDEState *d;
|
||
|
uint8_t *pci_conf;
|
||
|
|
||
|
/* register a function 1 of PIIX4 */
|
||
|
d = (PCIIDEState *)pci_register_device(bus, "PIIX4 IDE",
|
||
|
sizeof(PCIIDEState),
|
||
|
devfn,
|
||
|
NULL, NULL);
|
||
|
d->type = IDE_TYPE_PIIX4;
|
||
|
|
||
|
pci_conf = d->dev.config;
|
||
|
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
|
||
|
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB);
|
||
|
pci_conf[0x09] = 0x80; // legacy ATA mode
|
||
|
pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
|
||
|
pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
|
||
|
|
||
|
qemu_register_reset(piix3_reset, d);
|
||
|
piix3_reset(d);
|
||
|
|
||
|
pci_register_bar((PCIDevice *)d, 4, 0x10,
|
||
|
PCI_ADDRESS_SPACE_IO, bmdma_map);
|
||
|
|
||
|
/*
|
||
|
* These should call isa_reserve_irq() instead when MIPS supports it
|
||
|
*/
|
||
|
ide_init2(&d->bus[0], hd_table[0], hd_table[1], pic[14]);
|
||
|
ide_init2(&d->bus[1], hd_table[2], hd_table[3], pic[15]);
|
||
|
ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6);
|
||
|
ide_init_ioport(&d->bus[1], 0x170, 0x376);
|
||
|
|
||
|
register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
|
||
|
}
|
||
|
|