2003-05-13 02:25:15 +02:00
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/*
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2003-05-14 21:00:11 +02:00
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* virtual page mapping and translated block handling
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2007-09-16 23:08:06 +02:00
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*
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2003-05-13 02:25:15 +02:00
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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2004-04-01 01:37:16 +02:00
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#include "config.h"
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2004-09-29 23:15:28 +02:00
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#ifdef _WIN32
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2007-12-17 05:42:29 +01:00
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#define WIN32_LEAN_AND_MEAN
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2004-09-29 23:15:28 +02:00
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#include <windows.h>
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#else
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2004-11-14 17:22:05 +01:00
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#include <sys/types.h>
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2004-09-29 23:15:28 +02:00
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#include <sys/mman.h>
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#endif
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2003-05-13 02:25:15 +02:00
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include <errno.h>
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#include <unistd.h>
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#include <inttypes.h>
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2003-09-30 23:04:53 +02:00
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#include "cpu.h"
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#include "exec-all.h"
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2008-04-11 23:35:42 +02:00
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#include "qemu-common.h"
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2008-05-23 11:57:34 +02:00
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#include "tcg.h"
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2008-06-30 18:31:04 +02:00
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#include "hw/hw.h"
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2008-10-06 16:02:03 +02:00
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#include "osdep.h"
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2008-11-05 17:04:33 +01:00
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#include "kvm.h"
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2006-03-25 20:31:22 +01:00
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#if defined(CONFIG_USER_ONLY)
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#include <qemu.h>
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#endif
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2003-05-13 02:25:15 +02:00
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2003-05-14 21:00:11 +02:00
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//#define DEBUG_TB_INVALIDATE
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2003-06-24 15:28:12 +02:00
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//#define DEBUG_FLUSH
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2004-01-04 19:06:42 +01:00
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//#define DEBUG_TLB
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2006-12-18 06:03:52 +01:00
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//#define DEBUG_UNASSIGNED
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2003-05-14 21:00:11 +02:00
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/* make various TB consistency checks */
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2007-09-16 23:08:06 +02:00
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//#define DEBUG_TB_CHECK
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//#define DEBUG_TLB_CHECK
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2003-05-14 21:00:11 +02:00
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2007-03-17 16:17:58 +01:00
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//#define DEBUG_IOPORT
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2007-05-26 19:36:03 +02:00
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//#define DEBUG_SUBPAGE
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2007-03-17 16:17:58 +01:00
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2006-04-16 17:14:59 +02:00
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#if !defined(CONFIG_USER_ONLY)
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/* TB consistency checks only implemented for usermode emulation. */
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#undef DEBUG_TB_CHECK
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#endif
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2004-01-04 19:06:42 +01:00
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#define SMC_BITMAP_USE_THRESHOLD 10
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#define MMAP_AREA_START 0x00000000
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#define MMAP_AREA_END 0xa8000000
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2003-05-14 21:00:11 +02:00
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2005-07-24 14:55:09 +02:00
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#if defined(TARGET_SPARC64)
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#define TARGET_PHYS_ADDR_SPACE_BITS 41
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2007-05-19 14:58:30 +02:00
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#elif defined(TARGET_SPARC)
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#define TARGET_PHYS_ADDR_SPACE_BITS 36
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2007-04-05 22:08:21 +02:00
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#elif defined(TARGET_ALPHA)
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#define TARGET_PHYS_ADDR_SPACE_BITS 42
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#define TARGET_VIRT_ADDR_SPACE_BITS 42
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2005-07-24 14:55:09 +02:00
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#elif defined(TARGET_PPC64)
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#define TARGET_PHYS_ADDR_SPACE_BITS 42
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2008-04-27 23:12:55 +02:00
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#elif defined(TARGET_X86_64) && !defined(USE_KQEMU)
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#define TARGET_PHYS_ADDR_SPACE_BITS 42
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#elif defined(TARGET_I386) && !defined(USE_KQEMU)
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#define TARGET_PHYS_ADDR_SPACE_BITS 36
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2005-07-24 14:55:09 +02:00
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#else
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/* Note: for compatibility with kqemu, we use 32 bits for x86_64 */
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#define TARGET_PHYS_ADDR_SPACE_BITS 32
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#endif
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2008-10-04 09:24:27 +02:00
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static TranslationBlock *tbs;
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2008-05-28 14:30:31 +02:00
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int code_gen_max_blocks;
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2004-01-04 19:06:42 +01:00
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TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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2008-10-04 09:24:27 +02:00
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static int nb_tbs;
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2003-05-14 23:51:13 +02:00
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/* any access to the tbs or the page table must use this lock */
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spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
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2003-05-14 21:00:11 +02:00
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2008-07-26 17:05:57 +02:00
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#if defined(__arm__) || defined(__sparc_v9__)
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/* The prologue must be reachable with a direct jump. ARM and Sparc64
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have limited branch ranges (possibly also PPC) so place it in a
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2008-07-10 19:21:31 +02:00
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section close to code segment. */
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#define code_gen_section \
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__attribute__((__section__(".gen_code"))) \
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__attribute__((aligned (32)))
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#else
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#define code_gen_section \
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__attribute__((aligned (32)))
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#endif
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uint8_t code_gen_prologue[1024] code_gen_section;
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2008-10-04 09:24:27 +02:00
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static uint8_t *code_gen_buffer;
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static unsigned long code_gen_buffer_size;
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2008-05-28 14:30:31 +02:00
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/* threshold to flush the translated code buffer */
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2008-10-04 09:24:27 +02:00
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static unsigned long code_gen_buffer_max_size;
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2003-05-14 21:00:11 +02:00
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uint8_t *code_gen_ptr;
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2008-06-08 03:09:01 +02:00
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#if !defined(CONFIG_USER_ONLY)
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2008-04-27 23:12:55 +02:00
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ram_addr_t phys_ram_size;
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2004-01-04 19:06:42 +01:00
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int phys_ram_fd;
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uint8_t *phys_ram_base;
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2004-02-06 20:46:14 +01:00
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uint8_t *phys_ram_dirty;
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2008-10-06 16:02:03 +02:00
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static int in_migration;
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2007-02-09 00:08:38 +01:00
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static ram_addr_t phys_ram_alloc_offset = 0;
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2008-06-08 03:09:01 +02:00
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#endif
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2004-01-04 19:06:42 +01:00
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2005-11-22 00:25:50 +01:00
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CPUState *first_cpu;
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/* current CPU in the current thread. It is only valid inside
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cpu_exec() */
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2007-09-16 23:08:06 +02:00
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CPUState *cpu_single_env;
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2008-06-29 03:03:05 +02:00
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/* 0 = Do not count executed instructions.
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2008-06-30 19:22:19 +02:00
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1 = Precise instruction counting.
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2008-06-29 03:03:05 +02:00
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2 = Adaptive rate instruction counting. */
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int use_icount = 0;
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/* Current instruction counter. While executing translated code this may
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include some instructions that have not yet been executed. */
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int64_t qemu_icount;
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2005-11-22 00:25:50 +01:00
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2003-05-13 02:25:15 +02:00
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typedef struct PageDesc {
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2004-05-21 16:52:29 +02:00
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/* list of TBs intersecting this ram page */
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2003-05-14 21:00:11 +02:00
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TranslationBlock *first_tb;
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2004-01-04 19:06:42 +01:00
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/* in order to optimize self modifying code, we count the number
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of lookups we do to a given page to use a bitmap */
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unsigned int code_write_count;
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uint8_t *code_bitmap;
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#if defined(CONFIG_USER_ONLY)
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unsigned long flags;
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#endif
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2003-05-13 02:25:15 +02:00
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} PageDesc;
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2004-05-21 16:52:29 +02:00
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typedef struct PhysPageDesc {
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2008-06-09 02:20:13 +02:00
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/* offset in host memory of the page + io_index in the low bits */
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2008-04-27 23:12:55 +02:00
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ram_addr_t phys_offset;
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2004-05-21 16:52:29 +02:00
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} PhysPageDesc;
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2003-05-13 02:25:15 +02:00
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#define L2_BITS 10
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2007-04-05 22:08:21 +02:00
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#if defined(CONFIG_USER_ONLY) && defined(TARGET_VIRT_ADDR_SPACE_BITS)
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/* XXX: this is a temporary hack for alpha target.
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* In the future, this is to be replaced by a multi-level table
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* to actually be able to handle the complete 64 bits address space.
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*/
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#define L1_BITS (TARGET_VIRT_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS)
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#else
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2008-04-22 22:45:18 +02:00
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#define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS)
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2007-04-05 22:08:21 +02:00
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#endif
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2003-05-13 02:25:15 +02:00
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#define L1_SIZE (1 << L1_BITS)
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#define L2_SIZE (1 << L2_BITS)
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2004-07-05 23:25:26 +02:00
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unsigned long qemu_real_host_page_size;
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unsigned long qemu_host_page_bits;
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unsigned long qemu_host_page_size;
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unsigned long qemu_host_page_mask;
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2003-05-13 02:25:15 +02:00
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2004-05-21 16:52:29 +02:00
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/* XXX: for system emulation, it could just be an array */
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2003-05-13 02:25:15 +02:00
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static PageDesc *l1_map[L1_SIZE];
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2008-10-04 09:24:27 +02:00
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static PhysPageDesc **l1_phys_map;
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2003-05-13 02:25:15 +02:00
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2008-06-08 03:09:01 +02:00
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#if !defined(CONFIG_USER_ONLY)
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static void io_mem_init(void);
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2003-08-10 23:47:01 +02:00
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/* io memory support */
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CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
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CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
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2004-06-03 16:01:43 +02:00
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void *io_mem_opaque[IO_MEM_NB_ENTRIES];
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2003-08-10 23:47:01 +02:00
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static int io_mem_nb;
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2007-03-17 00:58:11 +01:00
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static int io_mem_watch;
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#endif
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2003-08-10 23:47:01 +02:00
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2003-10-05 16:28:56 +02:00
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/* log support */
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2008-10-05 11:57:08 +02:00
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static const char *logfilename = "/tmp/qemu.log";
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2003-10-05 16:28:56 +02:00
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FILE *logfile;
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int loglevel;
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2007-06-30 15:53:24 +02:00
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static int log_append = 0;
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2003-10-05 16:28:56 +02:00
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2005-01-26 23:00:47 +01:00
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/* statistics */
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static int tlb_flush_count;
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static int tb_flush_count;
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static int tb_phys_invalidate_count;
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2007-05-26 19:36:03 +02:00
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#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
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typedef struct subpage_t {
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target_phys_addr_t base;
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2008-01-02 20:45:26 +01:00
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CPUReadMemoryFunc **mem_read[TARGET_PAGE_SIZE][4];
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CPUWriteMemoryFunc **mem_write[TARGET_PAGE_SIZE][4];
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void *opaque[TARGET_PAGE_SIZE][2][4];
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2007-05-26 19:36:03 +02:00
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} subpage_t;
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2008-05-10 12:55:51 +02:00
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#ifdef _WIN32
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static void map_exec(void *addr, long size)
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{
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DWORD old_protect;
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VirtualProtect(addr, size,
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PAGE_EXECUTE_READWRITE, &old_protect);
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}
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#else
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static void map_exec(void *addr, long size)
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{
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2008-05-29 11:35:57 +02:00
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unsigned long start, end, page_size;
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2008-05-10 12:55:51 +02:00
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2008-05-29 11:35:57 +02:00
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page_size = getpagesize();
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2008-05-10 12:55:51 +02:00
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start = (unsigned long)addr;
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2008-05-29 11:35:57 +02:00
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start &= ~(page_size - 1);
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2008-05-10 12:55:51 +02:00
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end = (unsigned long)addr + size;
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2008-05-29 11:35:57 +02:00
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end += page_size - 1;
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end &= ~(page_size - 1);
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2008-05-10 12:55:51 +02:00
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mprotect((void *)start, end - start,
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PROT_READ | PROT_WRITE | PROT_EXEC);
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}
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#endif
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2003-06-15 22:05:50 +02:00
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static void page_init(void)
|
2003-05-13 02:25:15 +02:00
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{
|
2004-07-05 23:25:26 +02:00
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/* NOTE: we can always suppose that qemu_host_page_size >=
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2003-05-13 02:25:15 +02:00
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TARGET_PAGE_SIZE */
|
2008-11-11 23:06:42 +01:00
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#ifdef _WIN32
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{
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SYSTEM_INFO system_info;
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GetSystemInfo(&system_info);
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qemu_real_host_page_size = system_info.dwPageSize;
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}
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#else
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qemu_real_host_page_size = getpagesize();
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#endif
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2004-07-05 23:25:26 +02:00
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if (qemu_host_page_size == 0)
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qemu_host_page_size = qemu_real_host_page_size;
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if (qemu_host_page_size < TARGET_PAGE_SIZE)
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qemu_host_page_size = TARGET_PAGE_SIZE;
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qemu_host_page_bits = 0;
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while ((1 << qemu_host_page_bits) < qemu_host_page_size)
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qemu_host_page_bits++;
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qemu_host_page_mask = ~(qemu_host_page_size - 1);
|
2005-07-24 14:55:09 +02:00
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l1_phys_map = qemu_vmalloc(L1_SIZE * sizeof(void *));
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memset(l1_phys_map, 0, L1_SIZE * sizeof(void *));
|
2007-12-12 02:16:23 +01:00
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#if !defined(_WIN32) && defined(CONFIG_USER_ONLY)
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{
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long long startaddr, endaddr;
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FILE *f;
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int n;
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|
2008-06-02 18:16:42 +02:00
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mmap_lock();
|
2008-05-31 18:33:53 +02:00
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last_brk = (unsigned long)sbrk(0);
|
2007-12-12 02:16:23 +01:00
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f = fopen("/proc/self/maps", "r");
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if (f) {
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do {
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n = fscanf (f, "%llx-%llx %*[^\n]\n", &startaddr, &endaddr);
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|
if (n == 2) {
|
2008-05-03 19:51:24 +02:00
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startaddr = MIN(startaddr,
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(1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1);
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endaddr = MIN(endaddr,
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(1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1);
|
2008-05-29 15:56:10 +02:00
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|
page_set_flags(startaddr & TARGET_PAGE_MASK,
|
2007-12-12 02:16:23 +01:00
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|
|
TARGET_PAGE_ALIGN(endaddr),
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PAGE_RESERVED);
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|
}
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|
} while (!feof(f));
|
|
|
|
fclose(f);
|
|
|
|
}
|
2008-06-02 18:16:42 +02:00
|
|
|
mmap_unlock();
|
2007-12-12 02:16:23 +01:00
|
|
|
}
|
|
|
|
#endif
|
2003-05-13 02:25:15 +02:00
|
|
|
}
|
|
|
|
|
2008-09-15 17:56:30 +02:00
|
|
|
static inline PageDesc **page_l1_map(target_ulong index)
|
2003-05-13 02:25:15 +02:00
|
|
|
{
|
2008-06-09 15:47:45 +02:00
|
|
|
#if TARGET_LONG_BITS > 32
|
|
|
|
/* Host memory outside guest VM. For 32-bit targets we have already
|
|
|
|
excluded high addresses. */
|
2008-08-29 15:10:00 +02:00
|
|
|
if (index > ((target_ulong)L2_SIZE * L1_SIZE))
|
2008-06-09 15:47:45 +02:00
|
|
|
return NULL;
|
|
|
|
#endif
|
2008-09-15 17:56:30 +02:00
|
|
|
return &l1_map[index >> L2_BITS];
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline PageDesc *page_find_alloc(target_ulong index)
|
|
|
|
{
|
|
|
|
PageDesc **lp, *p;
|
|
|
|
lp = page_l1_map(index);
|
|
|
|
if (!lp)
|
|
|
|
return NULL;
|
|
|
|
|
2003-05-13 02:25:15 +02:00
|
|
|
p = *lp;
|
|
|
|
if (!p) {
|
|
|
|
/* allocate if not found */
|
2008-06-09 15:47:45 +02:00
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
|
|
unsigned long addr;
|
|
|
|
size_t len = sizeof(PageDesc) * L2_SIZE;
|
|
|
|
/* Don't use qemu_malloc because it may recurse. */
|
|
|
|
p = mmap(0, len, PROT_READ | PROT_WRITE,
|
|
|
|
MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
|
2003-05-13 02:25:15 +02:00
|
|
|
*lp = p;
|
2008-06-09 15:47:45 +02:00
|
|
|
addr = h2g(p);
|
|
|
|
if (addr == (target_ulong)addr) {
|
|
|
|
page_set_flags(addr & TARGET_PAGE_MASK,
|
|
|
|
TARGET_PAGE_ALIGN(addr + len),
|
|
|
|
PAGE_RESERVED);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
p = qemu_mallocz(sizeof(PageDesc) * L2_SIZE);
|
|
|
|
*lp = p;
|
|
|
|
#endif
|
2003-05-13 02:25:15 +02:00
|
|
|
}
|
|
|
|
return p + (index & (L2_SIZE - 1));
|
|
|
|
}
|
|
|
|
|
2008-04-27 23:12:55 +02:00
|
|
|
static inline PageDesc *page_find(target_ulong index)
|
2003-05-13 02:25:15 +02:00
|
|
|
{
|
2008-09-15 17:56:30 +02:00
|
|
|
PageDesc **lp, *p;
|
|
|
|
lp = page_l1_map(index);
|
|
|
|
if (!lp)
|
|
|
|
return NULL;
|
2003-05-13 02:25:15 +02:00
|
|
|
|
2008-09-15 17:56:30 +02:00
|
|
|
p = *lp;
|
2003-05-13 02:25:15 +02:00
|
|
|
if (!p)
|
|
|
|
return 0;
|
2003-05-14 21:00:11 +02:00
|
|
|
return p + (index & (L2_SIZE - 1));
|
|
|
|
}
|
|
|
|
|
2005-07-24 14:55:09 +02:00
|
|
|
static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
|
2004-05-21 16:52:29 +02:00
|
|
|
{
|
2005-07-24 14:55:09 +02:00
|
|
|
void **lp, **p;
|
2006-04-08 22:02:06 +02:00
|
|
|
PhysPageDesc *pd;
|
2004-05-21 16:52:29 +02:00
|
|
|
|
2005-07-24 14:55:09 +02:00
|
|
|
p = (void **)l1_phys_map;
|
|
|
|
#if TARGET_PHYS_ADDR_SPACE_BITS > 32
|
|
|
|
|
|
|
|
#if TARGET_PHYS_ADDR_SPACE_BITS > (32 + L1_BITS)
|
|
|
|
#error unsupported TARGET_PHYS_ADDR_SPACE_BITS
|
|
|
|
#endif
|
|
|
|
lp = p + ((index >> (L1_BITS + L2_BITS)) & (L1_SIZE - 1));
|
2004-05-21 16:52:29 +02:00
|
|
|
p = *lp;
|
|
|
|
if (!p) {
|
|
|
|
/* allocate if not found */
|
2005-07-24 14:55:09 +02:00
|
|
|
if (!alloc)
|
|
|
|
return NULL;
|
|
|
|
p = qemu_vmalloc(sizeof(void *) * L1_SIZE);
|
|
|
|
memset(p, 0, sizeof(void *) * L1_SIZE);
|
|
|
|
*lp = p;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
lp = p + ((index >> L2_BITS) & (L1_SIZE - 1));
|
2006-04-08 22:02:06 +02:00
|
|
|
pd = *lp;
|
|
|
|
if (!pd) {
|
|
|
|
int i;
|
2005-07-24 14:55:09 +02:00
|
|
|
/* allocate if not found */
|
|
|
|
if (!alloc)
|
|
|
|
return NULL;
|
2006-04-08 22:02:06 +02:00
|
|
|
pd = qemu_vmalloc(sizeof(PhysPageDesc) * L2_SIZE);
|
|
|
|
*lp = pd;
|
|
|
|
for (i = 0; i < L2_SIZE; i++)
|
|
|
|
pd[i].phys_offset = IO_MEM_UNASSIGNED;
|
2004-05-21 16:52:29 +02:00
|
|
|
}
|
2006-04-08 22:02:06 +02:00
|
|
|
return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1));
|
2004-05-21 16:52:29 +02:00
|
|
|
}
|
|
|
|
|
2005-07-24 14:55:09 +02:00
|
|
|
static inline PhysPageDesc *phys_page_find(target_phys_addr_t index)
|
2004-05-21 16:52:29 +02:00
|
|
|
{
|
2005-07-24 14:55:09 +02:00
|
|
|
return phys_page_find_alloc(index, 0);
|
2004-05-21 16:52:29 +02:00
|
|
|
}
|
|
|
|
|
2004-01-04 19:06:42 +01:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2005-11-22 00:25:50 +01:00
|
|
|
static void tlb_protect_code(ram_addr_t ram_addr);
|
2007-09-16 23:08:06 +02:00
|
|
|
static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
|
2005-08-21 11:26:42 +02:00
|
|
|
target_ulong vaddr);
|
2008-06-02 18:16:42 +02:00
|
|
|
#define mmap_lock() do { } while(0)
|
|
|
|
#define mmap_unlock() do { } while(0)
|
2004-01-04 19:06:42 +01:00
|
|
|
#endif
|
2003-05-14 21:00:11 +02:00
|
|
|
|
2008-05-29 11:35:57 +02:00
|
|
|
#define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024)
|
|
|
|
|
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
|
|
/* Currently it is not recommanded to allocate big chunks of data in
|
|
|
|
user mode. It will change when a dedicated libc will be used */
|
|
|
|
#define USE_STATIC_CODE_GEN_BUFFER
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef USE_STATIC_CODE_GEN_BUFFER
|
|
|
|
static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE];
|
|
|
|
#endif
|
|
|
|
|
2008-08-17 22:26:25 +02:00
|
|
|
static void code_gen_alloc(unsigned long tb_size)
|
2008-05-28 14:30:31 +02:00
|
|
|
{
|
2008-05-29 11:35:57 +02:00
|
|
|
#ifdef USE_STATIC_CODE_GEN_BUFFER
|
|
|
|
code_gen_buffer = static_code_gen_buffer;
|
|
|
|
code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
|
|
|
|
map_exec(code_gen_buffer, code_gen_buffer_size);
|
|
|
|
#else
|
2008-05-28 14:30:31 +02:00
|
|
|
code_gen_buffer_size = tb_size;
|
|
|
|
if (code_gen_buffer_size == 0) {
|
2008-05-29 11:35:57 +02:00
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
|
|
/* in user mode, phys_ram_size is not meaningful */
|
|
|
|
code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
|
|
|
|
#else
|
2008-05-28 14:30:31 +02:00
|
|
|
/* XXX: needs ajustments */
|
2008-09-24 16:10:36 +02:00
|
|
|
code_gen_buffer_size = (unsigned long)(phys_ram_size / 4);
|
2008-05-29 11:35:57 +02:00
|
|
|
#endif
|
2008-05-28 14:30:31 +02:00
|
|
|
}
|
|
|
|
if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE)
|
|
|
|
code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE;
|
|
|
|
/* The code gen buffer location may have constraints depending on
|
|
|
|
the host cpu and OS */
|
|
|
|
#if defined(__linux__)
|
|
|
|
{
|
|
|
|
int flags;
|
2008-07-26 17:05:57 +02:00
|
|
|
void *start = NULL;
|
|
|
|
|
2008-05-28 14:30:31 +02:00
|
|
|
flags = MAP_PRIVATE | MAP_ANONYMOUS;
|
|
|
|
#if defined(__x86_64__)
|
|
|
|
flags |= MAP_32BIT;
|
|
|
|
/* Cannot map more than that */
|
|
|
|
if (code_gen_buffer_size > (800 * 1024 * 1024))
|
|
|
|
code_gen_buffer_size = (800 * 1024 * 1024);
|
2008-07-26 17:05:57 +02:00
|
|
|
#elif defined(__sparc_v9__)
|
|
|
|
// Map the buffer below 2G, so we can use direct calls and branches
|
|
|
|
flags |= MAP_FIXED;
|
|
|
|
start = (void *) 0x60000000UL;
|
|
|
|
if (code_gen_buffer_size > (512 * 1024 * 1024))
|
|
|
|
code_gen_buffer_size = (512 * 1024 * 1024);
|
2008-05-28 14:30:31 +02:00
|
|
|
#endif
|
2008-07-26 17:05:57 +02:00
|
|
|
code_gen_buffer = mmap(start, code_gen_buffer_size,
|
|
|
|
PROT_WRITE | PROT_READ | PROT_EXEC,
|
2008-05-28 14:30:31 +02:00
|
|
|
flags, -1, 0);
|
|
|
|
if (code_gen_buffer == MAP_FAILED) {
|
|
|
|
fprintf(stderr, "Could not allocate dynamic translator buffer\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
}
|
2008-09-27 17:32:41 +02:00
|
|
|
#elif defined(__FreeBSD__)
|
|
|
|
{
|
|
|
|
int flags;
|
|
|
|
void *addr = NULL;
|
|
|
|
flags = MAP_PRIVATE | MAP_ANONYMOUS;
|
|
|
|
#if defined(__x86_64__)
|
|
|
|
/* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume
|
|
|
|
* 0x40000000 is free */
|
|
|
|
flags |= MAP_FIXED;
|
|
|
|
addr = (void *)0x40000000;
|
|
|
|
/* Cannot map more than that */
|
|
|
|
if (code_gen_buffer_size > (800 * 1024 * 1024))
|
|
|
|
code_gen_buffer_size = (800 * 1024 * 1024);
|
|
|
|
#endif
|
|
|
|
code_gen_buffer = mmap(addr, code_gen_buffer_size,
|
|
|
|
PROT_WRITE | PROT_READ | PROT_EXEC,
|
|
|
|
flags, -1, 0);
|
|
|
|
if (code_gen_buffer == MAP_FAILED) {
|
|
|
|
fprintf(stderr, "Could not allocate dynamic translator buffer\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
}
|
2008-05-28 14:30:31 +02:00
|
|
|
#else
|
|
|
|
code_gen_buffer = qemu_malloc(code_gen_buffer_size);
|
|
|
|
if (!code_gen_buffer) {
|
|
|
|
fprintf(stderr, "Could not allocate dynamic translator buffer\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
map_exec(code_gen_buffer, code_gen_buffer_size);
|
|
|
|
#endif
|
2008-05-29 11:35:57 +02:00
|
|
|
#endif /* !USE_STATIC_CODE_GEN_BUFFER */
|
2008-05-28 14:30:31 +02:00
|
|
|
map_exec(code_gen_prologue, sizeof(code_gen_prologue));
|
|
|
|
code_gen_buffer_max_size = code_gen_buffer_size -
|
|
|
|
code_gen_max_block_size();
|
|
|
|
code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE;
|
|
|
|
tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock));
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Must be called before using the QEMU cpus. 'tb_size' is the size
|
|
|
|
(in bytes) allocated to the translation buffer. Zero means default
|
|
|
|
size. */
|
|
|
|
void cpu_exec_init_all(unsigned long tb_size)
|
|
|
|
{
|
|
|
|
cpu_gen_init();
|
|
|
|
code_gen_alloc(tb_size);
|
|
|
|
code_gen_ptr = code_gen_buffer;
|
2008-05-29 11:35:57 +02:00
|
|
|
page_init();
|
2008-06-08 03:09:01 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2008-05-28 14:30:31 +02:00
|
|
|
io_mem_init();
|
2008-06-08 03:09:01 +02:00
|
|
|
#endif
|
2008-05-28 14:30:31 +02:00
|
|
|
}
|
|
|
|
|
2008-07-01 22:01:19 +02:00
|
|
|
#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
|
|
|
|
|
|
|
|
#define CPU_COMMON_SAVE_VERSION 1
|
|
|
|
|
|
|
|
static void cpu_common_save(QEMUFile *f, void *opaque)
|
|
|
|
{
|
|
|
|
CPUState *env = opaque;
|
|
|
|
|
|
|
|
qemu_put_be32s(f, &env->halted);
|
|
|
|
qemu_put_be32s(f, &env->interrupt_request);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int cpu_common_load(QEMUFile *f, void *opaque, int version_id)
|
|
|
|
{
|
|
|
|
CPUState *env = opaque;
|
|
|
|
|
|
|
|
if (version_id != CPU_COMMON_SAVE_VERSION)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
qemu_get_be32s(f, &env->halted);
|
2008-07-01 23:53:33 +02:00
|
|
|
qemu_get_be32s(f, &env->interrupt_request);
|
2008-07-01 22:01:19 +02:00
|
|
|
tlb_flush(env, 1);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2005-11-22 00:25:50 +01:00
|
|
|
void cpu_exec_init(CPUState *env)
|
2003-05-14 21:00:11 +02:00
|
|
|
{
|
2005-11-22 00:25:50 +01:00
|
|
|
CPUState **penv;
|
|
|
|
int cpu_index;
|
|
|
|
|
|
|
|
env->next_cpu = NULL;
|
|
|
|
penv = &first_cpu;
|
|
|
|
cpu_index = 0;
|
|
|
|
while (*penv != NULL) {
|
|
|
|
penv = (CPUState **)&(*penv)->next_cpu;
|
|
|
|
cpu_index++;
|
|
|
|
}
|
|
|
|
env->cpu_index = cpu_index;
|
|
|
|
*penv = env;
|
2008-06-30 18:31:04 +02:00
|
|
|
#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
|
2008-07-01 22:01:19 +02:00
|
|
|
register_savevm("cpu_common", cpu_index, CPU_COMMON_SAVE_VERSION,
|
|
|
|
cpu_common_save, cpu_common_load, env);
|
2008-06-30 18:31:04 +02:00
|
|
|
register_savevm("cpu", cpu_index, CPU_SAVE_VERSION,
|
|
|
|
cpu_save, cpu_load, env);
|
|
|
|
#endif
|
2003-05-14 21:00:11 +02:00
|
|
|
}
|
|
|
|
|
2004-01-04 19:06:42 +01:00
|
|
|
static inline void invalidate_page_bitmap(PageDesc *p)
|
|
|
|
{
|
|
|
|
if (p->code_bitmap) {
|
2004-02-16 23:01:13 +01:00
|
|
|
qemu_free(p->code_bitmap);
|
2004-01-04 19:06:42 +01:00
|
|
|
p->code_bitmap = NULL;
|
|
|
|
}
|
|
|
|
p->code_write_count = 0;
|
|
|
|
}
|
|
|
|
|
2003-05-14 21:00:11 +02:00
|
|
|
/* set to NULL all the 'first_tb' fields in all PageDescs */
|
|
|
|
static void page_flush_tb(void)
|
|
|
|
{
|
|
|
|
int i, j;
|
|
|
|
PageDesc *p;
|
|
|
|
|
|
|
|
for(i = 0; i < L1_SIZE; i++) {
|
|
|
|
p = l1_map[i];
|
|
|
|
if (p) {
|
2004-01-04 19:06:42 +01:00
|
|
|
for(j = 0; j < L2_SIZE; j++) {
|
|
|
|
p->first_tb = NULL;
|
|
|
|
invalidate_page_bitmap(p);
|
|
|
|
p++;
|
|
|
|
}
|
2003-05-14 21:00:11 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* flush all the translation blocks */
|
2003-05-25 18:46:15 +02:00
|
|
|
/* XXX: tb_flush is currently not thread safe */
|
2005-11-22 00:25:50 +01:00
|
|
|
void tb_flush(CPUState *env1)
|
2003-05-14 21:00:11 +02:00
|
|
|
{
|
2005-11-22 00:25:50 +01:00
|
|
|
CPUState *env;
|
2004-01-04 16:48:17 +01:00
|
|
|
#if defined(DEBUG_FLUSH)
|
2007-11-04 08:31:40 +01:00
|
|
|
printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
|
|
|
|
(unsigned long)(code_gen_ptr - code_gen_buffer),
|
|
|
|
nb_tbs, nb_tbs > 0 ?
|
|
|
|
((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0);
|
2003-05-14 21:00:11 +02:00
|
|
|
#endif
|
2008-05-28 14:30:31 +02:00
|
|
|
if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size)
|
2008-03-31 19:07:36 +02:00
|
|
|
cpu_abort(env1, "Internal error: code buffer overflow\n");
|
|
|
|
|
2003-05-14 21:00:11 +02:00
|
|
|
nb_tbs = 0;
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2005-11-22 00:25:50 +01:00
|
|
|
for(env = first_cpu; env != NULL; env = env->next_cpu) {
|
|
|
|
memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
|
|
|
|
}
|
2004-01-04 19:06:42 +01:00
|
|
|
|
2004-10-03 15:36:49 +02:00
|
|
|
memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *));
|
2003-05-14 21:00:11 +02:00
|
|
|
page_flush_tb();
|
2004-01-04 19:06:42 +01:00
|
|
|
|
2003-05-14 21:00:11 +02:00
|
|
|
code_gen_ptr = code_gen_buffer;
|
2003-05-25 18:46:15 +02:00
|
|
|
/* XXX: flush processor icache at this point if cache flush is
|
|
|
|
expensive */
|
2005-01-26 23:00:47 +01:00
|
|
|
tb_flush_count++;
|
2003-05-14 21:00:11 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef DEBUG_TB_CHECK
|
|
|
|
|
2007-04-04 09:55:12 +02:00
|
|
|
static void tb_invalidate_check(target_ulong address)
|
2003-05-14 21:00:11 +02:00
|
|
|
{
|
|
|
|
TranslationBlock *tb;
|
|
|
|
int i;
|
|
|
|
address &= TARGET_PAGE_MASK;
|
2006-04-16 17:14:59 +02:00
|
|
|
for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
|
|
|
|
for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
|
2003-05-14 21:00:11 +02:00
|
|
|
if (!(address + TARGET_PAGE_SIZE <= tb->pc ||
|
|
|
|
address >= tb->pc + tb->size)) {
|
|
|
|
printf("ERROR invalidate: address=%08lx PC=%08lx size=%04x\n",
|
2006-04-16 17:14:59 +02:00
|
|
|
address, (long)tb->pc, tb->size);
|
2003-05-14 21:00:11 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* verify that all the pages have correct rights for code */
|
|
|
|
static void tb_page_check(void)
|
|
|
|
{
|
|
|
|
TranslationBlock *tb;
|
|
|
|
int i, flags1, flags2;
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2006-04-16 17:14:59 +02:00
|
|
|
for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
|
|
|
|
for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
|
2003-05-14 21:00:11 +02:00
|
|
|
flags1 = page_get_flags(tb->pc);
|
|
|
|
flags2 = page_get_flags(tb->pc + tb->size - 1);
|
|
|
|
if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) {
|
|
|
|
printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
|
2006-04-16 17:14:59 +02:00
|
|
|
(long)tb->pc, tb->size, flags1, flags2);
|
2003-05-14 21:00:11 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-10-04 09:24:27 +02:00
|
|
|
static void tb_jmp_check(TranslationBlock *tb)
|
2003-05-25 18:46:15 +02:00
|
|
|
{
|
|
|
|
TranslationBlock *tb1;
|
|
|
|
unsigned int n1;
|
|
|
|
|
|
|
|
/* suppress any remaining jumps to this TB */
|
|
|
|
tb1 = tb->jmp_first;
|
|
|
|
for(;;) {
|
|
|
|
n1 = (long)tb1 & 3;
|
|
|
|
tb1 = (TranslationBlock *)((long)tb1 & ~3);
|
|
|
|
if (n1 == 2)
|
|
|
|
break;
|
|
|
|
tb1 = tb1->jmp_next[n1];
|
|
|
|
}
|
|
|
|
/* check end of list */
|
|
|
|
if (tb1 != tb) {
|
|
|
|
printf("ERROR: jmp_list from 0x%08lx\n", (long)tb);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2003-05-14 21:00:11 +02:00
|
|
|
#endif
|
|
|
|
|
|
|
|
/* invalidate one TB */
|
|
|
|
static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb,
|
|
|
|
int next_offset)
|
|
|
|
{
|
|
|
|
TranslationBlock *tb1;
|
|
|
|
for(;;) {
|
|
|
|
tb1 = *ptb;
|
|
|
|
if (tb1 == tb) {
|
|
|
|
*ptb = *(TranslationBlock **)((char *)tb1 + next_offset);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
ptb = (TranslationBlock **)((char *)tb1 + next_offset);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2004-01-04 19:06:42 +01:00
|
|
|
static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb)
|
|
|
|
{
|
|
|
|
TranslationBlock *tb1;
|
|
|
|
unsigned int n1;
|
|
|
|
|
|
|
|
for(;;) {
|
|
|
|
tb1 = *ptb;
|
|
|
|
n1 = (long)tb1 & 3;
|
|
|
|
tb1 = (TranslationBlock *)((long)tb1 & ~3);
|
|
|
|
if (tb1 == tb) {
|
|
|
|
*ptb = tb1->page_next[n1];
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
ptb = &tb1->page_next[n1];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2003-05-25 18:46:15 +02:00
|
|
|
static inline void tb_jmp_remove(TranslationBlock *tb, int n)
|
|
|
|
{
|
|
|
|
TranslationBlock *tb1, **ptb;
|
|
|
|
unsigned int n1;
|
|
|
|
|
|
|
|
ptb = &tb->jmp_next[n];
|
|
|
|
tb1 = *ptb;
|
|
|
|
if (tb1) {
|
|
|
|
/* find tb(n) in circular list */
|
|
|
|
for(;;) {
|
|
|
|
tb1 = *ptb;
|
|
|
|
n1 = (long)tb1 & 3;
|
|
|
|
tb1 = (TranslationBlock *)((long)tb1 & ~3);
|
|
|
|
if (n1 == n && tb1 == tb)
|
|
|
|
break;
|
|
|
|
if (n1 == 2) {
|
|
|
|
ptb = &tb1->jmp_first;
|
|
|
|
} else {
|
|
|
|
ptb = &tb1->jmp_next[n1];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/* now we can suppress tb(n) from the list */
|
|
|
|
*ptb = tb->jmp_next[n];
|
|
|
|
|
|
|
|
tb->jmp_next[n] = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* reset the jump entry 'n' of a TB so that it is not chained to
|
|
|
|
another TB */
|
|
|
|
static inline void tb_reset_jump(TranslationBlock *tb, int n)
|
|
|
|
{
|
|
|
|
tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n]));
|
|
|
|
}
|
|
|
|
|
2008-06-29 03:03:05 +02:00
|
|
|
void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr)
|
2003-05-14 21:00:11 +02:00
|
|
|
{
|
2005-11-22 00:25:50 +01:00
|
|
|
CPUState *env;
|
2005-11-20 11:35:40 +01:00
|
|
|
PageDesc *p;
|
2003-05-25 18:46:15 +02:00
|
|
|
unsigned int h, n1;
|
2008-04-27 23:12:55 +02:00
|
|
|
target_phys_addr_t phys_pc;
|
2005-11-20 11:35:40 +01:00
|
|
|
TranslationBlock *tb1, *tb2;
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2005-11-20 11:35:40 +01:00
|
|
|
/* remove the TB from the hash list */
|
|
|
|
phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
|
|
|
|
h = tb_phys_hash_func(phys_pc);
|
2007-09-16 23:08:06 +02:00
|
|
|
tb_remove(&tb_phys_hash[h], tb,
|
2005-11-20 11:35:40 +01:00
|
|
|
offsetof(TranslationBlock, phys_hash_next));
|
|
|
|
|
|
|
|
/* remove the TB from the page list */
|
|
|
|
if (tb->page_addr[0] != page_addr) {
|
|
|
|
p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
|
|
|
|
tb_page_remove(&p->first_tb, tb);
|
|
|
|
invalidate_page_bitmap(p);
|
|
|
|
}
|
|
|
|
if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) {
|
|
|
|
p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
|
|
|
|
tb_page_remove(&p->first_tb, tb);
|
|
|
|
invalidate_page_bitmap(p);
|
|
|
|
}
|
|
|
|
|
2003-11-19 23:12:02 +01:00
|
|
|
tb_invalidated_flag = 1;
|
2004-02-16 23:01:13 +01:00
|
|
|
|
2003-05-14 21:00:11 +02:00
|
|
|
/* remove the TB from the hash list */
|
2005-11-20 11:35:40 +01:00
|
|
|
h = tb_jmp_cache_hash_func(tb->pc);
|
2005-11-22 00:25:50 +01:00
|
|
|
for(env = first_cpu; env != NULL; env = env->next_cpu) {
|
|
|
|
if (env->tb_jmp_cache[h] == tb)
|
|
|
|
env->tb_jmp_cache[h] = NULL;
|
|
|
|
}
|
2003-05-25 18:46:15 +02:00
|
|
|
|
|
|
|
/* suppress this TB from the two jump lists */
|
|
|
|
tb_jmp_remove(tb, 0);
|
|
|
|
tb_jmp_remove(tb, 1);
|
|
|
|
|
|
|
|
/* suppress any remaining jumps to this TB */
|
|
|
|
tb1 = tb->jmp_first;
|
|
|
|
for(;;) {
|
|
|
|
n1 = (long)tb1 & 3;
|
|
|
|
if (n1 == 2)
|
|
|
|
break;
|
|
|
|
tb1 = (TranslationBlock *)((long)tb1 & ~3);
|
|
|
|
tb2 = tb1->jmp_next[n1];
|
|
|
|
tb_reset_jump(tb1, n1);
|
|
|
|
tb1->jmp_next[n1] = NULL;
|
|
|
|
tb1 = tb2;
|
|
|
|
}
|
|
|
|
tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */
|
2004-01-04 19:06:42 +01:00
|
|
|
|
2005-01-26 23:00:47 +01:00
|
|
|
tb_phys_invalidate_count++;
|
2004-01-04 19:06:42 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void set_bits(uint8_t *tab, int start, int len)
|
|
|
|
{
|
|
|
|
int end, mask, end1;
|
|
|
|
|
|
|
|
end = start + len;
|
|
|
|
tab += start >> 3;
|
|
|
|
mask = 0xff << (start & 7);
|
|
|
|
if ((start & ~7) == (end & ~7)) {
|
|
|
|
if (start < end) {
|
|
|
|
mask &= ~(0xff << (end & 7));
|
|
|
|
*tab |= mask;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
*tab++ |= mask;
|
|
|
|
start = (start + 8) & ~7;
|
|
|
|
end1 = end & ~7;
|
|
|
|
while (start < end1) {
|
|
|
|
*tab++ = 0xff;
|
|
|
|
start += 8;
|
|
|
|
}
|
|
|
|
if (start < end) {
|
|
|
|
mask = ~(0xff << (end & 7));
|
|
|
|
*tab |= mask;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void build_page_bitmap(PageDesc *p)
|
|
|
|
{
|
|
|
|
int n, tb_start, tb_end;
|
|
|
|
TranslationBlock *tb;
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2008-06-09 15:57:23 +02:00
|
|
|
p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8);
|
2004-01-04 19:06:42 +01:00
|
|
|
if (!p->code_bitmap)
|
|
|
|
return;
|
|
|
|
|
|
|
|
tb = p->first_tb;
|
|
|
|
while (tb != NULL) {
|
|
|
|
n = (long)tb & 3;
|
|
|
|
tb = (TranslationBlock *)((long)tb & ~3);
|
|
|
|
/* NOTE: this is subtle as a TB may span two physical pages */
|
|
|
|
if (n == 0) {
|
|
|
|
/* NOTE: tb_end may be after the end of the page, but
|
|
|
|
it is not a problem */
|
|
|
|
tb_start = tb->pc & ~TARGET_PAGE_MASK;
|
|
|
|
tb_end = tb_start + tb->size;
|
|
|
|
if (tb_end > TARGET_PAGE_SIZE)
|
|
|
|
tb_end = TARGET_PAGE_SIZE;
|
|
|
|
} else {
|
|
|
|
tb_start = 0;
|
|
|
|
tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
|
|
|
|
}
|
|
|
|
set_bits(p->code_bitmap, tb_start, tb_end - tb_start);
|
|
|
|
tb = tb->page_next[n];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-06-29 03:03:05 +02:00
|
|
|
TranslationBlock *tb_gen_code(CPUState *env,
|
|
|
|
target_ulong pc, target_ulong cs_base,
|
|
|
|
int flags, int cflags)
|
2004-04-25 19:57:43 +02:00
|
|
|
{
|
|
|
|
TranslationBlock *tb;
|
|
|
|
uint8_t *tc_ptr;
|
|
|
|
target_ulong phys_pc, phys_page2, virt_page2;
|
|
|
|
int code_gen_size;
|
|
|
|
|
2005-01-04 00:35:10 +01:00
|
|
|
phys_pc = get_phys_addr_code(env, pc);
|
|
|
|
tb = tb_alloc(pc);
|
2004-04-25 19:57:43 +02:00
|
|
|
if (!tb) {
|
|
|
|
/* flush must be done */
|
|
|
|
tb_flush(env);
|
|
|
|
/* cannot fail at this point */
|
2005-01-04 00:35:10 +01:00
|
|
|
tb = tb_alloc(pc);
|
2008-06-29 03:03:05 +02:00
|
|
|
/* Don't forget to invalidate previous TB info. */
|
|
|
|
tb_invalidated_flag = 1;
|
2004-04-25 19:57:43 +02:00
|
|
|
}
|
|
|
|
tc_ptr = code_gen_ptr;
|
|
|
|
tb->tc_ptr = tc_ptr;
|
|
|
|
tb->cs_base = cs_base;
|
|
|
|
tb->flags = flags;
|
|
|
|
tb->cflags = cflags;
|
2007-12-11 20:35:45 +01:00
|
|
|
cpu_gen_code(env, tb, &code_gen_size);
|
2004-04-25 19:57:43 +02:00
|
|
|
code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2004-04-25 19:57:43 +02:00
|
|
|
/* check next page if needed */
|
2005-01-04 00:35:10 +01:00
|
|
|
virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
|
2004-04-25 19:57:43 +02:00
|
|
|
phys_page2 = -1;
|
2005-01-04 00:35:10 +01:00
|
|
|
if ((pc & TARGET_PAGE_MASK) != virt_page2) {
|
2004-04-25 19:57:43 +02:00
|
|
|
phys_page2 = get_phys_addr_code(env, virt_page2);
|
|
|
|
}
|
|
|
|
tb_link_phys(tb, phys_pc, phys_page2);
|
2008-06-29 03:03:05 +02:00
|
|
|
return tb;
|
2004-04-25 19:57:43 +02:00
|
|
|
}
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2004-01-04 19:06:42 +01:00
|
|
|
/* invalidate all TBs which intersect with the target physical page
|
|
|
|
starting in range [start;end[. NOTE: start and end must refer to
|
2004-04-25 19:57:43 +02:00
|
|
|
the same physical page. 'is_cpu_write_access' should be true if called
|
|
|
|
from a real cpu write access: the virtual CPU will exit the current
|
|
|
|
TB if code is modified inside this TB. */
|
2008-04-27 23:12:55 +02:00
|
|
|
void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
|
2004-04-25 19:57:43 +02:00
|
|
|
int is_cpu_write_access)
|
|
|
|
{
|
2008-11-18 20:46:41 +01:00
|
|
|
TranslationBlock *tb, *tb_next, *saved_tb;
|
2004-04-25 19:57:43 +02:00
|
|
|
CPUState *env = cpu_single_env;
|
2004-01-04 19:06:42 +01:00
|
|
|
target_ulong tb_start, tb_end;
|
2008-11-18 20:46:41 +01:00
|
|
|
PageDesc *p;
|
|
|
|
int n;
|
|
|
|
#ifdef TARGET_HAS_PRECISE_SMC
|
|
|
|
int current_tb_not_found = is_cpu_write_access;
|
|
|
|
TranslationBlock *current_tb = NULL;
|
|
|
|
int current_tb_modified = 0;
|
|
|
|
target_ulong current_pc = 0;
|
|
|
|
target_ulong current_cs_base = 0;
|
|
|
|
int current_flags = 0;
|
|
|
|
#endif /* TARGET_HAS_PRECISE_SMC */
|
2004-01-04 19:06:42 +01:00
|
|
|
|
|
|
|
p = page_find(start >> TARGET_PAGE_BITS);
|
2007-09-16 23:08:06 +02:00
|
|
|
if (!p)
|
2004-01-04 19:06:42 +01:00
|
|
|
return;
|
2007-09-16 23:08:06 +02:00
|
|
|
if (!p->code_bitmap &&
|
2004-04-25 19:57:43 +02:00
|
|
|
++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD &&
|
|
|
|
is_cpu_write_access) {
|
2004-01-04 19:06:42 +01:00
|
|
|
/* build code bitmap */
|
|
|
|
build_page_bitmap(p);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* we remove all the TBs in the range [start, end[ */
|
|
|
|
/* XXX: see if in some cases it could be faster to invalidate all the code */
|
|
|
|
tb = p->first_tb;
|
|
|
|
while (tb != NULL) {
|
|
|
|
n = (long)tb & 3;
|
|
|
|
tb = (TranslationBlock *)((long)tb & ~3);
|
|
|
|
tb_next = tb->page_next[n];
|
|
|
|
/* NOTE: this is subtle as a TB may span two physical pages */
|
|
|
|
if (n == 0) {
|
|
|
|
/* NOTE: tb_end may be after the end of the page, but
|
|
|
|
it is not a problem */
|
|
|
|
tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
|
|
|
|
tb_end = tb_start + tb->size;
|
|
|
|
} else {
|
|
|
|
tb_start = tb->page_addr[1];
|
|
|
|
tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
|
|
|
|
}
|
|
|
|
if (!(tb_end <= start || tb_start >= end)) {
|
2004-04-25 19:57:43 +02:00
|
|
|
#ifdef TARGET_HAS_PRECISE_SMC
|
|
|
|
if (current_tb_not_found) {
|
|
|
|
current_tb_not_found = 0;
|
|
|
|
current_tb = NULL;
|
2008-06-29 03:03:05 +02:00
|
|
|
if (env->mem_io_pc) {
|
2004-04-25 19:57:43 +02:00
|
|
|
/* now we have a real cpu fault */
|
2008-06-29 03:03:05 +02:00
|
|
|
current_tb = tb_find_pc(env->mem_io_pc);
|
2004-04-25 19:57:43 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
if (current_tb == tb &&
|
2008-06-29 03:03:05 +02:00
|
|
|
(current_tb->cflags & CF_COUNT_MASK) != 1) {
|
2004-04-25 19:57:43 +02:00
|
|
|
/* If we are modifying the current TB, we must stop
|
|
|
|
its execution. We could be more precise by checking
|
|
|
|
that the modification is after the current PC, but it
|
|
|
|
would require a specialized function to partially
|
|
|
|
restore the CPU state */
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2004-04-25 19:57:43 +02:00
|
|
|
current_tb_modified = 1;
|
2007-09-16 23:08:06 +02:00
|
|
|
cpu_restore_state(current_tb, env,
|
2008-06-29 03:03:05 +02:00
|
|
|
env->mem_io_pc, NULL);
|
2008-11-18 20:46:41 +01:00
|
|
|
cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base,
|
|
|
|
¤t_flags);
|
2004-04-25 19:57:43 +02:00
|
|
|
}
|
|
|
|
#endif /* TARGET_HAS_PRECISE_SMC */
|
2005-11-26 21:12:28 +01:00
|
|
|
/* we need to do that to handle the case where a signal
|
|
|
|
occurs while doing tb_phys_invalidate() */
|
|
|
|
saved_tb = NULL;
|
|
|
|
if (env) {
|
|
|
|
saved_tb = env->current_tb;
|
|
|
|
env->current_tb = NULL;
|
|
|
|
}
|
2004-01-04 19:06:42 +01:00
|
|
|
tb_phys_invalidate(tb, -1);
|
2005-11-26 21:12:28 +01:00
|
|
|
if (env) {
|
|
|
|
env->current_tb = saved_tb;
|
|
|
|
if (env->interrupt_request && env->current_tb)
|
|
|
|
cpu_interrupt(env, env->interrupt_request);
|
|
|
|
}
|
2004-01-04 19:06:42 +01:00
|
|
|
}
|
|
|
|
tb = tb_next;
|
|
|
|
}
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
/* if no code remaining, no need to continue to use slow writes */
|
|
|
|
if (!p->first_tb) {
|
|
|
|
invalidate_page_bitmap(p);
|
2004-04-25 19:57:43 +02:00
|
|
|
if (is_cpu_write_access) {
|
2008-06-29 03:03:05 +02:00
|
|
|
tlb_unprotect_code_phys(env, start, env->mem_io_vaddr);
|
2004-04-25 19:57:43 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#ifdef TARGET_HAS_PRECISE_SMC
|
|
|
|
if (current_tb_modified) {
|
|
|
|
/* we generate a block containing just the instruction
|
|
|
|
modifying the memory. It will ensure that it cannot modify
|
|
|
|
itself */
|
2004-06-14 20:56:36 +02:00
|
|
|
env->current_tb = NULL;
|
2008-06-29 03:03:05 +02:00
|
|
|
tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
|
2004-04-25 19:57:43 +02:00
|
|
|
cpu_resume_from_signal(env, NULL);
|
2004-01-04 19:06:42 +01:00
|
|
|
}
|
2003-05-14 21:00:11 +02:00
|
|
|
#endif
|
2004-01-04 19:06:42 +01:00
|
|
|
}
|
2003-05-14 21:00:11 +02:00
|
|
|
|
2004-01-04 19:06:42 +01:00
|
|
|
/* len must be <= 8 and start must be a multiple of len */
|
2008-04-27 23:12:55 +02:00
|
|
|
static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len)
|
2004-01-04 19:06:42 +01:00
|
|
|
{
|
|
|
|
PageDesc *p;
|
|
|
|
int offset, b;
|
2004-02-16 23:01:13 +01:00
|
|
|
#if 0
|
2004-06-03 16:01:43 +02:00
|
|
|
if (1) {
|
|
|
|
if (loglevel) {
|
2007-09-16 23:08:06 +02:00
|
|
|
fprintf(logfile, "modifying code at 0x%x size=%d EIP=%x PC=%08x\n",
|
2008-06-29 03:03:05 +02:00
|
|
|
cpu_single_env->mem_io_vaddr, len,
|
2007-09-16 23:08:06 +02:00
|
|
|
cpu_single_env->eip,
|
2004-06-03 16:01:43 +02:00
|
|
|
cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base);
|
|
|
|
}
|
2004-02-16 23:01:13 +01:00
|
|
|
}
|
|
|
|
#endif
|
2004-01-04 19:06:42 +01:00
|
|
|
p = page_find(start >> TARGET_PAGE_BITS);
|
2007-09-16 23:08:06 +02:00
|
|
|
if (!p)
|
2004-01-04 19:06:42 +01:00
|
|
|
return;
|
|
|
|
if (p->code_bitmap) {
|
|
|
|
offset = start & ~TARGET_PAGE_MASK;
|
|
|
|
b = p->code_bitmap[offset >> 3] >> (offset & 7);
|
|
|
|
if (b & ((1 << len) - 1))
|
|
|
|
goto do_invalidate;
|
|
|
|
} else {
|
|
|
|
do_invalidate:
|
2004-04-25 19:57:43 +02:00
|
|
|
tb_invalidate_phys_page_range(start, start + len, 1);
|
2004-01-04 19:06:42 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#if !defined(CONFIG_SOFTMMU)
|
2008-04-27 23:12:55 +02:00
|
|
|
static void tb_invalidate_phys_page(target_phys_addr_t addr,
|
2004-04-25 19:57:43 +02:00
|
|
|
unsigned long pc, void *puc)
|
2004-01-04 19:06:42 +01:00
|
|
|
{
|
2008-11-18 20:46:41 +01:00
|
|
|
TranslationBlock *tb;
|
2004-01-04 19:06:42 +01:00
|
|
|
PageDesc *p;
|
2008-11-18 20:46:41 +01:00
|
|
|
int n;
|
2004-04-25 19:57:43 +02:00
|
|
|
#ifdef TARGET_HAS_PRECISE_SMC
|
2008-11-18 20:46:41 +01:00
|
|
|
TranslationBlock *current_tb = NULL;
|
2004-04-25 19:57:43 +02:00
|
|
|
CPUState *env = cpu_single_env;
|
2008-11-18 20:46:41 +01:00
|
|
|
int current_tb_modified = 0;
|
|
|
|
target_ulong current_pc = 0;
|
|
|
|
target_ulong current_cs_base = 0;
|
|
|
|
int current_flags = 0;
|
2004-04-25 19:57:43 +02:00
|
|
|
#endif
|
2004-01-04 19:06:42 +01:00
|
|
|
|
|
|
|
addr &= TARGET_PAGE_MASK;
|
|
|
|
p = page_find(addr >> TARGET_PAGE_BITS);
|
2007-09-16 23:08:06 +02:00
|
|
|
if (!p)
|
2004-01-04 19:06:42 +01:00
|
|
|
return;
|
|
|
|
tb = p->first_tb;
|
2004-04-25 19:57:43 +02:00
|
|
|
#ifdef TARGET_HAS_PRECISE_SMC
|
|
|
|
if (tb && pc != 0) {
|
|
|
|
current_tb = tb_find_pc(pc);
|
|
|
|
}
|
|
|
|
#endif
|
2004-01-04 19:06:42 +01:00
|
|
|
while (tb != NULL) {
|
|
|
|
n = (long)tb & 3;
|
|
|
|
tb = (TranslationBlock *)((long)tb & ~3);
|
2004-04-25 19:57:43 +02:00
|
|
|
#ifdef TARGET_HAS_PRECISE_SMC
|
|
|
|
if (current_tb == tb &&
|
2008-06-29 03:03:05 +02:00
|
|
|
(current_tb->cflags & CF_COUNT_MASK) != 1) {
|
2004-04-25 19:57:43 +02:00
|
|
|
/* If we are modifying the current TB, we must stop
|
|
|
|
its execution. We could be more precise by checking
|
|
|
|
that the modification is after the current PC, but it
|
|
|
|
would require a specialized function to partially
|
|
|
|
restore the CPU state */
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2004-04-25 19:57:43 +02:00
|
|
|
current_tb_modified = 1;
|
|
|
|
cpu_restore_state(current_tb, env, pc, puc);
|
2008-11-18 20:46:41 +01:00
|
|
|
cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base,
|
|
|
|
¤t_flags);
|
2004-04-25 19:57:43 +02:00
|
|
|
}
|
|
|
|
#endif /* TARGET_HAS_PRECISE_SMC */
|
2004-01-04 19:06:42 +01:00
|
|
|
tb_phys_invalidate(tb, addr);
|
|
|
|
tb = tb->page_next[n];
|
|
|
|
}
|
2003-05-14 21:00:11 +02:00
|
|
|
p->first_tb = NULL;
|
2004-04-25 19:57:43 +02:00
|
|
|
#ifdef TARGET_HAS_PRECISE_SMC
|
|
|
|
if (current_tb_modified) {
|
|
|
|
/* we generate a block containing just the instruction
|
|
|
|
modifying the memory. It will ensure that it cannot modify
|
|
|
|
itself */
|
2004-06-14 20:56:36 +02:00
|
|
|
env->current_tb = NULL;
|
2008-06-29 03:03:05 +02:00
|
|
|
tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
|
2004-04-25 19:57:43 +02:00
|
|
|
cpu_resume_from_signal(env, puc);
|
|
|
|
}
|
|
|
|
#endif
|
2003-05-14 21:00:11 +02:00
|
|
|
}
|
2004-01-04 19:06:42 +01:00
|
|
|
#endif
|
2003-05-14 21:00:11 +02:00
|
|
|
|
|
|
|
/* add the tb in the target page and protect it if necessary */
|
2007-09-16 23:08:06 +02:00
|
|
|
static inline void tb_alloc_page(TranslationBlock *tb,
|
2006-03-25 20:31:22 +01:00
|
|
|
unsigned int n, target_ulong page_addr)
|
2003-05-14 21:00:11 +02:00
|
|
|
{
|
|
|
|
PageDesc *p;
|
2004-01-04 19:06:42 +01:00
|
|
|
TranslationBlock *last_first_tb;
|
|
|
|
|
|
|
|
tb->page_addr[n] = page_addr;
|
2005-08-21 11:26:42 +02:00
|
|
|
p = page_find_alloc(page_addr >> TARGET_PAGE_BITS);
|
2004-01-04 19:06:42 +01:00
|
|
|
tb->page_next[n] = p->first_tb;
|
|
|
|
last_first_tb = p->first_tb;
|
|
|
|
p->first_tb = (TranslationBlock *)((long)tb | n);
|
|
|
|
invalidate_page_bitmap(p);
|
2003-05-14 21:00:11 +02:00
|
|
|
|
2004-06-22 20:48:46 +02:00
|
|
|
#if defined(TARGET_HAS_SMC) || 1
|
2004-04-25 19:57:43 +02:00
|
|
|
|
2004-01-04 19:06:42 +01:00
|
|
|
#if defined(CONFIG_USER_ONLY)
|
2003-05-14 21:00:11 +02:00
|
|
|
if (p->flags & PAGE_WRITE) {
|
2006-03-25 20:31:22 +01:00
|
|
|
target_ulong addr;
|
|
|
|
PageDesc *p2;
|
2004-01-04 19:06:42 +01:00
|
|
|
int prot;
|
|
|
|
|
2003-05-14 21:00:11 +02:00
|
|
|
/* force the host page as non writable (writes will have a
|
|
|
|
page fault + mprotect overhead) */
|
2006-03-25 20:31:22 +01:00
|
|
|
page_addr &= qemu_host_page_mask;
|
2003-05-14 21:00:11 +02:00
|
|
|
prot = 0;
|
2006-03-25 20:31:22 +01:00
|
|
|
for(addr = page_addr; addr < page_addr + qemu_host_page_size;
|
|
|
|
addr += TARGET_PAGE_SIZE) {
|
|
|
|
|
|
|
|
p2 = page_find (addr >> TARGET_PAGE_BITS);
|
|
|
|
if (!p2)
|
|
|
|
continue;
|
|
|
|
prot |= p2->flags;
|
|
|
|
p2->flags &= ~PAGE_WRITE;
|
|
|
|
page_get_flags(addr);
|
|
|
|
}
|
2007-09-16 23:08:06 +02:00
|
|
|
mprotect(g2h(page_addr), qemu_host_page_size,
|
2003-05-14 21:00:11 +02:00
|
|
|
(prot & PAGE_BITS) & ~PAGE_WRITE);
|
|
|
|
#ifdef DEBUG_TB_INVALIDATE
|
2007-11-04 08:31:40 +01:00
|
|
|
printf("protecting code page: 0x" TARGET_FMT_lx "\n",
|
2006-03-25 20:31:22 +01:00
|
|
|
page_addr);
|
2003-05-14 21:00:11 +02:00
|
|
|
#endif
|
|
|
|
}
|
2004-01-04 19:06:42 +01:00
|
|
|
#else
|
|
|
|
/* if some code is already present, then the pages are already
|
|
|
|
protected. So we handle the case where only the first TB is
|
|
|
|
allocated in a physical page */
|
|
|
|
if (!last_first_tb) {
|
2005-11-22 00:25:50 +01:00
|
|
|
tlb_protect_code(page_addr);
|
2004-01-04 19:06:42 +01:00
|
|
|
}
|
|
|
|
#endif
|
2004-04-25 19:57:43 +02:00
|
|
|
|
|
|
|
#endif /* TARGET_HAS_SMC */
|
2003-05-14 21:00:11 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Allocate a new translation block. Flush the translation buffer if
|
|
|
|
too many translation blocks or too much generated code. */
|
2005-01-04 00:35:10 +01:00
|
|
|
TranslationBlock *tb_alloc(target_ulong pc)
|
2003-05-14 21:00:11 +02:00
|
|
|
{
|
|
|
|
TranslationBlock *tb;
|
|
|
|
|
2008-05-28 14:30:31 +02:00
|
|
|
if (nb_tbs >= code_gen_max_blocks ||
|
|
|
|
(code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size)
|
2003-05-25 18:46:15 +02:00
|
|
|
return NULL;
|
2003-05-14 21:00:11 +02:00
|
|
|
tb = &tbs[nb_tbs++];
|
|
|
|
tb->pc = pc;
|
2004-02-26 00:24:04 +01:00
|
|
|
tb->cflags = 0;
|
2003-05-25 18:46:15 +02:00
|
|
|
return tb;
|
|
|
|
}
|
|
|
|
|
2008-06-29 03:03:05 +02:00
|
|
|
void tb_free(TranslationBlock *tb)
|
|
|
|
{
|
2008-06-30 19:22:19 +02:00
|
|
|
/* In practice this is mostly used for single use temporary TB
|
2008-06-29 03:03:05 +02:00
|
|
|
Ignore the hard cases and just back up if this TB happens to
|
|
|
|
be the last one generated. */
|
|
|
|
if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) {
|
|
|
|
code_gen_ptr = tb->tc_ptr;
|
|
|
|
nb_tbs--;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2004-01-04 19:06:42 +01:00
|
|
|
/* add a new TB and link it to the physical page tables. phys_page2 is
|
|
|
|
(-1) to indicate that only one page contains the TB. */
|
2007-09-16 23:08:06 +02:00
|
|
|
void tb_link_phys(TranslationBlock *tb,
|
2004-01-04 19:06:42 +01:00
|
|
|
target_ulong phys_pc, target_ulong phys_page2)
|
2003-05-25 18:46:15 +02:00
|
|
|
{
|
2004-01-04 19:06:42 +01:00
|
|
|
unsigned int h;
|
|
|
|
TranslationBlock **ptb;
|
|
|
|
|
2008-06-02 18:16:42 +02:00
|
|
|
/* Grab the mmap lock to stop another thread invalidating this TB
|
|
|
|
before we are done. */
|
|
|
|
mmap_lock();
|
2004-01-04 19:06:42 +01:00
|
|
|
/* add in the physical hash table */
|
|
|
|
h = tb_phys_hash_func(phys_pc);
|
|
|
|
ptb = &tb_phys_hash[h];
|
|
|
|
tb->phys_hash_next = *ptb;
|
|
|
|
*ptb = tb;
|
2003-05-14 21:00:11 +02:00
|
|
|
|
|
|
|
/* add in the page list */
|
2004-01-04 19:06:42 +01:00
|
|
|
tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK);
|
|
|
|
if (phys_page2 != -1)
|
|
|
|
tb_alloc_page(tb, 1, phys_page2);
|
|
|
|
else
|
|
|
|
tb->page_addr[1] = -1;
|
|
|
|
|
2003-05-25 18:46:15 +02:00
|
|
|
tb->jmp_first = (TranslationBlock *)((long)tb | 2);
|
|
|
|
tb->jmp_next[0] = NULL;
|
|
|
|
tb->jmp_next[1] = NULL;
|
|
|
|
|
|
|
|
/* init original jump addresses */
|
|
|
|
if (tb->tb_next_offset[0] != 0xffff)
|
|
|
|
tb_reset_jump(tb, 0);
|
|
|
|
if (tb->tb_next_offset[1] != 0xffff)
|
|
|
|
tb_reset_jump(tb, 1);
|
2005-11-20 11:35:40 +01:00
|
|
|
|
|
|
|
#ifdef DEBUG_TB_CHECK
|
|
|
|
tb_page_check();
|
|
|
|
#endif
|
2008-06-02 18:16:42 +02:00
|
|
|
mmap_unlock();
|
2003-05-14 21:00:11 +02:00
|
|
|
}
|
|
|
|
|
2004-01-04 19:06:42 +01:00
|
|
|
/* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr <
|
|
|
|
tb[1].tc_ptr. Return NULL if not found */
|
|
|
|
TranslationBlock *tb_find_pc(unsigned long tc_ptr)
|
2003-05-14 21:00:11 +02:00
|
|
|
{
|
2004-01-04 19:06:42 +01:00
|
|
|
int m_min, m_max, m;
|
|
|
|
unsigned long v;
|
|
|
|
TranslationBlock *tb;
|
2003-05-28 01:29:48 +02:00
|
|
|
|
|
|
|
if (nb_tbs <= 0)
|
|
|
|
return NULL;
|
|
|
|
if (tc_ptr < (unsigned long)code_gen_buffer ||
|
|
|
|
tc_ptr >= (unsigned long)code_gen_ptr)
|
|
|
|
return NULL;
|
|
|
|
/* binary search (cf Knuth) */
|
|
|
|
m_min = 0;
|
|
|
|
m_max = nb_tbs - 1;
|
|
|
|
while (m_min <= m_max) {
|
|
|
|
m = (m_min + m_max) >> 1;
|
|
|
|
tb = &tbs[m];
|
|
|
|
v = (unsigned long)tb->tc_ptr;
|
|
|
|
if (v == tc_ptr)
|
|
|
|
return tb;
|
|
|
|
else if (tc_ptr < v) {
|
|
|
|
m_max = m - 1;
|
|
|
|
} else {
|
|
|
|
m_min = m + 1;
|
|
|
|
}
|
2007-09-16 23:08:06 +02:00
|
|
|
}
|
2003-05-28 01:29:48 +02:00
|
|
|
return &tbs[m_max];
|
|
|
|
}
|
2003-06-21 15:11:07 +02:00
|
|
|
|
2003-06-25 18:16:50 +02:00
|
|
|
static void tb_reset_jump_recursive(TranslationBlock *tb);
|
|
|
|
|
|
|
|
static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n)
|
|
|
|
{
|
|
|
|
TranslationBlock *tb1, *tb_next, **ptb;
|
|
|
|
unsigned int n1;
|
|
|
|
|
|
|
|
tb1 = tb->jmp_next[n];
|
|
|
|
if (tb1 != NULL) {
|
|
|
|
/* find head of list */
|
|
|
|
for(;;) {
|
|
|
|
n1 = (long)tb1 & 3;
|
|
|
|
tb1 = (TranslationBlock *)((long)tb1 & ~3);
|
|
|
|
if (n1 == 2)
|
|
|
|
break;
|
|
|
|
tb1 = tb1->jmp_next[n1];
|
|
|
|
}
|
|
|
|
/* we are now sure now that tb jumps to tb1 */
|
|
|
|
tb_next = tb1;
|
|
|
|
|
|
|
|
/* remove tb from the jmp_first list */
|
|
|
|
ptb = &tb_next->jmp_first;
|
|
|
|
for(;;) {
|
|
|
|
tb1 = *ptb;
|
|
|
|
n1 = (long)tb1 & 3;
|
|
|
|
tb1 = (TranslationBlock *)((long)tb1 & ~3);
|
|
|
|
if (n1 == n && tb1 == tb)
|
|
|
|
break;
|
|
|
|
ptb = &tb1->jmp_next[n1];
|
|
|
|
}
|
|
|
|
*ptb = tb->jmp_next[n];
|
|
|
|
tb->jmp_next[n] = NULL;
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2003-06-25 18:16:50 +02:00
|
|
|
/* suppress the jump to next tb in generated code */
|
|
|
|
tb_reset_jump(tb, n);
|
|
|
|
|
2004-01-04 16:48:17 +01:00
|
|
|
/* suppress jumps in the tb on which we could have jumped */
|
2003-06-25 18:16:50 +02:00
|
|
|
tb_reset_jump_recursive(tb_next);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tb_reset_jump_recursive(TranslationBlock *tb)
|
|
|
|
{
|
|
|
|
tb_reset_jump_recursive2(tb, 0);
|
|
|
|
tb_reset_jump_recursive2(tb, 1);
|
|
|
|
}
|
|
|
|
|
2005-04-17 21:16:13 +02:00
|
|
|
#if defined(TARGET_HAS_ICE)
|
2004-04-25 19:57:43 +02:00
|
|
|
static void breakpoint_invalidate(CPUState *env, target_ulong pc)
|
|
|
|
{
|
2007-04-07 13:21:28 +02:00
|
|
|
target_phys_addr_t addr;
|
|
|
|
target_ulong pd;
|
2006-04-08 19:14:56 +02:00
|
|
|
ram_addr_t ram_addr;
|
|
|
|
PhysPageDesc *p;
|
2004-04-25 19:57:43 +02:00
|
|
|
|
2006-04-08 19:14:56 +02:00
|
|
|
addr = cpu_get_phys_page_debug(env, pc);
|
|
|
|
p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
|
|
|
if (!p) {
|
|
|
|
pd = IO_MEM_UNASSIGNED;
|
|
|
|
} else {
|
|
|
|
pd = p->phys_offset;
|
|
|
|
}
|
|
|
|
ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK);
|
2006-04-08 19:36:21 +02:00
|
|
|
tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
|
2004-04-25 19:57:43 +02:00
|
|
|
}
|
2005-01-04 00:35:10 +01:00
|
|
|
#endif
|
2004-04-25 19:57:43 +02:00
|
|
|
|
2007-03-17 00:58:11 +01:00
|
|
|
/* Add a watchpoint. */
|
2008-11-18 21:07:32 +01:00
|
|
|
int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
|
|
|
|
int flags, CPUWatchpoint **watchpoint)
|
2007-03-17 00:58:11 +01:00
|
|
|
{
|
2008-11-18 21:14:20 +01:00
|
|
|
target_ulong len_mask = ~(len - 1);
|
2008-11-18 21:56:59 +01:00
|
|
|
CPUWatchpoint *wp, *prev_wp;
|
2007-03-17 00:58:11 +01:00
|
|
|
|
2008-11-18 21:14:20 +01:00
|
|
|
/* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */
|
|
|
|
if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) {
|
|
|
|
fprintf(stderr, "qemu: tried to set invalid watchpoint at "
|
|
|
|
TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2008-11-18 21:07:32 +01:00
|
|
|
wp = qemu_malloc(sizeof(*wp));
|
|
|
|
if (!wp)
|
2008-11-18 22:52:54 +01:00
|
|
|
return -ENOMEM;
|
2008-11-18 21:07:32 +01:00
|
|
|
|
|
|
|
wp->vaddr = addr;
|
2008-11-18 21:14:20 +01:00
|
|
|
wp->len_mask = len_mask;
|
2008-11-18 21:07:32 +01:00
|
|
|
wp->flags = flags;
|
|
|
|
|
2008-11-18 21:56:59 +01:00
|
|
|
/* keep all GDB-injected watchpoints in front */
|
|
|
|
if (!(flags & BP_GDB) && env->watchpoints) {
|
|
|
|
prev_wp = env->watchpoints;
|
|
|
|
while (prev_wp->next != NULL && (prev_wp->next->flags & BP_GDB))
|
|
|
|
prev_wp = prev_wp->next;
|
|
|
|
} else {
|
|
|
|
prev_wp = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Insert new watchpoint */
|
|
|
|
if (prev_wp) {
|
|
|
|
wp->next = prev_wp->next;
|
|
|
|
prev_wp->next = wp;
|
|
|
|
} else {
|
|
|
|
wp->next = env->watchpoints;
|
|
|
|
env->watchpoints = wp;
|
|
|
|
}
|
2008-11-18 21:07:32 +01:00
|
|
|
if (wp->next)
|
|
|
|
wp->next->prev = wp;
|
2008-11-18 21:56:59 +01:00
|
|
|
wp->prev = prev_wp;
|
2007-03-17 00:58:11 +01:00
|
|
|
|
|
|
|
tlb_flush_page(env, addr);
|
2008-11-18 21:07:32 +01:00
|
|
|
|
|
|
|
if (watchpoint)
|
|
|
|
*watchpoint = wp;
|
|
|
|
return 0;
|
2007-03-17 00:58:11 +01:00
|
|
|
}
|
|
|
|
|
2008-11-18 21:07:32 +01:00
|
|
|
/* Remove a specific watchpoint. */
|
|
|
|
int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len,
|
|
|
|
int flags)
|
2007-03-17 00:58:11 +01:00
|
|
|
{
|
2008-11-18 21:14:20 +01:00
|
|
|
target_ulong len_mask = ~(len - 1);
|
2008-11-18 21:07:32 +01:00
|
|
|
CPUWatchpoint *wp;
|
2007-03-17 00:58:11 +01:00
|
|
|
|
2008-11-18 21:07:32 +01:00
|
|
|
for (wp = env->watchpoints; wp != NULL; wp = wp->next) {
|
2008-11-18 21:14:20 +01:00
|
|
|
if (addr == wp->vaddr && len_mask == wp->len_mask
|
2008-11-18 21:37:55 +01:00
|
|
|
&& flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
|
2008-11-18 21:07:32 +01:00
|
|
|
cpu_watchpoint_remove_by_ref(env, wp);
|
2007-03-17 00:58:11 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
2008-11-18 21:07:32 +01:00
|
|
|
return -ENOENT;
|
2007-03-17 00:58:11 +01:00
|
|
|
}
|
|
|
|
|
2008-11-18 21:07:32 +01:00
|
|
|
/* Remove a specific watchpoint by reference. */
|
|
|
|
void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint)
|
|
|
|
{
|
|
|
|
if (watchpoint->next)
|
|
|
|
watchpoint->next->prev = watchpoint->prev;
|
|
|
|
if (watchpoint->prev)
|
|
|
|
watchpoint->prev->next = watchpoint->next;
|
|
|
|
else
|
|
|
|
env->watchpoints = watchpoint->next;
|
2008-05-17 20:58:29 +02:00
|
|
|
|
2008-11-18 21:07:32 +01:00
|
|
|
tlb_flush_page(env, watchpoint->vaddr);
|
|
|
|
|
|
|
|
qemu_free(watchpoint);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Remove all matching watchpoints. */
|
|
|
|
void cpu_watchpoint_remove_all(CPUState *env, int mask)
|
|
|
|
{
|
|
|
|
CPUWatchpoint *wp;
|
|
|
|
|
|
|
|
for (wp = env->watchpoints; wp != NULL; wp = wp->next)
|
|
|
|
if (wp->flags & mask)
|
|
|
|
cpu_watchpoint_remove_by_ref(env, wp);
|
2008-05-17 20:58:29 +02:00
|
|
|
}
|
|
|
|
|
2008-11-18 21:07:32 +01:00
|
|
|
/* Add a breakpoint. */
|
|
|
|
int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
|
|
|
|
CPUBreakpoint **breakpoint)
|
2003-07-26 14:06:08 +02:00
|
|
|
{
|
2005-04-17 21:16:13 +02:00
|
|
|
#if defined(TARGET_HAS_ICE)
|
2008-11-18 21:56:59 +01:00
|
|
|
CPUBreakpoint *bp, *prev_bp;
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2008-11-18 21:07:32 +01:00
|
|
|
bp = qemu_malloc(sizeof(*bp));
|
|
|
|
if (!bp)
|
2008-11-18 22:52:54 +01:00
|
|
|
return -ENOMEM;
|
2003-07-26 14:06:08 +02:00
|
|
|
|
2008-11-18 21:07:32 +01:00
|
|
|
bp->pc = pc;
|
|
|
|
bp->flags = flags;
|
|
|
|
|
2008-11-18 21:56:59 +01:00
|
|
|
/* keep all GDB-injected breakpoints in front */
|
|
|
|
if (!(flags & BP_GDB) && env->breakpoints) {
|
|
|
|
prev_bp = env->breakpoints;
|
|
|
|
while (prev_bp->next != NULL && (prev_bp->next->flags & BP_GDB))
|
|
|
|
prev_bp = prev_bp->next;
|
|
|
|
} else {
|
|
|
|
prev_bp = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Insert new breakpoint */
|
|
|
|
if (prev_bp) {
|
|
|
|
bp->next = prev_bp->next;
|
|
|
|
prev_bp->next = bp;
|
|
|
|
} else {
|
|
|
|
bp->next = env->breakpoints;
|
|
|
|
env->breakpoints = bp;
|
|
|
|
}
|
2008-11-18 21:07:32 +01:00
|
|
|
if (bp->next)
|
|
|
|
bp->next->prev = bp;
|
2008-11-18 21:56:59 +01:00
|
|
|
bp->prev = prev_bp;
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2004-04-25 19:57:43 +02:00
|
|
|
breakpoint_invalidate(env, pc);
|
2008-11-18 21:07:32 +01:00
|
|
|
|
|
|
|
if (breakpoint)
|
|
|
|
*breakpoint = bp;
|
2003-07-26 14:06:08 +02:00
|
|
|
return 0;
|
|
|
|
#else
|
2008-11-18 21:07:32 +01:00
|
|
|
return -ENOSYS;
|
2003-07-26 14:06:08 +02:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2008-11-18 21:07:32 +01:00
|
|
|
/* Remove a specific breakpoint. */
|
|
|
|
int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags)
|
|
|
|
{
|
2008-05-17 20:58:29 +02:00
|
|
|
#if defined(TARGET_HAS_ICE)
|
2008-11-18 21:07:32 +01:00
|
|
|
CPUBreakpoint *bp;
|
|
|
|
|
|
|
|
for (bp = env->breakpoints; bp != NULL; bp = bp->next) {
|
|
|
|
if (bp->pc == pc && bp->flags == flags) {
|
|
|
|
cpu_breakpoint_remove_by_ref(env, bp);
|
|
|
|
return 0;
|
|
|
|
}
|
2008-05-17 20:58:29 +02:00
|
|
|
}
|
2008-11-18 21:07:32 +01:00
|
|
|
return -ENOENT;
|
|
|
|
#else
|
|
|
|
return -ENOSYS;
|
2008-05-17 20:58:29 +02:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2008-11-18 21:07:32 +01:00
|
|
|
/* Remove a specific breakpoint by reference. */
|
|
|
|
void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint)
|
2003-07-26 14:06:08 +02:00
|
|
|
{
|
2005-04-17 21:16:13 +02:00
|
|
|
#if defined(TARGET_HAS_ICE)
|
2008-11-18 21:07:32 +01:00
|
|
|
if (breakpoint->next)
|
|
|
|
breakpoint->next->prev = breakpoint->prev;
|
|
|
|
if (breakpoint->prev)
|
|
|
|
breakpoint->prev->next = breakpoint->next;
|
|
|
|
else
|
|
|
|
env->breakpoints = breakpoint->next;
|
2004-04-25 19:57:43 +02:00
|
|
|
|
2008-11-18 21:07:32 +01:00
|
|
|
breakpoint_invalidate(env, breakpoint->pc);
|
|
|
|
|
|
|
|
qemu_free(breakpoint);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Remove all matching breakpoints. */
|
|
|
|
void cpu_breakpoint_remove_all(CPUState *env, int mask)
|
|
|
|
{
|
|
|
|
#if defined(TARGET_HAS_ICE)
|
|
|
|
CPUBreakpoint *bp;
|
|
|
|
|
|
|
|
for (bp = env->breakpoints; bp != NULL; bp = bp->next)
|
|
|
|
if (bp->flags & mask)
|
|
|
|
cpu_breakpoint_remove_by_ref(env, bp);
|
2003-07-26 14:06:08 +02:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2003-07-29 22:50:33 +02:00
|
|
|
/* enable or disable single step mode. EXCP_DEBUG is returned by the
|
|
|
|
CPU loop after each instruction */
|
|
|
|
void cpu_single_step(CPUState *env, int enabled)
|
|
|
|
{
|
2005-04-17 21:16:13 +02:00
|
|
|
#if defined(TARGET_HAS_ICE)
|
2003-07-29 22:50:33 +02:00
|
|
|
if (env->singlestep_enabled != enabled) {
|
|
|
|
env->singlestep_enabled = enabled;
|
|
|
|
/* must flush all the translated code to avoid inconsistancies */
|
2004-01-04 19:06:42 +01:00
|
|
|
/* XXX: only flush what is necessary */
|
2004-01-04 16:48:17 +01:00
|
|
|
tb_flush(env);
|
2003-07-29 22:50:33 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2003-10-05 16:28:56 +02:00
|
|
|
/* enable or disable low levels log */
|
|
|
|
void cpu_set_log(int log_flags)
|
|
|
|
{
|
|
|
|
loglevel = log_flags;
|
|
|
|
if (loglevel && !logfile) {
|
2007-07-01 20:21:11 +02:00
|
|
|
logfile = fopen(logfilename, log_append ? "a" : "w");
|
2003-10-05 16:28:56 +02:00
|
|
|
if (!logfile) {
|
|
|
|
perror(logfilename);
|
|
|
|
_exit(1);
|
|
|
|
}
|
2004-01-04 19:06:42 +01:00
|
|
|
#if !defined(CONFIG_SOFTMMU)
|
|
|
|
/* must avoid mmap() usage of glibc by setting a buffer "by hand" */
|
|
|
|
{
|
2008-09-20 10:07:15 +02:00
|
|
|
static char logfile_buf[4096];
|
2004-01-04 19:06:42 +01:00
|
|
|
setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf));
|
|
|
|
}
|
|
|
|
#else
|
2003-10-05 16:28:56 +02:00
|
|
|
setvbuf(logfile, NULL, _IOLBF, 0);
|
2004-01-04 19:06:42 +01:00
|
|
|
#endif
|
2007-06-30 15:53:24 +02:00
|
|
|
log_append = 1;
|
|
|
|
}
|
|
|
|
if (!loglevel && logfile) {
|
|
|
|
fclose(logfile);
|
|
|
|
logfile = NULL;
|
2003-10-05 16:28:56 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_set_log_filename(const char *filename)
|
|
|
|
{
|
|
|
|
logfilename = strdup(filename);
|
2007-06-30 15:53:24 +02:00
|
|
|
if (logfile) {
|
|
|
|
fclose(logfile);
|
|
|
|
logfile = NULL;
|
|
|
|
}
|
|
|
|
cpu_set_log(loglevel);
|
2003-10-05 16:28:56 +02:00
|
|
|
}
|
2003-07-29 22:50:33 +02:00
|
|
|
|
2004-01-04 16:48:17 +01:00
|
|
|
/* mask must never be zero, except for A20 change call */
|
2003-06-30 15:12:32 +02:00
|
|
|
void cpu_interrupt(CPUState *env, int mask)
|
2003-06-25 18:16:50 +02:00
|
|
|
{
|
2008-06-07 22:50:51 +02:00
|
|
|
#if !defined(USE_NPTL)
|
2003-06-25 18:16:50 +02:00
|
|
|
TranslationBlock *tb;
|
2008-03-28 23:29:15 +01:00
|
|
|
static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED;
|
2008-06-07 22:50:51 +02:00
|
|
|
#endif
|
2008-06-29 03:03:05 +02:00
|
|
|
int old_mask;
|
2004-02-16 23:01:13 +01:00
|
|
|
|
2008-06-29 03:03:05 +02:00
|
|
|
old_mask = env->interrupt_request;
|
2008-06-07 22:50:51 +02:00
|
|
|
/* FIXME: This is probably not threadsafe. A different thread could
|
2008-06-30 19:22:19 +02:00
|
|
|
be in the middle of a read-modify-write operation. */
|
2003-06-30 15:12:32 +02:00
|
|
|
env->interrupt_request |= mask;
|
2008-06-07 22:50:51 +02:00
|
|
|
#if defined(USE_NPTL)
|
|
|
|
/* FIXME: TB unchaining isn't SMP safe. For now just ignore the
|
|
|
|
problem and hope the cpu will stop of its own accord. For userspace
|
|
|
|
emulation this often isn't actually as bad as it sounds. Often
|
|
|
|
signals are used primarily to interrupt blocking syscalls. */
|
|
|
|
#else
|
2008-06-29 03:03:05 +02:00
|
|
|
if (use_icount) {
|
2008-07-09 17:31:50 +02:00
|
|
|
env->icount_decr.u16.high = 0xffff;
|
2008-06-29 03:03:05 +02:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
/* CPU_INTERRUPT_EXIT isn't a real interrupt. It just means
|
|
|
|
an async event happened and we need to process it. */
|
|
|
|
if (!can_do_io(env)
|
|
|
|
&& (mask & ~(old_mask | CPU_INTERRUPT_EXIT)) != 0) {
|
|
|
|
cpu_abort(env, "Raised interrupt while not in I/O function");
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
} else {
|
|
|
|
tb = env->current_tb;
|
|
|
|
/* if the cpu is currently executing code, we must unlink it and
|
|
|
|
all the potentially executing TB */
|
|
|
|
if (tb && !testandset(&interrupt_lock)) {
|
|
|
|
env->current_tb = NULL;
|
|
|
|
tb_reset_jump_recursive(tb);
|
|
|
|
resetlock(&interrupt_lock);
|
|
|
|
}
|
2003-06-25 18:16:50 +02:00
|
|
|
}
|
2008-06-07 22:50:51 +02:00
|
|
|
#endif
|
2003-06-25 18:16:50 +02:00
|
|
|
}
|
|
|
|
|
2004-05-20 15:42:52 +02:00
|
|
|
void cpu_reset_interrupt(CPUState *env, int mask)
|
|
|
|
{
|
|
|
|
env->interrupt_request &= ~mask;
|
|
|
|
}
|
|
|
|
|
2008-10-02 20:27:46 +02:00
|
|
|
const CPULogItem cpu_log_items[] = {
|
2007-09-16 23:08:06 +02:00
|
|
|
{ CPU_LOG_TB_OUT_ASM, "out_asm",
|
2004-03-21 18:06:25 +01:00
|
|
|
"show generated host assembly code for each compiled TB" },
|
|
|
|
{ CPU_LOG_TB_IN_ASM, "in_asm",
|
|
|
|
"show target assembly code for each compiled TB" },
|
2007-09-16 23:08:06 +02:00
|
|
|
{ CPU_LOG_TB_OP, "op",
|
2008-02-01 11:50:11 +01:00
|
|
|
"show micro ops for each compiled TB" },
|
2004-03-21 18:06:25 +01:00
|
|
|
{ CPU_LOG_TB_OP_OPT, "op_opt",
|
2008-03-14 18:37:11 +01:00
|
|
|
"show micro ops "
|
|
|
|
#ifdef TARGET_I386
|
|
|
|
"before eflags optimization and "
|
2004-03-21 18:06:25 +01:00
|
|
|
#endif
|
2008-03-14 18:37:11 +01:00
|
|
|
"after liveness analysis" },
|
2004-03-21 18:06:25 +01:00
|
|
|
{ CPU_LOG_INT, "int",
|
|
|
|
"show interrupts/exceptions in short format" },
|
|
|
|
{ CPU_LOG_EXEC, "exec",
|
|
|
|
"show trace before each executed TB (lots of logs)" },
|
2004-05-21 14:59:32 +02:00
|
|
|
{ CPU_LOG_TB_CPU, "cpu",
|
2007-06-03 15:35:16 +02:00
|
|
|
"show CPU state before block translation" },
|
2004-03-21 18:06:25 +01:00
|
|
|
#ifdef TARGET_I386
|
|
|
|
{ CPU_LOG_PCALL, "pcall",
|
|
|
|
"show protected mode far calls/returns/exceptions" },
|
|
|
|
#endif
|
2004-10-09 19:32:58 +02:00
|
|
|
#ifdef DEBUG_IOPORT
|
2004-05-12 21:11:15 +02:00
|
|
|
{ CPU_LOG_IOPORT, "ioport",
|
|
|
|
"show all i/o ports accesses" },
|
2004-10-09 19:32:58 +02:00
|
|
|
#endif
|
2004-03-21 18:06:25 +01:00
|
|
|
{ 0, NULL, NULL },
|
|
|
|
};
|
|
|
|
|
|
|
|
static int cmp1(const char *s1, int n, const char *s2)
|
|
|
|
{
|
|
|
|
if (strlen(s2) != n)
|
|
|
|
return 0;
|
|
|
|
return memcmp(s1, s2, n) == 0;
|
|
|
|
}
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2004-03-21 18:06:25 +01:00
|
|
|
/* takes a comma separated list of log masks. Return 0 if error. */
|
|
|
|
int cpu_str_to_log_mask(const char *str)
|
|
|
|
{
|
2008-10-02 20:27:46 +02:00
|
|
|
const CPULogItem *item;
|
2004-03-21 18:06:25 +01:00
|
|
|
int mask;
|
|
|
|
const char *p, *p1;
|
|
|
|
|
|
|
|
p = str;
|
|
|
|
mask = 0;
|
|
|
|
for(;;) {
|
|
|
|
p1 = strchr(p, ',');
|
|
|
|
if (!p1)
|
|
|
|
p1 = p + strlen(p);
|
2004-10-09 19:32:58 +02:00
|
|
|
if(cmp1(p,p1-p,"all")) {
|
|
|
|
for(item = cpu_log_items; item->mask != 0; item++) {
|
|
|
|
mask |= item->mask;
|
|
|
|
}
|
|
|
|
} else {
|
2004-03-21 18:06:25 +01:00
|
|
|
for(item = cpu_log_items; item->mask != 0; item++) {
|
|
|
|
if (cmp1(p, p1 - p, item->name))
|
|
|
|
goto found;
|
|
|
|
}
|
|
|
|
return 0;
|
2004-10-09 19:32:58 +02:00
|
|
|
}
|
2004-03-21 18:06:25 +01:00
|
|
|
found:
|
|
|
|
mask |= item->mask;
|
|
|
|
if (*p1 != ',')
|
|
|
|
break;
|
|
|
|
p = p1 + 1;
|
|
|
|
}
|
|
|
|
return mask;
|
|
|
|
}
|
2003-06-25 18:16:50 +02:00
|
|
|
|
2003-06-21 15:11:07 +02:00
|
|
|
void cpu_abort(CPUState *env, const char *fmt, ...)
|
|
|
|
{
|
|
|
|
va_list ap;
|
2007-11-23 17:53:59 +01:00
|
|
|
va_list ap2;
|
2003-06-21 15:11:07 +02:00
|
|
|
|
|
|
|
va_start(ap, fmt);
|
2007-11-23 17:53:59 +01:00
|
|
|
va_copy(ap2, ap);
|
2003-06-21 15:11:07 +02:00
|
|
|
fprintf(stderr, "qemu: fatal: ");
|
|
|
|
vfprintf(stderr, fmt, ap);
|
|
|
|
fprintf(stderr, "\n");
|
|
|
|
#ifdef TARGET_I386
|
2004-10-09 20:08:01 +02:00
|
|
|
cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP);
|
|
|
|
#else
|
|
|
|
cpu_dump_state(env, stderr, fprintf, 0);
|
2003-06-21 15:11:07 +02:00
|
|
|
#endif
|
2007-06-10 16:07:13 +02:00
|
|
|
if (logfile) {
|
2007-09-29 14:18:20 +02:00
|
|
|
fprintf(logfile, "qemu: fatal: ");
|
2007-11-23 17:53:59 +01:00
|
|
|
vfprintf(logfile, fmt, ap2);
|
2007-09-29 14:18:20 +02:00
|
|
|
fprintf(logfile, "\n");
|
|
|
|
#ifdef TARGET_I386
|
|
|
|
cpu_dump_state(env, logfile, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP);
|
|
|
|
#else
|
|
|
|
cpu_dump_state(env, logfile, fprintf, 0);
|
|
|
|
#endif
|
2007-06-10 16:07:13 +02:00
|
|
|
fflush(logfile);
|
|
|
|
fclose(logfile);
|
|
|
|
}
|
2007-11-23 17:53:59 +01:00
|
|
|
va_end(ap2);
|
2007-09-29 14:18:20 +02:00
|
|
|
va_end(ap);
|
2003-06-21 15:11:07 +02:00
|
|
|
abort();
|
|
|
|
}
|
|
|
|
|
2007-02-28 21:20:53 +01:00
|
|
|
CPUState *cpu_copy(CPUState *env)
|
|
|
|
{
|
2007-12-09 03:22:57 +01:00
|
|
|
CPUState *new_env = cpu_init(env->cpu_model_str);
|
2007-02-28 21:20:53 +01:00
|
|
|
/* preserve chaining and index */
|
|
|
|
CPUState *next_cpu = new_env->next_cpu;
|
|
|
|
int cpu_index = new_env->cpu_index;
|
|
|
|
memcpy(new_env, env, sizeof(CPUState));
|
|
|
|
new_env->next_cpu = next_cpu;
|
|
|
|
new_env->cpu_index = cpu_index;
|
|
|
|
return new_env;
|
|
|
|
}
|
|
|
|
|
2004-01-04 16:48:17 +01:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
|
2008-05-06 10:44:21 +02:00
|
|
|
static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
/* Discard jump cache entries for any tb which might potentially
|
|
|
|
overlap the flushed page. */
|
|
|
|
i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE);
|
|
|
|
memset (&env->tb_jmp_cache[i], 0,
|
|
|
|
TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
|
|
|
|
|
|
|
|
i = tb_jmp_cache_hash_page(addr);
|
|
|
|
memset (&env->tb_jmp_cache[i], 0,
|
|
|
|
TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
|
|
|
|
}
|
|
|
|
|
2004-02-04 00:35:10 +01:00
|
|
|
/* NOTE: if flush_global is true, also flush global entries (not
|
|
|
|
implemented yet) */
|
|
|
|
void tlb_flush(CPUState *env, int flush_global)
|
2003-08-10 23:47:01 +02:00
|
|
|
{
|
|
|
|
int i;
|
2004-01-04 16:48:17 +01:00
|
|
|
|
2004-01-04 19:06:42 +01:00
|
|
|
#if defined(DEBUG_TLB)
|
|
|
|
printf("tlb_flush:\n");
|
|
|
|
#endif
|
2004-01-04 16:48:17 +01:00
|
|
|
/* must reset current TB so that interrupts cannot modify the
|
|
|
|
links while we are modifying them */
|
|
|
|
env->current_tb = NULL;
|
|
|
|
|
2003-08-10 23:47:01 +02:00
|
|
|
for(i = 0; i < CPU_TLB_SIZE; i++) {
|
2005-11-28 22:19:04 +01:00
|
|
|
env->tlb_table[0][i].addr_read = -1;
|
|
|
|
env->tlb_table[0][i].addr_write = -1;
|
|
|
|
env->tlb_table[0][i].addr_code = -1;
|
|
|
|
env->tlb_table[1][i].addr_read = -1;
|
|
|
|
env->tlb_table[1][i].addr_write = -1;
|
|
|
|
env->tlb_table[1][i].addr_code = -1;
|
2007-04-05 08:43:27 +02:00
|
|
|
#if (NB_MMU_MODES >= 3)
|
|
|
|
env->tlb_table[2][i].addr_read = -1;
|
|
|
|
env->tlb_table[2][i].addr_write = -1;
|
|
|
|
env->tlb_table[2][i].addr_code = -1;
|
|
|
|
#if (NB_MMU_MODES == 4)
|
|
|
|
env->tlb_table[3][i].addr_read = -1;
|
|
|
|
env->tlb_table[3][i].addr_write = -1;
|
|
|
|
env->tlb_table[3][i].addr_code = -1;
|
|
|
|
#endif
|
|
|
|
#endif
|
2003-08-10 23:47:01 +02:00
|
|
|
}
|
2004-01-04 19:06:42 +01:00
|
|
|
|
2005-11-20 11:35:40 +01:00
|
|
|
memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
|
2004-01-04 19:06:42 +01:00
|
|
|
|
2005-02-10 23:00:27 +01:00
|
|
|
#ifdef USE_KQEMU
|
|
|
|
if (env->kqemu_enabled) {
|
|
|
|
kqemu_flush(env, flush_global);
|
|
|
|
}
|
2004-01-04 19:06:42 +01:00
|
|
|
#endif
|
2005-01-26 23:00:47 +01:00
|
|
|
tlb_flush_count++;
|
2003-08-10 23:47:01 +02:00
|
|
|
}
|
|
|
|
|
2004-05-20 23:56:27 +02:00
|
|
|
static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
|
2003-10-27 22:22:23 +01:00
|
|
|
{
|
2007-09-16 23:08:06 +02:00
|
|
|
if (addr == (tlb_entry->addr_read &
|
2005-11-28 22:19:04 +01:00
|
|
|
(TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
|
2007-09-16 23:08:06 +02:00
|
|
|
addr == (tlb_entry->addr_write &
|
2005-11-28 22:19:04 +01:00
|
|
|
(TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
|
2007-09-16 23:08:06 +02:00
|
|
|
addr == (tlb_entry->addr_code &
|
2005-11-28 22:19:04 +01:00
|
|
|
(TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
|
|
|
|
tlb_entry->addr_read = -1;
|
|
|
|
tlb_entry->addr_write = -1;
|
|
|
|
tlb_entry->addr_code = -1;
|
|
|
|
}
|
2003-10-27 22:22:23 +01:00
|
|
|
}
|
|
|
|
|
2004-04-25 23:28:44 +02:00
|
|
|
void tlb_flush_page(CPUState *env, target_ulong addr)
|
2003-08-10 23:47:01 +02:00
|
|
|
{
|
2005-11-20 11:35:40 +01:00
|
|
|
int i;
|
2004-01-04 16:48:17 +01:00
|
|
|
|
2004-01-04 19:06:42 +01:00
|
|
|
#if defined(DEBUG_TLB)
|
2005-07-24 14:55:09 +02:00
|
|
|
printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
|
2004-01-04 19:06:42 +01:00
|
|
|
#endif
|
2004-01-04 16:48:17 +01:00
|
|
|
/* must reset current TB so that interrupts cannot modify the
|
|
|
|
links while we are modifying them */
|
|
|
|
env->current_tb = NULL;
|
2003-10-27 22:22:23 +01:00
|
|
|
|
|
|
|
addr &= TARGET_PAGE_MASK;
|
|
|
|
i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
2005-11-28 22:19:04 +01:00
|
|
|
tlb_flush_entry(&env->tlb_table[0][i], addr);
|
|
|
|
tlb_flush_entry(&env->tlb_table[1][i], addr);
|
2007-04-05 08:43:27 +02:00
|
|
|
#if (NB_MMU_MODES >= 3)
|
|
|
|
tlb_flush_entry(&env->tlb_table[2][i], addr);
|
|
|
|
#if (NB_MMU_MODES == 4)
|
|
|
|
tlb_flush_entry(&env->tlb_table[3][i], addr);
|
|
|
|
#endif
|
|
|
|
#endif
|
2004-01-04 16:48:17 +01:00
|
|
|
|
2008-05-06 10:44:21 +02:00
|
|
|
tlb_flush_jmp_cache(env, addr);
|
2004-01-04 19:06:42 +01:00
|
|
|
|
2005-02-10 23:00:27 +01:00
|
|
|
#ifdef USE_KQEMU
|
|
|
|
if (env->kqemu_enabled) {
|
|
|
|
kqemu_flush_page(env, addr);
|
|
|
|
}
|
|
|
|
#endif
|
2004-01-04 19:06:42 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* update the TLBs so that writes to code in the virtual page 'addr'
|
|
|
|
can be detected */
|
2005-11-22 00:25:50 +01:00
|
|
|
static void tlb_protect_code(ram_addr_t ram_addr)
|
2004-01-04 19:06:42 +01:00
|
|
|
{
|
2007-09-16 23:08:06 +02:00
|
|
|
cpu_physical_memory_reset_dirty(ram_addr,
|
2005-11-22 00:25:50 +01:00
|
|
|
ram_addr + TARGET_PAGE_SIZE,
|
|
|
|
CODE_DIRTY_FLAG);
|
2004-01-04 19:06:42 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* update the TLB so that writes in physical page 'phys_addr' are no longer
|
2005-08-21 11:26:42 +02:00
|
|
|
tested for self modifying code */
|
2007-09-16 23:08:06 +02:00
|
|
|
static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
|
2005-08-21 11:26:42 +02:00
|
|
|
target_ulong vaddr)
|
2004-01-04 19:06:42 +01:00
|
|
|
{
|
2005-08-21 11:26:42 +02:00
|
|
|
phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG;
|
2004-02-06 20:46:14 +01:00
|
|
|
}
|
|
|
|
|
2007-09-16 23:08:06 +02:00
|
|
|
static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
|
2004-02-06 20:46:14 +01:00
|
|
|
unsigned long start, unsigned long length)
|
|
|
|
{
|
|
|
|
unsigned long addr;
|
2005-11-28 22:19:04 +01:00
|
|
|
if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
|
|
|
|
addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
|
2004-02-06 20:46:14 +01:00
|
|
|
if ((addr - start) < length) {
|
2008-06-09 02:20:13 +02:00
|
|
|
tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY;
|
2004-02-06 20:46:14 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-08-21 11:26:42 +02:00
|
|
|
void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
|
2005-02-10 23:00:27 +01:00
|
|
|
int dirty_flags)
|
2004-02-06 20:46:14 +01:00
|
|
|
{
|
|
|
|
CPUState *env;
|
2004-04-26 21:44:02 +02:00
|
|
|
unsigned long length, start1;
|
2005-02-10 23:00:27 +01:00
|
|
|
int i, mask, len;
|
|
|
|
uint8_t *p;
|
2004-02-06 20:46:14 +01:00
|
|
|
|
|
|
|
start &= TARGET_PAGE_MASK;
|
|
|
|
end = TARGET_PAGE_ALIGN(end);
|
|
|
|
|
|
|
|
length = end - start;
|
|
|
|
if (length == 0)
|
|
|
|
return;
|
2005-02-10 23:00:27 +01:00
|
|
|
len = length >> TARGET_PAGE_BITS;
|
2005-08-21 11:26:42 +02:00
|
|
|
#ifdef USE_KQEMU
|
2005-11-22 00:25:50 +01:00
|
|
|
/* XXX: should not depend on cpu context */
|
|
|
|
env = first_cpu;
|
2005-08-21 11:26:42 +02:00
|
|
|
if (env->kqemu_enabled) {
|
2005-08-21 21:12:28 +02:00
|
|
|
ram_addr_t addr;
|
|
|
|
addr = start;
|
|
|
|
for(i = 0; i < len; i++) {
|
|
|
|
kqemu_set_notdirty(env, addr);
|
|
|
|
addr += TARGET_PAGE_SIZE;
|
|
|
|
}
|
2005-08-21 11:26:42 +02:00
|
|
|
}
|
|
|
|
#endif
|
2005-08-21 21:12:28 +02:00
|
|
|
mask = ~dirty_flags;
|
|
|
|
p = phys_ram_dirty + (start >> TARGET_PAGE_BITS);
|
|
|
|
for(i = 0; i < len; i++)
|
|
|
|
p[i] &= mask;
|
|
|
|
|
2004-02-06 20:46:14 +01:00
|
|
|
/* we modify the TLB cache so that the dirty bit will be set again
|
|
|
|
when accessing the range */
|
2004-02-16 23:01:13 +01:00
|
|
|
start1 = start + (unsigned long)phys_ram_base;
|
2005-11-22 00:25:50 +01:00
|
|
|
for(env = first_cpu; env != NULL; env = env->next_cpu) {
|
|
|
|
for(i = 0; i < CPU_TLB_SIZE; i++)
|
2005-11-28 22:19:04 +01:00
|
|
|
tlb_reset_dirty_range(&env->tlb_table[0][i], start1, length);
|
2005-11-22 00:25:50 +01:00
|
|
|
for(i = 0; i < CPU_TLB_SIZE; i++)
|
2005-11-28 22:19:04 +01:00
|
|
|
tlb_reset_dirty_range(&env->tlb_table[1][i], start1, length);
|
2007-04-05 08:43:27 +02:00
|
|
|
#if (NB_MMU_MODES >= 3)
|
|
|
|
for(i = 0; i < CPU_TLB_SIZE; i++)
|
|
|
|
tlb_reset_dirty_range(&env->tlb_table[2][i], start1, length);
|
|
|
|
#if (NB_MMU_MODES == 4)
|
|
|
|
for(i = 0; i < CPU_TLB_SIZE; i++)
|
|
|
|
tlb_reset_dirty_range(&env->tlb_table[3][i], start1, length);
|
|
|
|
#endif
|
|
|
|
#endif
|
2005-11-22 00:25:50 +01:00
|
|
|
}
|
2004-02-06 20:46:14 +01:00
|
|
|
}
|
|
|
|
|
2008-10-06 16:02:03 +02:00
|
|
|
int cpu_physical_memory_set_dirty_tracking(int enable)
|
|
|
|
{
|
|
|
|
in_migration = enable;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int cpu_physical_memory_get_dirty_tracking(void)
|
|
|
|
{
|
|
|
|
return in_migration;
|
|
|
|
}
|
|
|
|
|
2008-11-24 21:21:41 +01:00
|
|
|
void cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, target_phys_addr_t end_addr)
|
|
|
|
{
|
|
|
|
if (kvm_enabled())
|
|
|
|
kvm_physical_sync_dirty_bitmap(start_addr, end_addr);
|
|
|
|
}
|
|
|
|
|
2005-08-21 11:26:42 +02:00
|
|
|
static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
|
|
|
|
{
|
|
|
|
ram_addr_t ram_addr;
|
|
|
|
|
2005-11-28 22:19:04 +01:00
|
|
|
if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
|
2007-09-16 23:08:06 +02:00
|
|
|
ram_addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) +
|
2005-08-21 11:26:42 +02:00
|
|
|
tlb_entry->addend - (unsigned long)phys_ram_base;
|
|
|
|
if (!cpu_physical_memory_is_dirty(ram_addr)) {
|
2008-06-09 02:20:13 +02:00
|
|
|
tlb_entry->addr_write |= TLB_NOTDIRTY;
|
2005-08-21 11:26:42 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* update the TLB according to the current state of the dirty bits */
|
|
|
|
void cpu_tlb_update_dirty(CPUState *env)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
for(i = 0; i < CPU_TLB_SIZE; i++)
|
2005-11-28 22:19:04 +01:00
|
|
|
tlb_update_dirty(&env->tlb_table[0][i]);
|
2005-08-21 11:26:42 +02:00
|
|
|
for(i = 0; i < CPU_TLB_SIZE; i++)
|
2005-11-28 22:19:04 +01:00
|
|
|
tlb_update_dirty(&env->tlb_table[1][i]);
|
2007-04-05 08:43:27 +02:00
|
|
|
#if (NB_MMU_MODES >= 3)
|
|
|
|
for(i = 0; i < CPU_TLB_SIZE; i++)
|
|
|
|
tlb_update_dirty(&env->tlb_table[2][i]);
|
|
|
|
#if (NB_MMU_MODES == 4)
|
|
|
|
for(i = 0; i < CPU_TLB_SIZE; i++)
|
|
|
|
tlb_update_dirty(&env->tlb_table[3][i]);
|
|
|
|
#endif
|
|
|
|
#endif
|
2005-08-21 11:26:42 +02:00
|
|
|
}
|
|
|
|
|
2008-06-09 02:20:13 +02:00
|
|
|
static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
|
2004-02-06 20:46:14 +01:00
|
|
|
{
|
2008-06-09 02:20:13 +02:00
|
|
|
if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY))
|
|
|
|
tlb_entry->addr_write = vaddr;
|
2004-02-06 20:46:14 +01:00
|
|
|
}
|
|
|
|
|
2008-06-09 02:20:13 +02:00
|
|
|
/* update the TLB corresponding to virtual page vaddr
|
|
|
|
so that it is no longer dirty */
|
|
|
|
static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr)
|
2004-02-06 20:46:14 +01:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2008-06-09 02:20:13 +02:00
|
|
|
vaddr &= TARGET_PAGE_MASK;
|
2004-02-06 20:46:14 +01:00
|
|
|
i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
2008-06-09 02:20:13 +02:00
|
|
|
tlb_set_dirty1(&env->tlb_table[0][i], vaddr);
|
|
|
|
tlb_set_dirty1(&env->tlb_table[1][i], vaddr);
|
2007-04-05 08:43:27 +02:00
|
|
|
#if (NB_MMU_MODES >= 3)
|
2008-06-09 02:20:13 +02:00
|
|
|
tlb_set_dirty1(&env->tlb_table[2][i], vaddr);
|
2007-04-05 08:43:27 +02:00
|
|
|
#if (NB_MMU_MODES == 4)
|
2008-06-09 02:20:13 +02:00
|
|
|
tlb_set_dirty1(&env->tlb_table[3][i], vaddr);
|
2007-04-05 08:43:27 +02:00
|
|
|
#endif
|
|
|
|
#endif
|
2004-01-04 19:06:42 +01:00
|
|
|
}
|
|
|
|
|
2004-02-16 23:01:13 +01:00
|
|
|
/* add a new TLB entry. At most one entry for a given virtual address
|
|
|
|
is permitted. Return 0 if OK or 2 if the page could not be mapped
|
|
|
|
(can only happen in non SOFTMMU mode for I/O pages or pages
|
|
|
|
conflicting with the host address space). */
|
2007-09-16 23:08:06 +02:00
|
|
|
int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
|
|
|
|
target_phys_addr_t paddr, int prot,
|
2007-10-14 09:07:08 +02:00
|
|
|
int mmu_idx, int is_softmmu)
|
2004-01-04 19:06:42 +01:00
|
|
|
{
|
2004-05-21 16:52:29 +02:00
|
|
|
PhysPageDesc *p;
|
2004-04-26 21:44:02 +02:00
|
|
|
unsigned long pd;
|
2004-01-04 19:06:42 +01:00
|
|
|
unsigned int index;
|
2004-04-26 21:44:02 +02:00
|
|
|
target_ulong address;
|
2008-06-09 02:20:13 +02:00
|
|
|
target_ulong code_address;
|
2005-07-24 14:55:09 +02:00
|
|
|
target_phys_addr_t addend;
|
2004-01-04 19:06:42 +01:00
|
|
|
int ret;
|
2005-11-28 22:19:04 +01:00
|
|
|
CPUTLBEntry *te;
|
2008-11-18 21:07:32 +01:00
|
|
|
CPUWatchpoint *wp;
|
2008-06-09 02:20:13 +02:00
|
|
|
target_phys_addr_t iotlb;
|
2004-01-04 19:06:42 +01:00
|
|
|
|
2004-05-21 16:52:29 +02:00
|
|
|
p = phys_page_find(paddr >> TARGET_PAGE_BITS);
|
2004-01-04 19:06:42 +01:00
|
|
|
if (!p) {
|
|
|
|
pd = IO_MEM_UNASSIGNED;
|
|
|
|
} else {
|
|
|
|
pd = p->phys_offset;
|
|
|
|
}
|
|
|
|
#if defined(DEBUG_TLB)
|
2007-10-14 09:07:08 +02:00
|
|
|
printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n",
|
|
|
|
vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd);
|
2004-01-04 19:06:42 +01:00
|
|
|
#endif
|
|
|
|
|
|
|
|
ret = 0;
|
2008-06-09 02:20:13 +02:00
|
|
|
address = vaddr;
|
|
|
|
if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
|
|
|
|
/* IO memory case (romd handled later) */
|
|
|
|
address |= TLB_MMIO;
|
|
|
|
}
|
|
|
|
addend = (unsigned long)phys_ram_base + (pd & TARGET_PAGE_MASK);
|
|
|
|
if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) {
|
|
|
|
/* Normal RAM. */
|
|
|
|
iotlb = pd & TARGET_PAGE_MASK;
|
|
|
|
if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM)
|
|
|
|
iotlb |= IO_MEM_NOTDIRTY;
|
|
|
|
else
|
|
|
|
iotlb |= IO_MEM_ROM;
|
|
|
|
} else {
|
|
|
|
/* IO handlers are currently passed a phsical address.
|
|
|
|
It would be nice to pass an offset from the base address
|
|
|
|
of that region. This would avoid having to special case RAM,
|
|
|
|
and avoid full address decoding in every device.
|
|
|
|
We can't use the high bits of pd for this because
|
|
|
|
IO_MEM_ROMD uses these as a ram address. */
|
|
|
|
iotlb = (pd & ~TARGET_PAGE_MASK) + paddr;
|
|
|
|
}
|
|
|
|
|
|
|
|
code_address = address;
|
|
|
|
/* Make accesses to pages with watchpoints go via the
|
|
|
|
watchpoint trap routines. */
|
2008-11-18 21:07:32 +01:00
|
|
|
for (wp = env->watchpoints; wp != NULL; wp = wp->next) {
|
|
|
|
if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {
|
2008-06-09 02:20:13 +02:00
|
|
|
iotlb = io_mem_watch + paddr;
|
|
|
|
/* TODO: The memory case can be optimized by not trapping
|
|
|
|
reads of pages with a write breakpoint. */
|
|
|
|
address |= TLB_MMIO;
|
2007-03-17 00:58:11 +01:00
|
|
|
}
|
2008-06-09 02:20:13 +02:00
|
|
|
}
|
2007-06-26 22:01:13 +02:00
|
|
|
|
2008-06-09 02:20:13 +02:00
|
|
|
index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
|
|
|
env->iotlb[mmu_idx][index] = iotlb - vaddr;
|
|
|
|
te = &env->tlb_table[mmu_idx][index];
|
|
|
|
te->addend = addend - vaddr;
|
|
|
|
if (prot & PAGE_READ) {
|
|
|
|
te->addr_read = address;
|
|
|
|
} else {
|
|
|
|
te->addr_read = -1;
|
|
|
|
}
|
2008-05-06 10:44:21 +02:00
|
|
|
|
2008-06-09 02:20:13 +02:00
|
|
|
if (prot & PAGE_EXEC) {
|
|
|
|
te->addr_code = code_address;
|
|
|
|
} else {
|
|
|
|
te->addr_code = -1;
|
|
|
|
}
|
|
|
|
if (prot & PAGE_WRITE) {
|
|
|
|
if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM ||
|
|
|
|
(pd & IO_MEM_ROMD)) {
|
|
|
|
/* Write access calls the I/O callback. */
|
|
|
|
te->addr_write = address | TLB_MMIO;
|
|
|
|
} else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM &&
|
|
|
|
!cpu_physical_memory_is_dirty(pd)) {
|
|
|
|
te->addr_write = address | TLB_NOTDIRTY;
|
2004-01-04 19:06:42 +01:00
|
|
|
} else {
|
2008-06-09 02:20:13 +02:00
|
|
|
te->addr_write = address;
|
2004-01-04 19:06:42 +01:00
|
|
|
}
|
2008-06-09 02:20:13 +02:00
|
|
|
} else {
|
|
|
|
te->addr_write = -1;
|
2004-01-04 19:06:42 +01:00
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2004-01-04 16:48:17 +01:00
|
|
|
#else
|
|
|
|
|
2004-02-04 00:35:10 +01:00
|
|
|
void tlb_flush(CPUState *env, int flush_global)
|
2004-01-04 16:48:17 +01:00
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2004-04-25 23:28:44 +02:00
|
|
|
void tlb_flush_page(CPUState *env, target_ulong addr)
|
2004-01-04 16:48:17 +01:00
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2007-09-16 23:08:06 +02:00
|
|
|
int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
|
|
|
|
target_phys_addr_t paddr, int prot,
|
2007-10-14 09:07:08 +02:00
|
|
|
int mmu_idx, int is_softmmu)
|
2004-01-04 19:06:42 +01:00
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
2004-01-04 16:48:17 +01:00
|
|
|
|
2004-01-04 19:06:42 +01:00
|
|
|
/* dump memory mappings */
|
|
|
|
void page_dump(FILE *f)
|
2003-08-10 23:47:01 +02:00
|
|
|
{
|
2004-01-04 19:06:42 +01:00
|
|
|
unsigned long start, end;
|
|
|
|
int i, j, prot, prot1;
|
|
|
|
PageDesc *p;
|
2003-08-10 23:47:01 +02:00
|
|
|
|
2004-01-04 19:06:42 +01:00
|
|
|
fprintf(f, "%-8s %-8s %-8s %s\n",
|
|
|
|
"start", "end", "size", "prot");
|
|
|
|
start = -1;
|
|
|
|
end = -1;
|
|
|
|
prot = 0;
|
|
|
|
for(i = 0; i <= L1_SIZE; i++) {
|
|
|
|
if (i < L1_SIZE)
|
|
|
|
p = l1_map[i];
|
|
|
|
else
|
|
|
|
p = NULL;
|
|
|
|
for(j = 0;j < L2_SIZE; j++) {
|
|
|
|
if (!p)
|
|
|
|
prot1 = 0;
|
|
|
|
else
|
|
|
|
prot1 = p[j].flags;
|
|
|
|
if (prot1 != prot) {
|
|
|
|
end = (i << (32 - L1_BITS)) | (j << TARGET_PAGE_BITS);
|
|
|
|
if (start != -1) {
|
|
|
|
fprintf(f, "%08lx-%08lx %08lx %c%c%c\n",
|
2007-09-16 23:08:06 +02:00
|
|
|
start, end, end - start,
|
2004-01-04 19:06:42 +01:00
|
|
|
prot & PAGE_READ ? 'r' : '-',
|
|
|
|
prot & PAGE_WRITE ? 'w' : '-',
|
|
|
|
prot & PAGE_EXEC ? 'x' : '-');
|
|
|
|
}
|
|
|
|
if (prot1 != 0)
|
|
|
|
start = end;
|
|
|
|
else
|
|
|
|
start = -1;
|
|
|
|
prot = prot1;
|
|
|
|
}
|
|
|
|
if (!p)
|
|
|
|
break;
|
|
|
|
}
|
2003-08-10 23:47:01 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-03-25 20:31:22 +01:00
|
|
|
int page_get_flags(target_ulong address)
|
2003-08-10 23:47:01 +02:00
|
|
|
{
|
2004-01-04 19:06:42 +01:00
|
|
|
PageDesc *p;
|
|
|
|
|
|
|
|
p = page_find(address >> TARGET_PAGE_BITS);
|
2003-08-10 23:47:01 +02:00
|
|
|
if (!p)
|
2004-01-04 19:06:42 +01:00
|
|
|
return 0;
|
|
|
|
return p->flags;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* modify the flags of a page and invalidate the code if
|
|
|
|
necessary. The flag PAGE_WRITE_ORG is positionned automatically
|
|
|
|
depending on PAGE_WRITE */
|
2006-03-25 20:31:22 +01:00
|
|
|
void page_set_flags(target_ulong start, target_ulong end, int flags)
|
2004-01-04 19:06:42 +01:00
|
|
|
{
|
|
|
|
PageDesc *p;
|
2006-03-25 20:31:22 +01:00
|
|
|
target_ulong addr;
|
2004-01-04 19:06:42 +01:00
|
|
|
|
2008-06-02 18:16:42 +02:00
|
|
|
/* mmap_lock should already be held. */
|
2004-01-04 19:06:42 +01:00
|
|
|
start = start & TARGET_PAGE_MASK;
|
|
|
|
end = TARGET_PAGE_ALIGN(end);
|
|
|
|
if (flags & PAGE_WRITE)
|
|
|
|
flags |= PAGE_WRITE_ORG;
|
|
|
|
for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
|
|
|
|
p = page_find_alloc(addr >> TARGET_PAGE_BITS);
|
2008-06-09 15:47:45 +02:00
|
|
|
/* We may be called for host regions that are outside guest
|
|
|
|
address space. */
|
|
|
|
if (!p)
|
|
|
|
return;
|
2004-01-04 19:06:42 +01:00
|
|
|
/* if the write protection is set, then we invalidate the code
|
|
|
|
inside */
|
2007-09-16 23:08:06 +02:00
|
|
|
if (!(p->flags & PAGE_WRITE) &&
|
2004-01-04 19:06:42 +01:00
|
|
|
(flags & PAGE_WRITE) &&
|
|
|
|
p->first_tb) {
|
2004-04-25 19:57:43 +02:00
|
|
|
tb_invalidate_phys_page(addr, 0, NULL);
|
2004-01-04 19:06:42 +01:00
|
|
|
}
|
|
|
|
p->flags = flags;
|
|
|
|
}
|
2003-08-10 23:47:01 +02:00
|
|
|
}
|
|
|
|
|
2007-11-02 20:02:07 +01:00
|
|
|
int page_check_range(target_ulong start, target_ulong len, int flags)
|
|
|
|
{
|
|
|
|
PageDesc *p;
|
|
|
|
target_ulong end;
|
|
|
|
target_ulong addr;
|
|
|
|
|
2008-10-28 11:24:11 +01:00
|
|
|
if (start + len < start)
|
|
|
|
/* we've wrapped around */
|
|
|
|
return -1;
|
|
|
|
|
2007-11-02 20:02:07 +01:00
|
|
|
end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */
|
|
|
|
start = start & TARGET_PAGE_MASK;
|
|
|
|
|
|
|
|
for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
|
|
|
|
p = page_find(addr >> TARGET_PAGE_BITS);
|
|
|
|
if( !p )
|
|
|
|
return -1;
|
|
|
|
if( !(p->flags & PAGE_VALID) )
|
|
|
|
return -1;
|
|
|
|
|
2007-11-14 11:51:00 +01:00
|
|
|
if ((flags & PAGE_READ) && !(p->flags & PAGE_READ))
|
2007-11-02 20:02:07 +01:00
|
|
|
return -1;
|
2007-11-14 11:51:00 +01:00
|
|
|
if (flags & PAGE_WRITE) {
|
|
|
|
if (!(p->flags & PAGE_WRITE_ORG))
|
|
|
|
return -1;
|
|
|
|
/* unprotect the page if it was put read-only because it
|
|
|
|
contains translated code */
|
|
|
|
if (!(p->flags & PAGE_WRITE)) {
|
|
|
|
if (!page_unprotect(addr, 0, NULL))
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
2007-11-02 20:02:07 +01:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2004-01-04 19:06:42 +01:00
|
|
|
/* called from signal handler: invalidate the code and unprotect the
|
|
|
|
page. Return TRUE if the fault was succesfully handled. */
|
2006-03-25 20:31:22 +01:00
|
|
|
int page_unprotect(target_ulong address, unsigned long pc, void *puc)
|
2004-01-04 19:06:42 +01:00
|
|
|
{
|
|
|
|
unsigned int page_index, prot, pindex;
|
|
|
|
PageDesc *p, *p1;
|
2006-03-25 20:31:22 +01:00
|
|
|
target_ulong host_start, host_end, addr;
|
2004-01-04 19:06:42 +01:00
|
|
|
|
2008-06-02 18:16:42 +02:00
|
|
|
/* Technically this isn't safe inside a signal handler. However we
|
|
|
|
know this only ever happens in a synchronous SEGV handler, so in
|
|
|
|
practice it seems to be ok. */
|
|
|
|
mmap_lock();
|
|
|
|
|
2004-07-05 23:25:26 +02:00
|
|
|
host_start = address & qemu_host_page_mask;
|
2004-01-04 19:06:42 +01:00
|
|
|
page_index = host_start >> TARGET_PAGE_BITS;
|
|
|
|
p1 = page_find(page_index);
|
2008-06-02 18:16:42 +02:00
|
|
|
if (!p1) {
|
|
|
|
mmap_unlock();
|
2004-01-04 19:06:42 +01:00
|
|
|
return 0;
|
2008-06-02 18:16:42 +02:00
|
|
|
}
|
2004-07-05 23:25:26 +02:00
|
|
|
host_end = host_start + qemu_host_page_size;
|
2004-01-04 19:06:42 +01:00
|
|
|
p = p1;
|
|
|
|
prot = 0;
|
|
|
|
for(addr = host_start;addr < host_end; addr += TARGET_PAGE_SIZE) {
|
|
|
|
prot |= p->flags;
|
|
|
|
p++;
|
|
|
|
}
|
|
|
|
/* if the page was really writable, then we change its
|
|
|
|
protection back to writable */
|
|
|
|
if (prot & PAGE_WRITE_ORG) {
|
|
|
|
pindex = (address - host_start) >> TARGET_PAGE_BITS;
|
|
|
|
if (!(p1[pindex].flags & PAGE_WRITE)) {
|
2007-09-16 23:08:06 +02:00
|
|
|
mprotect((void *)g2h(host_start), qemu_host_page_size,
|
2004-01-04 19:06:42 +01:00
|
|
|
(prot & PAGE_BITS) | PAGE_WRITE);
|
|
|
|
p1[pindex].flags |= PAGE_WRITE;
|
|
|
|
/* and since the content will be modified, we must invalidate
|
|
|
|
the corresponding translated code. */
|
2004-04-25 19:57:43 +02:00
|
|
|
tb_invalidate_phys_page(address, pc, puc);
|
2004-01-04 19:06:42 +01:00
|
|
|
#ifdef DEBUG_TB_CHECK
|
|
|
|
tb_invalidate_check(address);
|
|
|
|
#endif
|
2008-06-02 18:16:42 +02:00
|
|
|
mmap_unlock();
|
2004-01-04 19:06:42 +01:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
}
|
2008-06-02 18:16:42 +02:00
|
|
|
mmap_unlock();
|
2004-01-04 19:06:42 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-11-22 00:25:50 +01:00
|
|
|
static inline void tlb_set_dirty(CPUState *env,
|
|
|
|
unsigned long addr, target_ulong vaddr)
|
2004-02-06 20:46:14 +01:00
|
|
|
{
|
|
|
|
}
|
2004-01-04 19:06:42 +01:00
|
|
|
#endif /* defined(CONFIG_USER_ONLY) */
|
|
|
|
|
2008-06-08 03:09:01 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2007-05-26 19:36:03 +02:00
|
|
|
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
|
2008-04-27 23:12:55 +02:00
|
|
|
ram_addr_t memory);
|
|
|
|
static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
|
|
|
|
ram_addr_t orig_memory);
|
2007-05-26 19:36:03 +02:00
|
|
|
#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
|
|
|
|
need_subpage) \
|
|
|
|
do { \
|
|
|
|
if (addr > start_addr) \
|
|
|
|
start_addr2 = 0; \
|
|
|
|
else { \
|
|
|
|
start_addr2 = start_addr & ~TARGET_PAGE_MASK; \
|
|
|
|
if (start_addr2 > 0) \
|
|
|
|
need_subpage = 1; \
|
|
|
|
} \
|
|
|
|
\
|
2007-05-30 19:25:06 +02:00
|
|
|
if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \
|
2007-05-26 19:36:03 +02:00
|
|
|
end_addr2 = TARGET_PAGE_SIZE - 1; \
|
|
|
|
else { \
|
|
|
|
end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \
|
|
|
|
if (end_addr2 < TARGET_PAGE_SIZE - 1) \
|
|
|
|
need_subpage = 1; \
|
|
|
|
} \
|
|
|
|
} while (0)
|
|
|
|
|
2003-08-10 23:47:01 +02:00
|
|
|
/* register physical memory. 'size' must be a multiple of the target
|
|
|
|
page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
|
|
|
|
io memory page */
|
2007-09-16 23:08:06 +02:00
|
|
|
void cpu_register_physical_memory(target_phys_addr_t start_addr,
|
2008-04-27 23:12:55 +02:00
|
|
|
ram_addr_t size,
|
|
|
|
ram_addr_t phys_offset)
|
2003-08-10 23:47:01 +02:00
|
|
|
{
|
2005-07-24 14:55:09 +02:00
|
|
|
target_phys_addr_t addr, end_addr;
|
2004-05-21 16:52:29 +02:00
|
|
|
PhysPageDesc *p;
|
2006-06-26 00:25:22 +02:00
|
|
|
CPUState *env;
|
2008-04-27 23:12:55 +02:00
|
|
|
ram_addr_t orig_size = size;
|
2007-05-26 19:36:03 +02:00
|
|
|
void *subpage;
|
2003-08-10 23:47:01 +02:00
|
|
|
|
2008-05-30 22:48:25 +02:00
|
|
|
#ifdef USE_KQEMU
|
|
|
|
/* XXX: should not depend on cpu context */
|
|
|
|
env = first_cpu;
|
|
|
|
if (env->kqemu_enabled) {
|
|
|
|
kqemu_set_phys_mem(start_addr, size, phys_offset);
|
|
|
|
}
|
|
|
|
#endif
|
2008-11-05 17:04:33 +01:00
|
|
|
if (kvm_enabled())
|
|
|
|
kvm_set_phys_mem(start_addr, size, phys_offset);
|
|
|
|
|
2004-05-23 23:11:22 +02:00
|
|
|
size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
|
2007-05-30 19:25:06 +02:00
|
|
|
end_addr = start_addr + (target_phys_addr_t)size;
|
|
|
|
for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
|
2007-05-26 19:36:03 +02:00
|
|
|
p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
|
|
|
if (p && p->phys_offset != IO_MEM_UNASSIGNED) {
|
2008-04-27 23:12:55 +02:00
|
|
|
ram_addr_t orig_memory = p->phys_offset;
|
2007-05-26 19:36:03 +02:00
|
|
|
target_phys_addr_t start_addr2, end_addr2;
|
|
|
|
int need_subpage = 0;
|
|
|
|
|
|
|
|
CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2,
|
|
|
|
need_subpage);
|
2008-01-01 17:57:19 +01:00
|
|
|
if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
|
2007-05-26 19:36:03 +02:00
|
|
|
if (!(orig_memory & IO_MEM_SUBPAGE)) {
|
|
|
|
subpage = subpage_init((addr & TARGET_PAGE_MASK),
|
|
|
|
&p->phys_offset, orig_memory);
|
|
|
|
} else {
|
|
|
|
subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK)
|
|
|
|
>> IO_MEM_SHIFT];
|
|
|
|
}
|
|
|
|
subpage_register(subpage, start_addr2, end_addr2, phys_offset);
|
|
|
|
} else {
|
|
|
|
p->phys_offset = phys_offset;
|
|
|
|
if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
|
|
|
|
(phys_offset & IO_MEM_ROMD))
|
|
|
|
phys_offset += TARGET_PAGE_SIZE;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
|
|
|
|
p->phys_offset = phys_offset;
|
|
|
|
if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
|
|
|
|
(phys_offset & IO_MEM_ROMD))
|
|
|
|
phys_offset += TARGET_PAGE_SIZE;
|
|
|
|
else {
|
|
|
|
target_phys_addr_t start_addr2, end_addr2;
|
|
|
|
int need_subpage = 0;
|
|
|
|
|
|
|
|
CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr,
|
|
|
|
end_addr2, need_subpage);
|
|
|
|
|
2008-01-01 17:57:19 +01:00
|
|
|
if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
|
2007-05-26 19:36:03 +02:00
|
|
|
subpage = subpage_init((addr & TARGET_PAGE_MASK),
|
|
|
|
&p->phys_offset, IO_MEM_UNASSIGNED);
|
|
|
|
subpage_register(subpage, start_addr2, end_addr2,
|
|
|
|
phys_offset);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2003-08-10 23:47:01 +02:00
|
|
|
}
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2006-06-26 00:25:22 +02:00
|
|
|
/* since each CPU stores ram addresses in its TLB cache, we must
|
|
|
|
reset the modified entries */
|
|
|
|
/* XXX: slow ! */
|
|
|
|
for(env = first_cpu; env != NULL; env = env->next_cpu) {
|
|
|
|
tlb_flush(env, 1);
|
|
|
|
}
|
2003-08-10 23:47:01 +02:00
|
|
|
}
|
|
|
|
|
2006-09-24 20:41:10 +02:00
|
|
|
/* XXX: temporary until new memory mapping API */
|
2008-04-27 23:12:55 +02:00
|
|
|
ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr)
|
2006-09-24 20:41:10 +02:00
|
|
|
{
|
|
|
|
PhysPageDesc *p;
|
|
|
|
|
|
|
|
p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
|
|
|
if (!p)
|
|
|
|
return IO_MEM_UNASSIGNED;
|
|
|
|
return p->phys_offset;
|
|
|
|
}
|
|
|
|
|
2007-02-09 00:08:38 +01:00
|
|
|
/* XXX: better than nothing */
|
2008-04-27 23:12:55 +02:00
|
|
|
ram_addr_t qemu_ram_alloc(ram_addr_t size)
|
2007-02-09 00:08:38 +01:00
|
|
|
{
|
|
|
|
ram_addr_t addr;
|
2008-04-24 19:59:27 +02:00
|
|
|
if ((phys_ram_alloc_offset + size) > phys_ram_size) {
|
2008-10-02 19:34:21 +02:00
|
|
|
fprintf(stderr, "Not enough memory (requested_size = %" PRIu64 ", max memory = %" PRIu64 ")\n",
|
2008-05-23 13:56:45 +02:00
|
|
|
(uint64_t)size, (uint64_t)phys_ram_size);
|
2007-02-09 00:08:38 +01:00
|
|
|
abort();
|
|
|
|
}
|
|
|
|
addr = phys_ram_alloc_offset;
|
|
|
|
phys_ram_alloc_offset = TARGET_PAGE_ALIGN(phys_ram_alloc_offset + size);
|
|
|
|
return addr;
|
|
|
|
}
|
|
|
|
|
|
|
|
void qemu_ram_free(ram_addr_t addr)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2004-06-03 16:01:43 +02:00
|
|
|
static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
|
2003-08-10 23:47:01 +02:00
|
|
|
{
|
2006-12-18 06:03:52 +01:00
|
|
|
#ifdef DEBUG_UNASSIGNED
|
2007-11-04 08:31:40 +01:00
|
|
|
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
|
2007-05-06 19:59:24 +02:00
|
|
|
#endif
|
2008-10-06 20:46:28 +02:00
|
|
|
#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
|
|
|
|
do_unassigned_access(addr, 0, 0, 0, 1);
|
|
|
|
#endif
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr)
|
|
|
|
{
|
|
|
|
#ifdef DEBUG_UNASSIGNED
|
|
|
|
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
|
|
|
|
#endif
|
|
|
|
#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
|
|
|
|
do_unassigned_access(addr, 0, 0, 0, 2);
|
|
|
|
#endif
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr)
|
|
|
|
{
|
|
|
|
#ifdef DEBUG_UNASSIGNED
|
|
|
|
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
|
|
|
|
#endif
|
|
|
|
#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
|
|
|
|
do_unassigned_access(addr, 0, 0, 0, 4);
|
2006-12-18 06:03:52 +01:00
|
|
|
#endif
|
2003-08-10 23:47:01 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2004-06-03 16:01:43 +02:00
|
|
|
static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
|
2003-08-10 23:47:01 +02:00
|
|
|
{
|
2006-12-18 06:03:52 +01:00
|
|
|
#ifdef DEBUG_UNASSIGNED
|
2007-11-04 08:31:40 +01:00
|
|
|
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
|
2006-12-18 06:03:52 +01:00
|
|
|
#endif
|
2008-10-06 20:46:28 +02:00
|
|
|
#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
|
|
|
|
do_unassigned_access(addr, 1, 0, 0, 1);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
|
|
{
|
|
|
|
#ifdef DEBUG_UNASSIGNED
|
|
|
|
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
|
|
|
|
#endif
|
|
|
|
#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
|
|
|
|
do_unassigned_access(addr, 1, 0, 0, 2);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
|
|
{
|
|
|
|
#ifdef DEBUG_UNASSIGNED
|
|
|
|
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
|
|
|
|
#endif
|
|
|
|
#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
|
|
|
|
do_unassigned_access(addr, 1, 0, 0, 4);
|
2007-05-06 19:59:24 +02:00
|
|
|
#endif
|
2003-08-10 23:47:01 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static CPUReadMemoryFunc *unassigned_mem_read[3] = {
|
|
|
|
unassigned_mem_readb,
|
2008-10-06 20:46:28 +02:00
|
|
|
unassigned_mem_readw,
|
|
|
|
unassigned_mem_readl,
|
2003-08-10 23:47:01 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
static CPUWriteMemoryFunc *unassigned_mem_write[3] = {
|
|
|
|
unassigned_mem_writeb,
|
2008-10-06 20:46:28 +02:00
|
|
|
unassigned_mem_writew,
|
|
|
|
unassigned_mem_writel,
|
2003-08-10 23:47:01 +02:00
|
|
|
};
|
|
|
|
|
2008-06-09 02:20:13 +02:00
|
|
|
static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr,
|
|
|
|
uint32_t val)
|
2004-01-04 19:06:42 +01:00
|
|
|
{
|
2005-08-21 11:26:42 +02:00
|
|
|
int dirty_flags;
|
|
|
|
dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
|
|
|
|
if (!(dirty_flags & CODE_DIRTY_FLAG)) {
|
2004-01-04 19:06:42 +01:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2005-08-21 11:26:42 +02:00
|
|
|
tb_invalidate_phys_page_fast(ram_addr, 1);
|
|
|
|
dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
|
2004-01-04 19:06:42 +01:00
|
|
|
#endif
|
2005-08-21 11:26:42 +02:00
|
|
|
}
|
2008-06-09 02:20:13 +02:00
|
|
|
stb_p(phys_ram_base + ram_addr, val);
|
2006-02-08 23:43:39 +01:00
|
|
|
#ifdef USE_KQEMU
|
|
|
|
if (cpu_single_env->kqemu_enabled &&
|
|
|
|
(dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
|
|
|
|
kqemu_modify_page(cpu_single_env, ram_addr);
|
|
|
|
#endif
|
2005-08-21 21:12:28 +02:00
|
|
|
dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
|
|
|
|
phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
|
|
|
|
/* we remove the notdirty callback only if the code has been
|
|
|
|
flushed */
|
|
|
|
if (dirty_flags == 0xff)
|
2008-06-29 03:03:05 +02:00
|
|
|
tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
|
2004-01-04 19:06:42 +01:00
|
|
|
}
|
|
|
|
|
2008-06-09 02:20:13 +02:00
|
|
|
static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr,
|
|
|
|
uint32_t val)
|
2004-01-04 19:06:42 +01:00
|
|
|
{
|
2005-08-21 11:26:42 +02:00
|
|
|
int dirty_flags;
|
|
|
|
dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
|
|
|
|
if (!(dirty_flags & CODE_DIRTY_FLAG)) {
|
2004-01-04 19:06:42 +01:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2005-08-21 11:26:42 +02:00
|
|
|
tb_invalidate_phys_page_fast(ram_addr, 2);
|
|
|
|
dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
|
2004-01-04 19:06:42 +01:00
|
|
|
#endif
|
2005-08-21 11:26:42 +02:00
|
|
|
}
|
2008-06-09 02:20:13 +02:00
|
|
|
stw_p(phys_ram_base + ram_addr, val);
|
2006-02-08 23:43:39 +01:00
|
|
|
#ifdef USE_KQEMU
|
|
|
|
if (cpu_single_env->kqemu_enabled &&
|
|
|
|
(dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
|
|
|
|
kqemu_modify_page(cpu_single_env, ram_addr);
|
|
|
|
#endif
|
2005-08-21 21:12:28 +02:00
|
|
|
dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
|
|
|
|
phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
|
|
|
|
/* we remove the notdirty callback only if the code has been
|
|
|
|
flushed */
|
|
|
|
if (dirty_flags == 0xff)
|
2008-06-29 03:03:05 +02:00
|
|
|
tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
|
2004-01-04 19:06:42 +01:00
|
|
|
}
|
|
|
|
|
2008-06-09 02:20:13 +02:00
|
|
|
static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr,
|
|
|
|
uint32_t val)
|
2004-01-04 19:06:42 +01:00
|
|
|
{
|
2005-08-21 11:26:42 +02:00
|
|
|
int dirty_flags;
|
|
|
|
dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
|
|
|
|
if (!(dirty_flags & CODE_DIRTY_FLAG)) {
|
2004-01-04 19:06:42 +01:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2005-08-21 11:26:42 +02:00
|
|
|
tb_invalidate_phys_page_fast(ram_addr, 4);
|
|
|
|
dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
|
2004-01-04 19:06:42 +01:00
|
|
|
#endif
|
2005-08-21 11:26:42 +02:00
|
|
|
}
|
2008-06-09 02:20:13 +02:00
|
|
|
stl_p(phys_ram_base + ram_addr, val);
|
2006-02-08 23:43:39 +01:00
|
|
|
#ifdef USE_KQEMU
|
|
|
|
if (cpu_single_env->kqemu_enabled &&
|
|
|
|
(dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
|
|
|
|
kqemu_modify_page(cpu_single_env, ram_addr);
|
|
|
|
#endif
|
2005-08-21 21:12:28 +02:00
|
|
|
dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
|
|
|
|
phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
|
|
|
|
/* we remove the notdirty callback only if the code has been
|
|
|
|
flushed */
|
|
|
|
if (dirty_flags == 0xff)
|
2008-06-29 03:03:05 +02:00
|
|
|
tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
|
2004-01-04 19:06:42 +01:00
|
|
|
}
|
|
|
|
|
2005-08-21 11:26:42 +02:00
|
|
|
static CPUReadMemoryFunc *error_mem_read[3] = {
|
2004-01-04 19:06:42 +01:00
|
|
|
NULL, /* never used */
|
|
|
|
NULL, /* never used */
|
|
|
|
NULL, /* never used */
|
|
|
|
};
|
|
|
|
|
2004-02-06 20:46:14 +01:00
|
|
|
static CPUWriteMemoryFunc *notdirty_mem_write[3] = {
|
|
|
|
notdirty_mem_writeb,
|
|
|
|
notdirty_mem_writew,
|
|
|
|
notdirty_mem_writel,
|
|
|
|
};
|
|
|
|
|
2008-06-09 02:20:13 +02:00
|
|
|
/* Generate a debug exception if a watchpoint has been hit. */
|
2008-11-18 21:14:20 +01:00
|
|
|
static void check_watchpoint(int offset, int len_mask, int flags)
|
2008-06-09 02:20:13 +02:00
|
|
|
{
|
|
|
|
CPUState *env = cpu_single_env;
|
2008-11-18 21:24:06 +01:00
|
|
|
target_ulong pc, cs_base;
|
|
|
|
TranslationBlock *tb;
|
2008-06-09 02:20:13 +02:00
|
|
|
target_ulong vaddr;
|
2008-11-18 21:07:32 +01:00
|
|
|
CPUWatchpoint *wp;
|
2008-11-18 21:24:06 +01:00
|
|
|
int cpu_flags;
|
2008-06-09 02:20:13 +02:00
|
|
|
|
2008-11-18 21:24:06 +01:00
|
|
|
if (env->watchpoint_hit) {
|
|
|
|
/* We re-entered the check after replacing the TB. Now raise
|
|
|
|
* the debug interrupt so that is will trigger after the
|
|
|
|
* current instruction. */
|
|
|
|
cpu_interrupt(env, CPU_INTERRUPT_DEBUG);
|
|
|
|
return;
|
|
|
|
}
|
2008-06-29 03:03:05 +02:00
|
|
|
vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
|
2008-11-18 21:07:32 +01:00
|
|
|
for (wp = env->watchpoints; wp != NULL; wp = wp->next) {
|
2008-11-18 21:14:20 +01:00
|
|
|
if ((vaddr == (wp->vaddr & len_mask) ||
|
|
|
|
(vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) {
|
2008-11-18 21:37:55 +01:00
|
|
|
wp->flags |= BP_WATCHPOINT_HIT;
|
|
|
|
if (!env->watchpoint_hit) {
|
|
|
|
env->watchpoint_hit = wp;
|
|
|
|
tb = tb_find_pc(env->mem_io_pc);
|
|
|
|
if (!tb) {
|
|
|
|
cpu_abort(env, "check_watchpoint: could not find TB for "
|
|
|
|
"pc=%p", (void *)env->mem_io_pc);
|
|
|
|
}
|
|
|
|
cpu_restore_state(tb, env, env->mem_io_pc, NULL);
|
|
|
|
tb_phys_invalidate(tb, -1);
|
|
|
|
if (wp->flags & BP_STOP_BEFORE_ACCESS) {
|
|
|
|
env->exception_index = EXCP_DEBUG;
|
|
|
|
} else {
|
|
|
|
cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
|
|
|
|
tb_gen_code(env, pc, cs_base, cpu_flags, 1);
|
|
|
|
}
|
|
|
|
cpu_resume_from_signal(env, NULL);
|
2008-11-18 21:24:06 +01:00
|
|
|
}
|
2008-11-18 21:37:55 +01:00
|
|
|
} else {
|
|
|
|
wp->flags &= ~BP_WATCHPOINT_HIT;
|
2008-06-09 02:20:13 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-03-17 00:58:11 +01:00
|
|
|
/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
|
|
|
|
so these check for a hit then pass through to the normal out-of-line
|
|
|
|
phys routines. */
|
|
|
|
static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr)
|
|
|
|
{
|
2008-11-18 21:14:20 +01:00
|
|
|
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ);
|
2007-03-17 00:58:11 +01:00
|
|
|
return ldub_phys(addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr)
|
|
|
|
{
|
2008-11-18 21:14:20 +01:00
|
|
|
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ);
|
2007-03-17 00:58:11 +01:00
|
|
|
return lduw_phys(addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr)
|
|
|
|
{
|
2008-11-18 21:14:20 +01:00
|
|
|
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ);
|
2007-03-17 00:58:11 +01:00
|
|
|
return ldl_phys(addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void watch_mem_writeb(void *opaque, target_phys_addr_t addr,
|
|
|
|
uint32_t val)
|
|
|
|
{
|
2008-11-18 21:14:20 +01:00
|
|
|
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE);
|
2007-03-17 00:58:11 +01:00
|
|
|
stb_phys(addr, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void watch_mem_writew(void *opaque, target_phys_addr_t addr,
|
|
|
|
uint32_t val)
|
|
|
|
{
|
2008-11-18 21:14:20 +01:00
|
|
|
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE);
|
2007-03-17 00:58:11 +01:00
|
|
|
stw_phys(addr, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void watch_mem_writel(void *opaque, target_phys_addr_t addr,
|
|
|
|
uint32_t val)
|
|
|
|
{
|
2008-11-18 21:14:20 +01:00
|
|
|
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE);
|
2007-03-17 00:58:11 +01:00
|
|
|
stl_phys(addr, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static CPUReadMemoryFunc *watch_mem_read[3] = {
|
|
|
|
watch_mem_readb,
|
|
|
|
watch_mem_readw,
|
|
|
|
watch_mem_readl,
|
|
|
|
};
|
|
|
|
|
|
|
|
static CPUWriteMemoryFunc *watch_mem_write[3] = {
|
|
|
|
watch_mem_writeb,
|
|
|
|
watch_mem_writew,
|
|
|
|
watch_mem_writel,
|
|
|
|
};
|
|
|
|
|
2007-05-26 19:36:03 +02:00
|
|
|
static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr,
|
|
|
|
unsigned int len)
|
|
|
|
{
|
|
|
|
uint32_t ret;
|
|
|
|
unsigned int idx;
|
|
|
|
|
|
|
|
idx = SUBPAGE_IDX(addr - mmio->base);
|
|
|
|
#if defined(DEBUG_SUBPAGE)
|
|
|
|
printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
|
|
|
|
mmio, len, addr, idx);
|
|
|
|
#endif
|
2008-01-02 20:45:26 +01:00
|
|
|
ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len], addr);
|
2007-05-26 19:36:03 +02:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr,
|
|
|
|
uint32_t value, unsigned int len)
|
|
|
|
{
|
|
|
|
unsigned int idx;
|
|
|
|
|
|
|
|
idx = SUBPAGE_IDX(addr - mmio->base);
|
|
|
|
#if defined(DEBUG_SUBPAGE)
|
|
|
|
printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__,
|
|
|
|
mmio, len, addr, idx, value);
|
|
|
|
#endif
|
2008-01-02 20:45:26 +01:00
|
|
|
(**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len], addr, value);
|
2007-05-26 19:36:03 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr)
|
|
|
|
{
|
|
|
|
#if defined(DEBUG_SUBPAGE)
|
|
|
|
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return subpage_readlen(opaque, addr, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void subpage_writeb (void *opaque, target_phys_addr_t addr,
|
|
|
|
uint32_t value)
|
|
|
|
{
|
|
|
|
#if defined(DEBUG_SUBPAGE)
|
|
|
|
printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
|
|
|
|
#endif
|
|
|
|
subpage_writelen(opaque, addr, value, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr)
|
|
|
|
{
|
|
|
|
#if defined(DEBUG_SUBPAGE)
|
|
|
|
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return subpage_readlen(opaque, addr, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void subpage_writew (void *opaque, target_phys_addr_t addr,
|
|
|
|
uint32_t value)
|
|
|
|
{
|
|
|
|
#if defined(DEBUG_SUBPAGE)
|
|
|
|
printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
|
|
|
|
#endif
|
|
|
|
subpage_writelen(opaque, addr, value, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr)
|
|
|
|
{
|
|
|
|
#if defined(DEBUG_SUBPAGE)
|
|
|
|
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return subpage_readlen(opaque, addr, 2);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void subpage_writel (void *opaque,
|
|
|
|
target_phys_addr_t addr, uint32_t value)
|
|
|
|
{
|
|
|
|
#if defined(DEBUG_SUBPAGE)
|
|
|
|
printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
|
|
|
|
#endif
|
|
|
|
subpage_writelen(opaque, addr, value, 2);
|
|
|
|
}
|
|
|
|
|
|
|
|
static CPUReadMemoryFunc *subpage_read[] = {
|
|
|
|
&subpage_readb,
|
|
|
|
&subpage_readw,
|
|
|
|
&subpage_readl,
|
|
|
|
};
|
|
|
|
|
|
|
|
static CPUWriteMemoryFunc *subpage_write[] = {
|
|
|
|
&subpage_writeb,
|
|
|
|
&subpage_writew,
|
|
|
|
&subpage_writel,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
|
2008-04-27 23:12:55 +02:00
|
|
|
ram_addr_t memory)
|
2007-05-26 19:36:03 +02:00
|
|
|
{
|
|
|
|
int idx, eidx;
|
2008-01-01 17:57:19 +01:00
|
|
|
unsigned int i;
|
2007-05-26 19:36:03 +02:00
|
|
|
|
|
|
|
if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
|
|
|
|
return -1;
|
|
|
|
idx = SUBPAGE_IDX(start);
|
|
|
|
eidx = SUBPAGE_IDX(end);
|
|
|
|
#if defined(DEBUG_SUBPAGE)
|
|
|
|
printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %d\n", __func__,
|
|
|
|
mmio, start, end, idx, eidx, memory);
|
|
|
|
#endif
|
|
|
|
memory >>= IO_MEM_SHIFT;
|
|
|
|
for (; idx <= eidx; idx++) {
|
2008-01-01 17:57:19 +01:00
|
|
|
for (i = 0; i < 4; i++) {
|
2008-01-02 20:45:26 +01:00
|
|
|
if (io_mem_read[memory][i]) {
|
|
|
|
mmio->mem_read[idx][i] = &io_mem_read[memory][i];
|
|
|
|
mmio->opaque[idx][0][i] = io_mem_opaque[memory];
|
|
|
|
}
|
|
|
|
if (io_mem_write[memory][i]) {
|
|
|
|
mmio->mem_write[idx][i] = &io_mem_write[memory][i];
|
|
|
|
mmio->opaque[idx][1][i] = io_mem_opaque[memory];
|
|
|
|
}
|
2008-01-01 17:57:19 +01:00
|
|
|
}
|
2007-05-26 19:36:03 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-04-27 23:12:55 +02:00
|
|
|
static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
|
|
|
|
ram_addr_t orig_memory)
|
2007-05-26 19:36:03 +02:00
|
|
|
{
|
|
|
|
subpage_t *mmio;
|
|
|
|
int subpage_memory;
|
|
|
|
|
|
|
|
mmio = qemu_mallocz(sizeof(subpage_t));
|
|
|
|
if (mmio != NULL) {
|
|
|
|
mmio->base = base;
|
|
|
|
subpage_memory = cpu_register_io_memory(0, subpage_read, subpage_write, mmio);
|
|
|
|
#if defined(DEBUG_SUBPAGE)
|
|
|
|
printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
|
|
|
|
mmio, base, TARGET_PAGE_SIZE, subpage_memory);
|
|
|
|
#endif
|
|
|
|
*phys = subpage_memory | IO_MEM_SUBPAGE;
|
|
|
|
subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory);
|
|
|
|
}
|
|
|
|
|
|
|
|
return mmio;
|
|
|
|
}
|
|
|
|
|
2003-08-10 23:47:01 +02:00
|
|
|
static void io_mem_init(void)
|
|
|
|
{
|
2005-08-21 11:26:42 +02:00
|
|
|
cpu_register_io_memory(IO_MEM_ROM >> IO_MEM_SHIFT, error_mem_read, unassigned_mem_write, NULL);
|
2004-06-03 16:01:43 +02:00
|
|
|
cpu_register_io_memory(IO_MEM_UNASSIGNED >> IO_MEM_SHIFT, unassigned_mem_read, unassigned_mem_write, NULL);
|
2005-08-21 11:26:42 +02:00
|
|
|
cpu_register_io_memory(IO_MEM_NOTDIRTY >> IO_MEM_SHIFT, error_mem_read, notdirty_mem_write, NULL);
|
2004-02-06 20:46:14 +01:00
|
|
|
io_mem_nb = 5;
|
|
|
|
|
2008-06-09 02:20:13 +02:00
|
|
|
io_mem_watch = cpu_register_io_memory(0, watch_mem_read,
|
2007-03-17 00:58:11 +01:00
|
|
|
watch_mem_write, NULL);
|
2004-02-06 20:46:14 +01:00
|
|
|
/* alloc dirty bits array */
|
2005-02-10 23:00:27 +01:00
|
|
|
phys_ram_dirty = qemu_vmalloc(phys_ram_size >> TARGET_PAGE_BITS);
|
2005-08-21 11:26:42 +02:00
|
|
|
memset(phys_ram_dirty, 0xff, phys_ram_size >> TARGET_PAGE_BITS);
|
2003-08-10 23:47:01 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* mem_read and mem_write are arrays of functions containing the
|
|
|
|
function to access byte (index 0), word (index 1) and dword (index
|
2008-01-02 20:45:26 +01:00
|
|
|
2). Functions can be omitted with a NULL function pointer. The
|
|
|
|
registered functions may be modified dynamically later.
|
|
|
|
If io_index is non zero, the corresponding io zone is
|
2008-01-01 17:57:19 +01:00
|
|
|
modified. If it is zero, a new io zone is allocated. The return
|
|
|
|
value can be used with cpu_register_physical_memory(). (-1) is
|
|
|
|
returned if error. */
|
2003-08-10 23:47:01 +02:00
|
|
|
int cpu_register_io_memory(int io_index,
|
|
|
|
CPUReadMemoryFunc **mem_read,
|
2004-06-03 16:01:43 +02:00
|
|
|
CPUWriteMemoryFunc **mem_write,
|
|
|
|
void *opaque)
|
2003-08-10 23:47:01 +02:00
|
|
|
{
|
2008-01-01 17:57:19 +01:00
|
|
|
int i, subwidth = 0;
|
2003-08-10 23:47:01 +02:00
|
|
|
|
|
|
|
if (io_index <= 0) {
|
2005-11-26 11:38:39 +01:00
|
|
|
if (io_mem_nb >= IO_MEM_NB_ENTRIES)
|
2003-08-10 23:47:01 +02:00
|
|
|
return -1;
|
|
|
|
io_index = io_mem_nb++;
|
|
|
|
} else {
|
|
|
|
if (io_index >= IO_MEM_NB_ENTRIES)
|
|
|
|
return -1;
|
|
|
|
}
|
2005-11-26 11:38:39 +01:00
|
|
|
|
2003-08-10 23:47:01 +02:00
|
|
|
for(i = 0;i < 3; i++) {
|
2008-01-01 17:57:19 +01:00
|
|
|
if (!mem_read[i] || !mem_write[i])
|
|
|
|
subwidth = IO_MEM_SUBWIDTH;
|
2003-08-10 23:47:01 +02:00
|
|
|
io_mem_read[io_index][i] = mem_read[i];
|
|
|
|
io_mem_write[io_index][i] = mem_write[i];
|
|
|
|
}
|
2004-06-03 16:01:43 +02:00
|
|
|
io_mem_opaque[io_index] = opaque;
|
2008-01-01 17:57:19 +01:00
|
|
|
return (io_index << IO_MEM_SHIFT) | subwidth;
|
2003-08-10 23:47:01 +02:00
|
|
|
}
|
2003-10-27 22:22:23 +01:00
|
|
|
|
2004-10-10 17:14:20 +02:00
|
|
|
CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index)
|
|
|
|
{
|
|
|
|
return io_mem_write[io_index >> IO_MEM_SHIFT];
|
|
|
|
}
|
|
|
|
|
|
|
|
CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index)
|
|
|
|
{
|
|
|
|
return io_mem_read[io_index >> IO_MEM_SHIFT];
|
|
|
|
}
|
|
|
|
|
2008-06-08 03:09:01 +02:00
|
|
|
#endif /* !defined(CONFIG_USER_ONLY) */
|
|
|
|
|
2004-01-24 16:23:36 +01:00
|
|
|
/* physical memory access (slow version, mainly for debug) */
|
|
|
|
#if defined(CONFIG_USER_ONLY)
|
2007-09-16 23:08:06 +02:00
|
|
|
void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
|
2004-01-24 16:23:36 +01:00
|
|
|
int len, int is_write)
|
|
|
|
{
|
|
|
|
int l, flags;
|
|
|
|
target_ulong page;
|
2006-03-25 20:31:22 +01:00
|
|
|
void * p;
|
2004-01-24 16:23:36 +01:00
|
|
|
|
|
|
|
while (len > 0) {
|
|
|
|
page = addr & TARGET_PAGE_MASK;
|
|
|
|
l = (page + TARGET_PAGE_SIZE) - addr;
|
|
|
|
if (l > len)
|
|
|
|
l = len;
|
|
|
|
flags = page_get_flags(page);
|
|
|
|
if (!(flags & PAGE_VALID))
|
|
|
|
return;
|
|
|
|
if (is_write) {
|
|
|
|
if (!(flags & PAGE_WRITE))
|
|
|
|
return;
|
2007-11-11 15:26:47 +01:00
|
|
|
/* XXX: this code should not depend on lock_user */
|
2008-04-28 01:53:45 +02:00
|
|
|
if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
|
2007-11-11 15:26:47 +01:00
|
|
|
/* FIXME - should this return an error rather than just fail? */
|
|
|
|
return;
|
2008-04-28 01:53:45 +02:00
|
|
|
memcpy(p, buf, l);
|
|
|
|
unlock_user(p, addr, l);
|
2004-01-24 16:23:36 +01:00
|
|
|
} else {
|
|
|
|
if (!(flags & PAGE_READ))
|
|
|
|
return;
|
2007-11-11 15:26:47 +01:00
|
|
|
/* XXX: this code should not depend on lock_user */
|
2008-04-28 01:53:45 +02:00
|
|
|
if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
|
2007-11-11 15:26:47 +01:00
|
|
|
/* FIXME - should this return an error rather than just fail? */
|
|
|
|
return;
|
2008-04-28 01:53:45 +02:00
|
|
|
memcpy(buf, p, l);
|
2008-04-28 10:54:59 +02:00
|
|
|
unlock_user(p, addr, 0);
|
2004-01-24 16:23:36 +01:00
|
|
|
}
|
|
|
|
len -= l;
|
|
|
|
buf += l;
|
|
|
|
addr += l;
|
|
|
|
}
|
|
|
|
}
|
2005-01-28 23:37:22 +01:00
|
|
|
|
2004-01-24 16:23:36 +01:00
|
|
|
#else
|
2007-09-16 23:08:06 +02:00
|
|
|
void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
|
2004-01-24 16:23:36 +01:00
|
|
|
int len, int is_write)
|
|
|
|
{
|
|
|
|
int l, io_index;
|
|
|
|
uint8_t *ptr;
|
|
|
|
uint32_t val;
|
2004-04-25 23:28:44 +02:00
|
|
|
target_phys_addr_t page;
|
|
|
|
unsigned long pd;
|
2004-05-21 16:52:29 +02:00
|
|
|
PhysPageDesc *p;
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2004-01-24 16:23:36 +01:00
|
|
|
while (len > 0) {
|
|
|
|
page = addr & TARGET_PAGE_MASK;
|
|
|
|
l = (page + TARGET_PAGE_SIZE) - addr;
|
|
|
|
if (l > len)
|
|
|
|
l = len;
|
2004-05-21 16:52:29 +02:00
|
|
|
p = phys_page_find(page >> TARGET_PAGE_BITS);
|
2004-01-24 16:23:36 +01:00
|
|
|
if (!p) {
|
|
|
|
pd = IO_MEM_UNASSIGNED;
|
|
|
|
} else {
|
|
|
|
pd = p->phys_offset;
|
|
|
|
}
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2004-01-24 16:23:36 +01:00
|
|
|
if (is_write) {
|
2005-08-21 11:26:42 +02:00
|
|
|
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
|
2004-01-24 16:23:36 +01:00
|
|
|
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
|
2005-11-22 00:25:50 +01:00
|
|
|
/* XXX: could force cpu_single_env to NULL to avoid
|
|
|
|
potential bugs */
|
2004-01-24 16:23:36 +01:00
|
|
|
if (l >= 4 && ((addr & 3) == 0)) {
|
2005-09-03 12:49:04 +02:00
|
|
|
/* 32 bit write access */
|
2005-01-04 00:35:10 +01:00
|
|
|
val = ldl_p(buf);
|
2004-06-03 16:01:43 +02:00
|
|
|
io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
|
2004-01-24 16:23:36 +01:00
|
|
|
l = 4;
|
|
|
|
} else if (l >= 2 && ((addr & 1) == 0)) {
|
2005-09-03 12:49:04 +02:00
|
|
|
/* 16 bit write access */
|
2005-01-04 00:35:10 +01:00
|
|
|
val = lduw_p(buf);
|
2004-06-03 16:01:43 +02:00
|
|
|
io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val);
|
2004-01-24 16:23:36 +01:00
|
|
|
l = 2;
|
|
|
|
} else {
|
2005-09-03 12:49:04 +02:00
|
|
|
/* 8 bit write access */
|
2005-01-04 00:35:10 +01:00
|
|
|
val = ldub_p(buf);
|
2004-06-03 16:01:43 +02:00
|
|
|
io_mem_write[io_index][0](io_mem_opaque[io_index], addr, val);
|
2004-01-24 16:23:36 +01:00
|
|
|
l = 1;
|
|
|
|
}
|
|
|
|
} else {
|
2004-02-26 00:24:04 +01:00
|
|
|
unsigned long addr1;
|
|
|
|
addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
|
2004-01-24 16:23:36 +01:00
|
|
|
/* RAM case */
|
2004-02-26 00:24:04 +01:00
|
|
|
ptr = phys_ram_base + addr1;
|
2004-01-24 16:23:36 +01:00
|
|
|
memcpy(ptr, buf, l);
|
2005-08-21 11:26:42 +02:00
|
|
|
if (!cpu_physical_memory_is_dirty(addr1)) {
|
|
|
|
/* invalidate code */
|
|
|
|
tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
|
|
|
|
/* set dirty bit */
|
2007-09-16 23:08:06 +02:00
|
|
|
phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
|
2005-08-21 21:12:28 +02:00
|
|
|
(0xff & ~CODE_DIRTY_FLAG);
|
2005-08-21 11:26:42 +02:00
|
|
|
}
|
2004-01-24 16:23:36 +01:00
|
|
|
}
|
|
|
|
} else {
|
2007-09-16 23:08:06 +02:00
|
|
|
if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
|
2006-06-25 23:54:59 +02:00
|
|
|
!(pd & IO_MEM_ROMD)) {
|
2004-01-24 16:23:36 +01:00
|
|
|
/* I/O case */
|
|
|
|
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
|
|
|
|
if (l >= 4 && ((addr & 3) == 0)) {
|
|
|
|
/* 32 bit read access */
|
2004-06-03 16:01:43 +02:00
|
|
|
val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
|
2005-01-04 00:35:10 +01:00
|
|
|
stl_p(buf, val);
|
2004-01-24 16:23:36 +01:00
|
|
|
l = 4;
|
|
|
|
} else if (l >= 2 && ((addr & 1) == 0)) {
|
|
|
|
/* 16 bit read access */
|
2004-06-03 16:01:43 +02:00
|
|
|
val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr);
|
2005-01-04 00:35:10 +01:00
|
|
|
stw_p(buf, val);
|
2004-01-24 16:23:36 +01:00
|
|
|
l = 2;
|
|
|
|
} else {
|
2005-09-03 12:49:04 +02:00
|
|
|
/* 8 bit read access */
|
2004-06-03 16:01:43 +02:00
|
|
|
val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr);
|
2005-01-04 00:35:10 +01:00
|
|
|
stb_p(buf, val);
|
2004-01-24 16:23:36 +01:00
|
|
|
l = 1;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* RAM case */
|
2007-09-16 23:08:06 +02:00
|
|
|
ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
|
2004-01-24 16:23:36 +01:00
|
|
|
(addr & ~TARGET_PAGE_MASK);
|
|
|
|
memcpy(buf, ptr, l);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
len -= l;
|
|
|
|
buf += l;
|
|
|
|
addr += l;
|
|
|
|
}
|
|
|
|
}
|
2005-01-28 23:37:22 +01:00
|
|
|
|
2006-04-23 19:14:48 +02:00
|
|
|
/* used for ROM loading : can write in RAM and ROM */
|
2007-09-16 23:08:06 +02:00
|
|
|
void cpu_physical_memory_write_rom(target_phys_addr_t addr,
|
2006-04-23 19:14:48 +02:00
|
|
|
const uint8_t *buf, int len)
|
|
|
|
{
|
|
|
|
int l;
|
|
|
|
uint8_t *ptr;
|
|
|
|
target_phys_addr_t page;
|
|
|
|
unsigned long pd;
|
|
|
|
PhysPageDesc *p;
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2006-04-23 19:14:48 +02:00
|
|
|
while (len > 0) {
|
|
|
|
page = addr & TARGET_PAGE_MASK;
|
|
|
|
l = (page + TARGET_PAGE_SIZE) - addr;
|
|
|
|
if (l > len)
|
|
|
|
l = len;
|
|
|
|
p = phys_page_find(page >> TARGET_PAGE_BITS);
|
|
|
|
if (!p) {
|
|
|
|
pd = IO_MEM_UNASSIGNED;
|
|
|
|
} else {
|
|
|
|
pd = p->phys_offset;
|
|
|
|
}
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2006-04-23 19:14:48 +02:00
|
|
|
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM &&
|
2006-06-25 23:54:59 +02:00
|
|
|
(pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM &&
|
|
|
|
!(pd & IO_MEM_ROMD)) {
|
2006-04-23 19:14:48 +02:00
|
|
|
/* do nothing */
|
|
|
|
} else {
|
|
|
|
unsigned long addr1;
|
|
|
|
addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
|
|
|
|
/* ROM/RAM case */
|
|
|
|
ptr = phys_ram_base + addr1;
|
|
|
|
memcpy(ptr, buf, l);
|
|
|
|
}
|
|
|
|
len -= l;
|
|
|
|
buf += l;
|
|
|
|
addr += l;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-01-28 23:37:22 +01:00
|
|
|
/* warning: addr must be aligned */
|
|
|
|
uint32_t ldl_phys(target_phys_addr_t addr)
|
|
|
|
{
|
|
|
|
int io_index;
|
|
|
|
uint8_t *ptr;
|
|
|
|
uint32_t val;
|
|
|
|
unsigned long pd;
|
|
|
|
PhysPageDesc *p;
|
|
|
|
|
|
|
|
p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
|
|
|
if (!p) {
|
|
|
|
pd = IO_MEM_UNASSIGNED;
|
|
|
|
} else {
|
|
|
|
pd = p->phys_offset;
|
|
|
|
}
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2007-09-16 23:08:06 +02:00
|
|
|
if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
|
2006-06-25 23:54:59 +02:00
|
|
|
!(pd & IO_MEM_ROMD)) {
|
2005-01-28 23:37:22 +01:00
|
|
|
/* I/O case */
|
|
|
|
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
|
|
|
|
val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
|
|
|
|
} else {
|
|
|
|
/* RAM case */
|
2007-09-16 23:08:06 +02:00
|
|
|
ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
|
2005-01-28 23:37:22 +01:00
|
|
|
(addr & ~TARGET_PAGE_MASK);
|
|
|
|
val = ldl_p(ptr);
|
|
|
|
}
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2005-11-28 22:19:04 +01:00
|
|
|
/* warning: addr must be aligned */
|
|
|
|
uint64_t ldq_phys(target_phys_addr_t addr)
|
|
|
|
{
|
|
|
|
int io_index;
|
|
|
|
uint8_t *ptr;
|
|
|
|
uint64_t val;
|
|
|
|
unsigned long pd;
|
|
|
|
PhysPageDesc *p;
|
|
|
|
|
|
|
|
p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
|
|
|
if (!p) {
|
|
|
|
pd = IO_MEM_UNASSIGNED;
|
|
|
|
} else {
|
|
|
|
pd = p->phys_offset;
|
|
|
|
}
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2006-06-25 23:54:59 +02:00
|
|
|
if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
|
|
|
|
!(pd & IO_MEM_ROMD)) {
|
2005-11-28 22:19:04 +01:00
|
|
|
/* I/O case */
|
|
|
|
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
|
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
|
|
val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32;
|
|
|
|
val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4);
|
|
|
|
#else
|
|
|
|
val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
|
|
|
|
val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32;
|
|
|
|
#endif
|
|
|
|
} else {
|
|
|
|
/* RAM case */
|
2007-09-16 23:08:06 +02:00
|
|
|
ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
|
2005-11-28 22:19:04 +01:00
|
|
|
(addr & ~TARGET_PAGE_MASK);
|
|
|
|
val = ldq_p(ptr);
|
|
|
|
}
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2005-10-30 21:48:42 +01:00
|
|
|
/* XXX: optimize */
|
|
|
|
uint32_t ldub_phys(target_phys_addr_t addr)
|
|
|
|
{
|
|
|
|
uint8_t val;
|
|
|
|
cpu_physical_memory_read(addr, &val, 1);
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* XXX: optimize */
|
|
|
|
uint32_t lduw_phys(target_phys_addr_t addr)
|
|
|
|
{
|
|
|
|
uint16_t val;
|
|
|
|
cpu_physical_memory_read(addr, (uint8_t *)&val, 2);
|
|
|
|
return tswap16(val);
|
|
|
|
}
|
|
|
|
|
2005-01-28 23:37:22 +01:00
|
|
|
/* warning: addr must be aligned. The ram page is not masked as dirty
|
|
|
|
and the code inside is not invalidated. It is useful if the dirty
|
|
|
|
bits are used to track modified PTEs */
|
|
|
|
void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
|
|
|
|
{
|
|
|
|
int io_index;
|
|
|
|
uint8_t *ptr;
|
|
|
|
unsigned long pd;
|
|
|
|
PhysPageDesc *p;
|
|
|
|
|
|
|
|
p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
|
|
|
if (!p) {
|
|
|
|
pd = IO_MEM_UNASSIGNED;
|
|
|
|
} else {
|
|
|
|
pd = p->phys_offset;
|
|
|
|
}
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2005-08-21 11:26:42 +02:00
|
|
|
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
|
2005-01-28 23:37:22 +01:00
|
|
|
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
|
|
|
|
io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
|
|
|
|
} else {
|
2008-10-06 16:02:03 +02:00
|
|
|
unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
|
|
|
|
ptr = phys_ram_base + addr1;
|
2005-01-28 23:37:22 +01:00
|
|
|
stl_p(ptr, val);
|
2008-10-06 16:02:03 +02:00
|
|
|
|
|
|
|
if (unlikely(in_migration)) {
|
|
|
|
if (!cpu_physical_memory_is_dirty(addr1)) {
|
|
|
|
/* invalidate code */
|
|
|
|
tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
|
|
|
|
/* set dirty bit */
|
|
|
|
phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
|
|
|
|
(0xff & ~CODE_DIRTY_FLAG);
|
|
|
|
}
|
|
|
|
}
|
2005-01-28 23:37:22 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-04-04 09:55:12 +02:00
|
|
|
void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
|
|
|
|
{
|
|
|
|
int io_index;
|
|
|
|
uint8_t *ptr;
|
|
|
|
unsigned long pd;
|
|
|
|
PhysPageDesc *p;
|
|
|
|
|
|
|
|
p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
|
|
|
if (!p) {
|
|
|
|
pd = IO_MEM_UNASSIGNED;
|
|
|
|
} else {
|
|
|
|
pd = p->phys_offset;
|
|
|
|
}
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2007-04-04 09:55:12 +02:00
|
|
|
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
|
|
|
|
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
|
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
|
|
io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32);
|
|
|
|
io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val);
|
|
|
|
#else
|
|
|
|
io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
|
|
|
|
io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32);
|
|
|
|
#endif
|
|
|
|
} else {
|
2007-09-16 23:08:06 +02:00
|
|
|
ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
|
2007-04-04 09:55:12 +02:00
|
|
|
(addr & ~TARGET_PAGE_MASK);
|
|
|
|
stq_p(ptr, val);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-01-28 23:37:22 +01:00
|
|
|
/* warning: addr must be aligned */
|
|
|
|
void stl_phys(target_phys_addr_t addr, uint32_t val)
|
|
|
|
{
|
|
|
|
int io_index;
|
|
|
|
uint8_t *ptr;
|
|
|
|
unsigned long pd;
|
|
|
|
PhysPageDesc *p;
|
|
|
|
|
|
|
|
p = phys_page_find(addr >> TARGET_PAGE_BITS);
|
|
|
|
if (!p) {
|
|
|
|
pd = IO_MEM_UNASSIGNED;
|
|
|
|
} else {
|
|
|
|
pd = p->phys_offset;
|
|
|
|
}
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2005-08-21 11:26:42 +02:00
|
|
|
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
|
2005-01-28 23:37:22 +01:00
|
|
|
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
|
|
|
|
io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
|
|
|
|
} else {
|
|
|
|
unsigned long addr1;
|
|
|
|
addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
|
|
|
|
/* RAM case */
|
|
|
|
ptr = phys_ram_base + addr1;
|
|
|
|
stl_p(ptr, val);
|
2005-08-21 11:26:42 +02:00
|
|
|
if (!cpu_physical_memory_is_dirty(addr1)) {
|
|
|
|
/* invalidate code */
|
|
|
|
tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
|
|
|
|
/* set dirty bit */
|
2005-08-21 21:12:28 +02:00
|
|
|
phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
|
|
|
|
(0xff & ~CODE_DIRTY_FLAG);
|
2005-08-21 11:26:42 +02:00
|
|
|
}
|
2005-01-28 23:37:22 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-10-30 21:48:42 +01:00
|
|
|
/* XXX: optimize */
|
|
|
|
void stb_phys(target_phys_addr_t addr, uint32_t val)
|
|
|
|
{
|
|
|
|
uint8_t v = val;
|
|
|
|
cpu_physical_memory_write(addr, &v, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* XXX: optimize */
|
|
|
|
void stw_phys(target_phys_addr_t addr, uint32_t val)
|
|
|
|
{
|
|
|
|
uint16_t v = tswap16(val);
|
|
|
|
cpu_physical_memory_write(addr, (const uint8_t *)&v, 2);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* XXX: optimize */
|
|
|
|
void stq_phys(target_phys_addr_t addr, uint64_t val)
|
|
|
|
{
|
|
|
|
val = tswap64(val);
|
|
|
|
cpu_physical_memory_write(addr, (const uint8_t *)&val, 8);
|
|
|
|
}
|
|
|
|
|
2004-01-24 16:23:36 +01:00
|
|
|
#endif
|
|
|
|
|
|
|
|
/* virtual memory access for debug */
|
2007-09-16 23:08:06 +02:00
|
|
|
int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
|
2004-02-26 00:24:04 +01:00
|
|
|
uint8_t *buf, int len, int is_write)
|
2004-01-24 16:23:36 +01:00
|
|
|
{
|
|
|
|
int l;
|
2007-04-07 13:21:28 +02:00
|
|
|
target_phys_addr_t phys_addr;
|
|
|
|
target_ulong page;
|
2004-01-24 16:23:36 +01:00
|
|
|
|
|
|
|
while (len > 0) {
|
|
|
|
page = addr & TARGET_PAGE_MASK;
|
|
|
|
phys_addr = cpu_get_phys_page_debug(env, page);
|
|
|
|
/* if no physical page mapped, return an error */
|
|
|
|
if (phys_addr == -1)
|
|
|
|
return -1;
|
|
|
|
l = (page + TARGET_PAGE_SIZE) - addr;
|
|
|
|
if (l > len)
|
|
|
|
l = len;
|
2007-09-16 23:08:06 +02:00
|
|
|
cpu_physical_memory_rw(phys_addr + (addr & ~TARGET_PAGE_MASK),
|
2004-02-26 00:24:04 +01:00
|
|
|
buf, l, is_write);
|
2004-01-24 16:23:36 +01:00
|
|
|
len -= l;
|
|
|
|
buf += l;
|
|
|
|
addr += l;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-06-29 03:03:05 +02:00
|
|
|
/* in deterministic execution mode, instructions doing device I/Os
|
|
|
|
must be at the end of the TB */
|
|
|
|
void cpu_io_recompile(CPUState *env, void *retaddr)
|
|
|
|
{
|
|
|
|
TranslationBlock *tb;
|
|
|
|
uint32_t n, cflags;
|
|
|
|
target_ulong pc, cs_base;
|
|
|
|
uint64_t flags;
|
|
|
|
|
|
|
|
tb = tb_find_pc((unsigned long)retaddr);
|
|
|
|
if (!tb) {
|
|
|
|
cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p",
|
|
|
|
retaddr);
|
|
|
|
}
|
|
|
|
n = env->icount_decr.u16.low + tb->icount;
|
|
|
|
cpu_restore_state(tb, env, (unsigned long)retaddr, NULL);
|
|
|
|
/* Calculate how many instructions had been executed before the fault
|
2008-06-30 19:22:19 +02:00
|
|
|
occurred. */
|
2008-06-29 03:03:05 +02:00
|
|
|
n = n - env->icount_decr.u16.low;
|
|
|
|
/* Generate a new TB ending on the I/O insn. */
|
|
|
|
n++;
|
|
|
|
/* On MIPS and SH, delay slot instructions can only be restarted if
|
|
|
|
they were already the first instruction in the TB. If this is not
|
2008-06-30 19:22:19 +02:00
|
|
|
the first instruction in a TB then re-execute the preceding
|
2008-06-29 03:03:05 +02:00
|
|
|
branch. */
|
|
|
|
#if defined(TARGET_MIPS)
|
|
|
|
if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) {
|
|
|
|
env->active_tc.PC -= 4;
|
|
|
|
env->icount_decr.u16.low++;
|
|
|
|
env->hflags &= ~MIPS_HFLAG_BMASK;
|
|
|
|
}
|
|
|
|
#elif defined(TARGET_SH4)
|
|
|
|
if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
|
|
|
|
&& n > 1) {
|
|
|
|
env->pc -= 2;
|
|
|
|
env->icount_decr.u16.low++;
|
|
|
|
env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
/* This should never happen. */
|
|
|
|
if (n > CF_COUNT_MASK)
|
|
|
|
cpu_abort(env, "TB too big during recompile");
|
|
|
|
|
|
|
|
cflags = n | CF_LAST_IO;
|
|
|
|
pc = tb->pc;
|
|
|
|
cs_base = tb->cs_base;
|
|
|
|
flags = tb->flags;
|
|
|
|
tb_phys_invalidate(tb, -1);
|
|
|
|
/* FIXME: In theory this could raise an exception. In practice
|
|
|
|
we have already translated the block once so it's probably ok. */
|
|
|
|
tb_gen_code(env, pc, cs_base, flags, cflags);
|
2008-06-30 19:22:19 +02:00
|
|
|
/* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not
|
2008-06-29 03:03:05 +02:00
|
|
|
the first in the TB) then we end up generating a whole new TB and
|
|
|
|
repeating the fault, which is horribly inefficient.
|
|
|
|
Better would be to execute just this insn uncached, or generate a
|
|
|
|
second new TB. */
|
|
|
|
cpu_resume_from_signal(env, NULL);
|
|
|
|
}
|
|
|
|
|
2005-01-26 23:00:47 +01:00
|
|
|
void dump_exec_info(FILE *f,
|
|
|
|
int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
|
|
|
|
{
|
|
|
|
int i, target_code_size, max_target_code_size;
|
|
|
|
int direct_jmp_count, direct_jmp2_count, cross_page;
|
|
|
|
TranslationBlock *tb;
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2005-01-26 23:00:47 +01:00
|
|
|
target_code_size = 0;
|
|
|
|
max_target_code_size = 0;
|
|
|
|
cross_page = 0;
|
|
|
|
direct_jmp_count = 0;
|
|
|
|
direct_jmp2_count = 0;
|
|
|
|
for(i = 0; i < nb_tbs; i++) {
|
|
|
|
tb = &tbs[i];
|
|
|
|
target_code_size += tb->size;
|
|
|
|
if (tb->size > max_target_code_size)
|
|
|
|
max_target_code_size = tb->size;
|
|
|
|
if (tb->page_addr[1] != -1)
|
|
|
|
cross_page++;
|
|
|
|
if (tb->tb_next_offset[0] != 0xffff) {
|
|
|
|
direct_jmp_count++;
|
|
|
|
if (tb->tb_next_offset[1] != 0xffff) {
|
|
|
|
direct_jmp2_count++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/* XXX: avoid using doubles ? */
|
2008-02-01 11:50:11 +01:00
|
|
|
cpu_fprintf(f, "Translation buffer state:\n");
|
2008-05-28 14:30:31 +02:00
|
|
|
cpu_fprintf(f, "gen code size %ld/%ld\n",
|
|
|
|
code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size);
|
|
|
|
cpu_fprintf(f, "TB count %d/%d\n",
|
|
|
|
nb_tbs, code_gen_max_blocks);
|
2007-09-16 23:08:06 +02:00
|
|
|
cpu_fprintf(f, "TB avg target size %d max=%d bytes\n",
|
2005-01-26 23:00:47 +01:00
|
|
|
nb_tbs ? target_code_size / nb_tbs : 0,
|
|
|
|
max_target_code_size);
|
2007-09-16 23:08:06 +02:00
|
|
|
cpu_fprintf(f, "TB avg host size %d bytes (expansion ratio: %0.1f)\n",
|
2005-01-26 23:00:47 +01:00
|
|
|
nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0,
|
|
|
|
target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0);
|
2007-09-16 23:08:06 +02:00
|
|
|
cpu_fprintf(f, "cross page TB count %d (%d%%)\n",
|
|
|
|
cross_page,
|
2005-01-26 23:00:47 +01:00
|
|
|
nb_tbs ? (cross_page * 100) / nb_tbs : 0);
|
|
|
|
cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n",
|
2007-09-16 23:08:06 +02:00
|
|
|
direct_jmp_count,
|
2005-01-26 23:00:47 +01:00
|
|
|
nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0,
|
|
|
|
direct_jmp2_count,
|
|
|
|
nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0);
|
2008-02-01 11:50:11 +01:00
|
|
|
cpu_fprintf(f, "\nStatistics:\n");
|
2005-01-26 23:00:47 +01:00
|
|
|
cpu_fprintf(f, "TB flush count %d\n", tb_flush_count);
|
|
|
|
cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count);
|
|
|
|
cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count);
|
2008-05-23 11:57:34 +02:00
|
|
|
tcg_dump_info(f, cpu_fprintf);
|
2005-01-26 23:00:47 +01:00
|
|
|
}
|
|
|
|
|
2007-09-16 23:08:06 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2003-10-27 22:22:23 +01:00
|
|
|
|
|
|
|
#define MMUSUFFIX _cmmu
|
|
|
|
#define GETPC() NULL
|
|
|
|
#define env cpu_single_env
|
2004-10-03 17:07:13 +02:00
|
|
|
#define SOFTMMU_CODE_ACCESS
|
2003-10-27 22:22:23 +01:00
|
|
|
|
|
|
|
#define SHIFT 0
|
|
|
|
#include "softmmu_template.h"
|
|
|
|
|
|
|
|
#define SHIFT 1
|
|
|
|
#include "softmmu_template.h"
|
|
|
|
|
|
|
|
#define SHIFT 2
|
|
|
|
#include "softmmu_template.h"
|
|
|
|
|
|
|
|
#define SHIFT 3
|
|
|
|
#include "softmmu_template.h"
|
|
|
|
|
|
|
|
#undef env
|
|
|
|
|
|
|
|
#endif
|