2012-08-01 12:52:36 +02:00
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/*
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* QEMU model of the Xilinx Zynq SPI controller
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*
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* Copyright (c) 2012 Peter A. G. Crosthwaite
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2016-01-26 19:17:05 +01:00
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#include "qemu/osdep.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/sysbus.h"
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2012-12-17 18:20:04 +01:00
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#include "sysemu/sysemu.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/ptimer.h"
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2012-12-17 18:20:00 +01:00
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#include "qemu/log.h"
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#include "qemu/bitops.h"
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2016-01-21 15:15:03 +01:00
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#include "hw/ssi/xilinx_spips.h"
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2017-08-11 09:54:12 +02:00
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#include "qapi/error.h"
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2017-12-13 18:59:21 +01:00
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#include "hw/register.h"
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2017-08-11 09:54:12 +02:00
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#include "migration/blocker.h"
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2012-08-01 12:52:36 +02:00
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2013-06-03 18:17:43 +02:00
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#ifndef XILINX_SPIPS_ERR_DEBUG
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#define XILINX_SPIPS_ERR_DEBUG 0
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2012-08-01 12:52:36 +02:00
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#endif
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2013-06-03 18:17:43 +02:00
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#define DB_PRINT_L(level, ...) do { \
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if (XILINX_SPIPS_ERR_DEBUG > (level)) { \
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fprintf(stderr, ": %s: ", __func__); \
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fprintf(stderr, ## __VA_ARGS__); \
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} \
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} while (0);
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2012-08-01 12:52:36 +02:00
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/* config register */
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#define R_CONFIG (0x00 / 4)
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2014-03-10 15:56:30 +01:00
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#define IFMODE (1U << 31)
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2017-12-13 18:59:21 +01:00
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#define R_CONFIG_ENDIAN (1 << 26)
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2012-08-01 12:52:36 +02:00
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#define MODEFAIL_GEN_EN (1 << 17)
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#define MAN_START_COM (1 << 16)
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#define MAN_START_EN (1 << 15)
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#define MANUAL_CS (1 << 14)
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#define CS (0xF << 10)
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#define CS_SHIFT (10)
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#define PERI_SEL (1 << 9)
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#define REF_CLK (1 << 8)
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#define FIFO_WIDTH (3 << 6)
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#define BAUD_RATE_DIV (7 << 3)
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#define CLK_PH (1 << 2)
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#define CLK_POL (1 << 1)
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#define MODE_SEL (1 << 0)
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2013-06-03 18:17:43 +02:00
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#define R_CONFIG_RSVD (0x7bf40000)
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2012-08-01 12:52:36 +02:00
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/* interrupt mechanism */
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#define R_INTR_STATUS (0x04 / 4)
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#define R_INTR_EN (0x08 / 4)
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#define R_INTR_DIS (0x0C / 4)
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#define R_INTR_MASK (0x10 / 4)
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#define IXR_TX_FIFO_UNDERFLOW (1 << 6)
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#define IXR_RX_FIFO_FULL (1 << 5)
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#define IXR_RX_FIFO_NOT_EMPTY (1 << 4)
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#define IXR_TX_FIFO_FULL (1 << 3)
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#define IXR_TX_FIFO_NOT_FULL (1 << 2)
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#define IXR_TX_FIFO_MODE_FAIL (1 << 1)
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#define IXR_RX_FIFO_OVERFLOW (1 << 0)
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#define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1)
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#define R_EN (0x14 / 4)
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#define R_DELAY (0x18 / 4)
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#define R_TX_DATA (0x1C / 4)
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#define R_RX_DATA (0x20 / 4)
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#define R_SLAVE_IDLE_COUNT (0x24 / 4)
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#define R_TX_THRES (0x28 / 4)
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#define R_RX_THRES (0x2C / 4)
|
2012-10-15 06:37:04 +02:00
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#define R_TXD1 (0x80 / 4)
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#define R_TXD2 (0x84 / 4)
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#define R_TXD3 (0x88 / 4)
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#define R_LQSPI_CFG (0xa0 / 4)
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#define R_LQSPI_CFG_RESET 0x03A002EB
|
2014-03-10 15:56:30 +01:00
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#define LQSPI_CFG_LQ_MODE (1U << 31)
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2012-10-15 06:37:04 +02:00
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#define LQSPI_CFG_TWO_MEM (1 << 30)
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#define LQSPI_CFG_SEP_BUS (1 << 30)
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#define LQSPI_CFG_U_PAGE (1 << 28)
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#define LQSPI_CFG_MODE_EN (1 << 25)
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#define LQSPI_CFG_MODE_WIDTH 8
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#define LQSPI_CFG_MODE_SHIFT 16
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#define LQSPI_CFG_DUMMY_WIDTH 3
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#define LQSPI_CFG_DUMMY_SHIFT 8
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#define LQSPI_CFG_INST_CODE 0xFF
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2017-12-13 18:59:21 +01:00
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#define R_CMND (0xc0 / 4)
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#define R_CMND_RXFIFO_DRAIN (1 << 19)
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FIELD(CMND, PARTIAL_BYTE_LEN, 16, 3)
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#define R_CMND_EXT_ADD (1 << 15)
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FIELD(CMND, RX_DISCARD, 8, 7)
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FIELD(CMND, DUMMY_CYCLES, 2, 6)
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#define R_CMND_DMA_EN (1 << 1)
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#define R_CMND_PUSH_WAIT (1 << 0)
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2012-10-15 06:37:04 +02:00
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#define R_LQSPI_STS (0xA4 / 4)
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#define LQSPI_STS_WR_RECVD (1 << 1)
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2012-08-01 12:52:36 +02:00
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#define R_MOD_ID (0xFC / 4)
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/* size of TXRX FIFOs */
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#define RXFF_A 32
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#define TXFF_A 32
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2013-06-03 18:17:42 +02:00
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#define RXFF_A_Q (64 * 4)
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#define TXFF_A_Q (64 * 4)
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2012-10-15 06:37:04 +02:00
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/* 16MB per linear region */
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#define LQSPI_ADDRESS_BITS 24
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#define SNOOP_CHECKING 0xFF
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2017-12-13 18:59:21 +01:00
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#define SNOOP_ADDR 0xF0
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#define SNOOP_NONE 0xEE
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2012-10-15 06:37:04 +02:00
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#define SNOOP_STRIPING 0
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static inline int num_effective_busses(XilinxSPIPS *s)
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{
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2013-03-15 17:41:59 +01:00
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return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS &&
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s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1;
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2012-10-15 06:37:04 +02:00
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}
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2013-06-03 18:17:42 +02:00
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static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field)
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{
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return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS
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|| !fifo8_is_empty(&s->tx_fifo));
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}
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2012-08-01 12:52:36 +02:00
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static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
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{
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2012-10-15 06:37:04 +02:00
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int i, j;
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2012-08-01 12:52:36 +02:00
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bool found = false;
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int field = s->regs[R_CONFIG] >> CS_SHIFT;
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2012-10-15 06:37:04 +02:00
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for (i = 0; i < s->num_cs; i++) {
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for (j = 0; j < num_effective_busses(s); j++) {
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int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE);
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int cs_to_set = (j * s->num_cs + i + upage) %
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(s->num_cs * s->num_busses);
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2013-06-03 18:17:42 +02:00
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if (xilinx_spips_cs_is_set(s, i, field) && !found) {
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2013-06-03 18:17:43 +02:00
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DB_PRINT_L(0, "selecting slave %d\n", i);
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2012-10-15 06:37:04 +02:00
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qemu_set_irq(s->cs_lines[cs_to_set], 0);
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2017-12-13 18:59:21 +01:00
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if (s->cs_lines_state[cs_to_set]) {
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s->cs_lines_state[cs_to_set] = false;
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s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD);
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}
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2012-10-15 06:37:04 +02:00
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} else {
|
2013-06-03 18:17:43 +02:00
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DB_PRINT_L(0, "deselecting slave %d\n", i);
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2012-10-15 06:37:04 +02:00
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qemu_set_irq(s->cs_lines[cs_to_set], 1);
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2017-12-13 18:59:21 +01:00
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s->cs_lines_state[cs_to_set] = true;
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2012-10-15 06:37:04 +02:00
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}
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}
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2013-06-03 18:17:42 +02:00
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if (xilinx_spips_cs_is_set(s, i, field)) {
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2012-08-01 12:52:36 +02:00
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found = true;
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}
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2012-10-15 06:37:04 +02:00
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}
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if (!found) {
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s->snoop_state = SNOOP_CHECKING;
|
2017-12-13 18:59:21 +01:00
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s->cmd_dummies = 0;
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s->link_state = 1;
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s->link_state_next = 1;
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s->link_state_next_when = 0;
|
2013-06-03 18:17:43 +02:00
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DB_PRINT_L(1, "moving to snoop check state\n");
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2012-10-15 06:37:04 +02:00
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}
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2012-08-01 12:52:36 +02:00
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}
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static void xilinx_spips_update_ixr(XilinxSPIPS *s)
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{
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2013-06-03 18:17:41 +02:00
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if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) {
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return;
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}
|
2012-08-01 12:52:36 +02:00
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/* These are set/cleared as they occur */
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s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW |
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IXR_TX_FIFO_MODE_FAIL);
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/* these are pure functions of fifo state, set them here */
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s->regs[R_INTR_STATUS] |=
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(fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) |
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(s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) |
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(fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) |
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(s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0);
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/* drive external interrupt pin */
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int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] &
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IXR_ALL);
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if (new_irqline != s->irqline) {
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s->irqline = new_irqline;
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qemu_set_irq(s->irq, s->irqline);
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}
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}
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static void xilinx_spips_reset(DeviceState *d)
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{
|
2013-03-15 17:41:59 +01:00
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XilinxSPIPS *s = XILINX_SPIPS(d);
|
2012-08-01 12:52:36 +02:00
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int i;
|
2016-01-21 15:15:03 +01:00
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for (i = 0; i < XLNX_SPIPS_R_MAX; i++) {
|
2012-08-01 12:52:36 +02:00
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s->regs[i] = 0;
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}
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fifo8_reset(&s->rx_fifo);
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fifo8_reset(&s->rx_fifo);
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/* non zero resets */
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s->regs[R_CONFIG] |= MODEFAIL_GEN_EN;
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s->regs[R_SLAVE_IDLE_COUNT] = 0xFF;
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s->regs[R_TX_THRES] = 1;
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s->regs[R_RX_THRES] = 1;
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/* FIXME: move magic number definition somewhere sensible */
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s->regs[R_MOD_ID] = 0x01090106;
|
2012-10-15 06:37:04 +02:00
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s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET;
|
2017-12-13 18:59:21 +01:00
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s->link_state = 1;
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s->link_state_next = 1;
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s->link_state_next_when = 0;
|
2012-10-15 06:37:04 +02:00
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s->snoop_state = SNOOP_CHECKING;
|
2017-12-13 18:59:21 +01:00
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s->cmd_dummies = 0;
|
2012-08-01 12:52:36 +02:00
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xilinx_spips_update_ixr(s);
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xilinx_spips_update_cs_lines(s);
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}
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|
2017-12-13 18:59:21 +01:00
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/* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB)
|
2013-06-03 18:17:43 +02:00
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* column wise (from element 0 to N-1). num is the length of x, and dir
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* reverses the direction of the transform. Best illustrated by example:
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* Each digit in the below array is a single bit (num == 3):
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*
|
2017-12-13 18:59:21 +01:00
|
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|
* {{ 76543210, } ----- stripe (dir == false) -----> {{ 741gdaFC, }
|
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|
|
* { hgfedcba, } { 630fcHEB, }
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|
|
* { HGFEDCBA, }} <---- upstripe (dir == true) ----- { 52hebGDA, }}
|
2013-06-03 18:17:43 +02:00
|
|
|
*/
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|
|
static inline void stripe8(uint8_t *x, int num, bool dir)
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|
|
{
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|
uint8_t r[num];
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|
memset(r, 0, sizeof(uint8_t) * num);
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|
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int idx[2] = {0, 0};
|
2017-12-13 18:59:21 +01:00
|
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|
int bit[2] = {0, 7};
|
2013-06-03 18:17:43 +02:00
|
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|
int d = dir;
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|
for (idx[0] = 0; idx[0] < num; ++idx[0]) {
|
2017-12-13 18:59:21 +01:00
|
|
|
for (bit[0] = 7; bit[0] >= 0; bit[0]--) {
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|
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|
r[idx[!d]] |= x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0;
|
2013-06-03 18:17:43 +02:00
|
|
|
idx[1] = (idx[1] + 1) % num;
|
|
|
|
if (!idx[1]) {
|
2017-12-13 18:59:21 +01:00
|
|
|
bit[1]--;
|
2013-06-03 18:17:43 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
memcpy(x, r, sizeof(uint8_t) * num);
|
|
|
|
}
|
|
|
|
|
2017-12-13 18:59:21 +01:00
|
|
|
static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command)
|
|
|
|
{
|
|
|
|
if (!qs) {
|
|
|
|
/* The SPI device is not a QSPI device */
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (command) { /* check for dummies */
|
|
|
|
case READ: /* no dummy bytes/cycles */
|
|
|
|
case PP:
|
|
|
|
case DPP:
|
|
|
|
case QPP:
|
|
|
|
case READ_4:
|
|
|
|
case PP_4:
|
|
|
|
case QPP_4:
|
|
|
|
return 0;
|
|
|
|
case FAST_READ:
|
|
|
|
case DOR:
|
|
|
|
case QOR:
|
|
|
|
case DOR_4:
|
|
|
|
case QOR_4:
|
|
|
|
return 1;
|
|
|
|
case DIOR:
|
|
|
|
case FAST_READ_4:
|
|
|
|
case DIOR_4:
|
|
|
|
return 2;
|
|
|
|
case QIOR:
|
|
|
|
case QIOR_4:
|
|
|
|
return 5;
|
|
|
|
default:
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint8_t get_addr_length(XilinxSPIPS *s, uint8_t cmd)
|
|
|
|
{
|
|
|
|
switch (cmd) {
|
|
|
|
case PP_4:
|
|
|
|
case QPP_4:
|
|
|
|
case READ_4:
|
|
|
|
case QIOR_4:
|
|
|
|
case FAST_READ_4:
|
|
|
|
case DOR_4:
|
|
|
|
case QOR_4:
|
|
|
|
case DIOR_4:
|
|
|
|
return 4;
|
|
|
|
default:
|
|
|
|
return (s->regs[R_CMND] & R_CMND_EXT_ADD) ? 4 : 3;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-08-01 12:52:36 +02:00
|
|
|
static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
|
|
|
|
{
|
2013-06-03 18:17:43 +02:00
|
|
|
int debug_level = 0;
|
2017-12-13 18:59:21 +01:00
|
|
|
XilinxQSPIPS *q = (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s),
|
|
|
|
TYPE_XILINX_QSPIPS);
|
2013-06-03 18:17:43 +02:00
|
|
|
|
2012-08-01 12:52:36 +02:00
|
|
|
for (;;) {
|
2012-10-15 06:37:04 +02:00
|
|
|
int i;
|
|
|
|
uint8_t tx = 0;
|
2013-06-03 18:17:43 +02:00
|
|
|
uint8_t tx_rx[num_effective_busses(s)];
|
2017-12-13 18:59:21 +01:00
|
|
|
uint8_t dummy_cycles = 0;
|
|
|
|
uint8_t addr_length;
|
2012-10-15 06:37:04 +02:00
|
|
|
|
2013-06-03 18:17:43 +02:00
|
|
|
if (fifo8_is_empty(&s->tx_fifo)) {
|
|
|
|
if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
|
|
|
|
s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
|
|
|
|
}
|
|
|
|
xilinx_spips_update_ixr(s);
|
|
|
|
return;
|
|
|
|
} else if (s->snoop_state == SNOOP_STRIPING) {
|
|
|
|
for (i = 0; i < num_effective_busses(s); ++i) {
|
|
|
|
tx_rx[i] = fifo8_pop(&s->tx_fifo);
|
2012-10-15 06:37:04 +02:00
|
|
|
}
|
2013-06-03 18:17:43 +02:00
|
|
|
stripe8(tx_rx, num_effective_busses(s), false);
|
2017-12-13 18:59:21 +01:00
|
|
|
} else if (s->snoop_state >= SNOOP_ADDR) {
|
2013-06-03 18:17:43 +02:00
|
|
|
tx = fifo8_pop(&s->tx_fifo);
|
|
|
|
for (i = 0; i < num_effective_busses(s); ++i) {
|
|
|
|
tx_rx[i] = tx;
|
|
|
|
}
|
2017-12-13 18:59:21 +01:00
|
|
|
} else {
|
|
|
|
/* Extract a dummy byte and generate dummy cycles according to the
|
|
|
|
* link state */
|
|
|
|
tx = fifo8_pop(&s->tx_fifo);
|
|
|
|
dummy_cycles = 8 / s->link_state;
|
2013-06-03 18:17:43 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < num_effective_busses(s); ++i) {
|
2017-12-13 18:59:21 +01:00
|
|
|
int bus = num_effective_busses(s) - 1 - i;
|
2017-12-13 18:59:21 +01:00
|
|
|
if (dummy_cycles) {
|
|
|
|
int d;
|
|
|
|
for (d = 0; d < dummy_cycles; ++d) {
|
|
|
|
tx_rx[0] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[0]);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]);
|
|
|
|
tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]);
|
|
|
|
DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]);
|
|
|
|
}
|
2013-06-03 18:17:43 +02:00
|
|
|
}
|
|
|
|
|
2017-12-13 18:59:21 +01:00
|
|
|
if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) {
|
|
|
|
DB_PRINT_L(debug_level, "dircarding drained rx byte\n");
|
|
|
|
/* Do nothing */
|
|
|
|
} else if (s->rx_discard) {
|
|
|
|
DB_PRINT_L(debug_level, "dircarding discarded rx byte\n");
|
|
|
|
s->rx_discard -= 8 / s->link_state;
|
|
|
|
} else if (fifo8_is_full(&s->rx_fifo)) {
|
2013-06-03 18:17:43 +02:00
|
|
|
s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW;
|
2013-06-03 18:17:43 +02:00
|
|
|
DB_PRINT_L(0, "rx FIFO overflow");
|
2013-06-03 18:17:43 +02:00
|
|
|
} else if (s->snoop_state == SNOOP_STRIPING) {
|
|
|
|
stripe8(tx_rx, num_effective_busses(s), true);
|
|
|
|
for (i = 0; i < num_effective_busses(s); ++i) {
|
|
|
|
fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]);
|
2017-12-13 18:59:21 +01:00
|
|
|
DB_PRINT_L(debug_level, "pushing striped rx byte\n");
|
2012-10-15 06:37:04 +02:00
|
|
|
}
|
2013-06-03 18:17:43 +02:00
|
|
|
} else {
|
2017-12-13 18:59:21 +01:00
|
|
|
DB_PRINT_L(debug_level, "pushing unstriped rx byte\n");
|
2013-06-03 18:17:43 +02:00
|
|
|
fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]);
|
2012-10-15 06:37:04 +02:00
|
|
|
}
|
2012-08-01 12:52:36 +02:00
|
|
|
|
2017-12-13 18:59:21 +01:00
|
|
|
if (s->link_state_next_when) {
|
|
|
|
s->link_state_next_when--;
|
|
|
|
if (!s->link_state_next_when) {
|
|
|
|
s->link_state = s->link_state_next;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-06-03 18:17:43 +02:00
|
|
|
DB_PRINT_L(debug_level, "initial snoop state: %x\n",
|
|
|
|
(unsigned)s->snoop_state);
|
2012-10-15 06:37:04 +02:00
|
|
|
switch (s->snoop_state) {
|
|
|
|
case (SNOOP_CHECKING):
|
2017-12-13 18:59:21 +01:00
|
|
|
/* Store the count of dummy bytes in the txfifo */
|
|
|
|
s->cmd_dummies = xilinx_spips_num_dummies(q, tx);
|
|
|
|
addr_length = get_addr_length(s, tx);
|
|
|
|
if (s->cmd_dummies < 0) {
|
|
|
|
s->snoop_state = SNOOP_NONE;
|
|
|
|
} else {
|
|
|
|
s->snoop_state = SNOOP_ADDR + addr_length - 1;
|
|
|
|
}
|
|
|
|
switch (tx) {
|
2013-03-15 17:41:59 +01:00
|
|
|
case DPP:
|
|
|
|
case DOR:
|
2017-12-13 18:59:21 +01:00
|
|
|
case DOR_4:
|
|
|
|
s->link_state_next = 2;
|
|
|
|
s->link_state_next_when = addr_length + s->cmd_dummies;
|
|
|
|
break;
|
|
|
|
case QPP:
|
|
|
|
case QPP_4:
|
2013-03-15 17:41:59 +01:00
|
|
|
case QOR:
|
2017-12-13 18:59:21 +01:00
|
|
|
case QOR_4:
|
|
|
|
s->link_state_next = 4;
|
|
|
|
s->link_state_next_when = addr_length + s->cmd_dummies;
|
|
|
|
break;
|
|
|
|
case DIOR:
|
|
|
|
case DIOR_4:
|
|
|
|
s->link_state = 2;
|
2012-10-15 06:37:04 +02:00
|
|
|
break;
|
2017-12-13 18:59:21 +01:00
|
|
|
case QIOR:
|
|
|
|
case QIOR_4:
|
|
|
|
s->link_state = 4;
|
2012-10-15 06:37:04 +02:00
|
|
|
break;
|
2017-12-13 18:59:21 +01:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case (SNOOP_ADDR):
|
|
|
|
/* Address has been transmitted, transmit dummy cycles now if
|
|
|
|
* needed */
|
|
|
|
if (s->cmd_dummies < 0) {
|
2012-10-15 06:37:04 +02:00
|
|
|
s->snoop_state = SNOOP_NONE;
|
2017-12-13 18:59:21 +01:00
|
|
|
} else {
|
|
|
|
s->snoop_state = s->cmd_dummies;
|
2012-10-15 06:37:04 +02:00
|
|
|
}
|
2012-08-01 12:52:36 +02:00
|
|
|
break;
|
2012-10-15 06:37:04 +02:00
|
|
|
case (SNOOP_STRIPING):
|
|
|
|
case (SNOOP_NONE):
|
2013-06-03 18:17:43 +02:00
|
|
|
/* Once we hit the boring stuff - squelch debug noise */
|
|
|
|
if (!debug_level) {
|
|
|
|
DB_PRINT_L(0, "squelching debug info ....\n");
|
|
|
|
debug_level = 1;
|
|
|
|
}
|
2012-10-15 06:37:04 +02:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
s->snoop_state--;
|
2012-08-01 12:52:36 +02:00
|
|
|
}
|
2013-06-03 18:17:43 +02:00
|
|
|
DB_PRINT_L(debug_level, "final snoop state: %x\n",
|
|
|
|
(unsigned)s->snoop_state);
|
2012-10-15 06:37:04 +02:00
|
|
|
}
|
|
|
|
}
|
2012-08-01 12:52:36 +02:00
|
|
|
|
2017-12-13 18:59:21 +01:00
|
|
|
static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, bool be)
|
2012-10-15 06:37:04 +02:00
|
|
|
{
|
|
|
|
int i;
|
2017-12-13 18:59:21 +01:00
|
|
|
for (i = 0; i < num && !fifo8_is_full(fifo); ++i) {
|
|
|
|
if (be) {
|
|
|
|
fifo8_push(fifo, (uint8_t)(value >> 24));
|
|
|
|
value <<= 8;
|
|
|
|
} else {
|
|
|
|
fifo8_push(fifo, (uint8_t)value);
|
|
|
|
value >>= 8;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2012-10-15 06:37:04 +02:00
|
|
|
|
2017-12-13 18:59:21 +01:00
|
|
|
static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < max && !fifo8_is_empty(fifo); ++i) {
|
|
|
|
value[i] = fifo8_pop(fifo);
|
2012-08-01 12:52:36 +02:00
|
|
|
}
|
2017-12-13 18:59:21 +01:00
|
|
|
return max - i;
|
2012-08-01 12:52:36 +02:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
|
2012-08-01 12:52:36 +02:00
|
|
|
unsigned size)
|
|
|
|
{
|
|
|
|
XilinxSPIPS *s = opaque;
|
|
|
|
uint32_t mask = ~0;
|
|
|
|
uint32_t ret;
|
2013-06-03 18:17:44 +02:00
|
|
|
uint8_t rx_buf[4];
|
2017-12-13 18:59:21 +01:00
|
|
|
int shortfall;
|
2012-08-01 12:52:36 +02:00
|
|
|
|
|
|
|
addr >>= 2;
|
|
|
|
switch (addr) {
|
|
|
|
case R_CONFIG:
|
2013-06-03 18:17:43 +02:00
|
|
|
mask = ~(R_CONFIG_RSVD | MAN_START_COM);
|
2012-08-01 12:52:36 +02:00
|
|
|
break;
|
|
|
|
case R_INTR_STATUS:
|
2013-06-03 18:17:41 +02:00
|
|
|
ret = s->regs[addr] & IXR_ALL;
|
|
|
|
s->regs[addr] = 0;
|
2013-06-03 18:17:43 +02:00
|
|
|
DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
|
2013-06-03 18:17:41 +02:00
|
|
|
return ret;
|
2012-08-01 12:52:36 +02:00
|
|
|
case R_INTR_MASK:
|
|
|
|
mask = IXR_ALL;
|
|
|
|
break;
|
|
|
|
case R_EN:
|
|
|
|
mask = 0x1;
|
|
|
|
break;
|
|
|
|
case R_SLAVE_IDLE_COUNT:
|
|
|
|
mask = 0xFF;
|
|
|
|
break;
|
|
|
|
case R_MOD_ID:
|
|
|
|
mask = 0x01FFFFFF;
|
|
|
|
break;
|
|
|
|
case R_INTR_EN:
|
|
|
|
case R_INTR_DIS:
|
|
|
|
case R_TX_DATA:
|
|
|
|
mask = 0;
|
|
|
|
break;
|
|
|
|
case R_RX_DATA:
|
2013-06-03 18:17:44 +02:00
|
|
|
memset(rx_buf, 0, sizeof(rx_buf));
|
2017-12-13 18:59:21 +01:00
|
|
|
shortfall = rx_data_bytes(&s->rx_fifo, rx_buf, s->num_txrx_bytes);
|
|
|
|
ret = s->regs[R_CONFIG] & R_CONFIG_ENDIAN ?
|
|
|
|
cpu_to_be32(*(uint32_t *)rx_buf) :
|
|
|
|
cpu_to_le32(*(uint32_t *)rx_buf);
|
|
|
|
if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) {
|
|
|
|
ret <<= 8 * shortfall;
|
|
|
|
}
|
2013-06-03 18:17:43 +02:00
|
|
|
DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
|
2012-08-01 12:52:36 +02:00
|
|
|
xilinx_spips_update_ixr(s);
|
|
|
|
return ret;
|
|
|
|
}
|
2013-06-03 18:17:43 +02:00
|
|
|
DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4,
|
|
|
|
s->regs[addr] & mask);
|
2012-08-01 12:52:36 +02:00
|
|
|
return s->regs[addr] & mask;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void xilinx_spips_write(void *opaque, hwaddr addr,
|
2012-08-01 12:52:36 +02:00
|
|
|
uint64_t value, unsigned size)
|
|
|
|
{
|
|
|
|
int mask = ~0;
|
|
|
|
int man_start_com = 0;
|
|
|
|
XilinxSPIPS *s = opaque;
|
|
|
|
|
2013-06-03 18:17:43 +02:00
|
|
|
DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
|
2012-08-01 12:52:36 +02:00
|
|
|
addr >>= 2;
|
|
|
|
switch (addr) {
|
|
|
|
case R_CONFIG:
|
2013-06-03 18:17:43 +02:00
|
|
|
mask = ~(R_CONFIG_RSVD | MAN_START_COM);
|
2012-08-01 12:52:36 +02:00
|
|
|
if (value & MAN_START_COM) {
|
|
|
|
man_start_com = 1;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case R_INTR_STATUS:
|
|
|
|
mask = IXR_ALL;
|
|
|
|
s->regs[R_INTR_STATUS] &= ~(mask & value);
|
|
|
|
goto no_reg_update;
|
|
|
|
case R_INTR_DIS:
|
|
|
|
mask = IXR_ALL;
|
|
|
|
s->regs[R_INTR_MASK] &= ~(mask & value);
|
|
|
|
goto no_reg_update;
|
|
|
|
case R_INTR_EN:
|
|
|
|
mask = IXR_ALL;
|
|
|
|
s->regs[R_INTR_MASK] |= mask & value;
|
|
|
|
goto no_reg_update;
|
|
|
|
case R_EN:
|
|
|
|
mask = 0x1;
|
|
|
|
break;
|
|
|
|
case R_SLAVE_IDLE_COUNT:
|
|
|
|
mask = 0xFF;
|
|
|
|
break;
|
|
|
|
case R_RX_DATA:
|
|
|
|
case R_INTR_MASK:
|
|
|
|
case R_MOD_ID:
|
|
|
|
mask = 0;
|
|
|
|
break;
|
|
|
|
case R_TX_DATA:
|
2017-12-13 18:59:21 +01:00
|
|
|
tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes,
|
|
|
|
s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
|
2012-10-15 06:37:04 +02:00
|
|
|
goto no_reg_update;
|
|
|
|
case R_TXD1:
|
2017-12-13 18:59:21 +01:00
|
|
|
tx_data_bytes(&s->tx_fifo, (uint32_t)value, 1,
|
|
|
|
s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
|
2012-10-15 06:37:04 +02:00
|
|
|
goto no_reg_update;
|
|
|
|
case R_TXD2:
|
2017-12-13 18:59:21 +01:00
|
|
|
tx_data_bytes(&s->tx_fifo, (uint32_t)value, 2,
|
|
|
|
s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
|
2012-10-15 06:37:04 +02:00
|
|
|
goto no_reg_update;
|
|
|
|
case R_TXD3:
|
2017-12-13 18:59:21 +01:00
|
|
|
tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3,
|
|
|
|
s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
|
2012-08-01 12:52:36 +02:00
|
|
|
goto no_reg_update;
|
|
|
|
}
|
|
|
|
s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
|
|
|
|
no_reg_update:
|
2013-06-03 18:17:42 +02:00
|
|
|
xilinx_spips_update_cs_lines(s);
|
2013-06-03 18:17:42 +02:00
|
|
|
if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) ||
|
|
|
|
(fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_EN)) {
|
2012-08-01 12:52:36 +02:00
|
|
|
xilinx_spips_flush_txfifo(s);
|
|
|
|
}
|
|
|
|
xilinx_spips_update_cs_lines(s);
|
2013-06-03 18:17:42 +02:00
|
|
|
xilinx_spips_update_ixr(s);
|
2012-08-01 12:52:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps spips_ops = {
|
|
|
|
.read = xilinx_spips_read,
|
|
|
|
.write = xilinx_spips_write,
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
|
|
};
|
|
|
|
|
2016-10-20 11:09:53 +02:00
|
|
|
static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q)
|
|
|
|
{
|
|
|
|
XilinxSPIPS *s = &q->parent_obj;
|
|
|
|
|
2017-08-11 09:54:12 +02:00
|
|
|
if ((q->mmio_execution_enabled) && (q->lqspi_cached_addr != ~0ULL)) {
|
2016-10-20 11:09:53 +02:00
|
|
|
/* Invalidate the current mapped mmio */
|
|
|
|
memory_region_invalidate_mmio_ptr(&s->mmlqspi, q->lqspi_cached_addr,
|
|
|
|
LQSPI_CACHE_SIZE);
|
|
|
|
}
|
2017-08-11 09:54:12 +02:00
|
|
|
|
|
|
|
q->lqspi_cached_addr = ~0ULL;
|
2016-10-20 11:09:53 +02:00
|
|
|
}
|
|
|
|
|
2013-06-03 18:17:42 +02:00
|
|
|
static void xilinx_qspips_write(void *opaque, hwaddr addr,
|
|
|
|
uint64_t value, unsigned size)
|
|
|
|
{
|
|
|
|
XilinxQSPIPS *q = XILINX_QSPIPS(opaque);
|
2017-12-13 18:59:21 +01:00
|
|
|
XilinxSPIPS *s = XILINX_SPIPS(opaque);
|
2013-06-03 18:17:42 +02:00
|
|
|
|
|
|
|
xilinx_spips_write(opaque, addr, value, size);
|
|
|
|
addr >>= 2;
|
|
|
|
|
|
|
|
if (addr == R_LQSPI_CFG) {
|
2016-10-20 11:09:53 +02:00
|
|
|
xilinx_qspips_invalidate_mmio_ptr(q);
|
2013-06-03 18:17:42 +02:00
|
|
|
}
|
2017-12-13 18:59:21 +01:00
|
|
|
if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) {
|
|
|
|
fifo8_reset(&s->rx_fifo);
|
|
|
|
}
|
2013-06-03 18:17:42 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps qspips_ops = {
|
|
|
|
.read = xilinx_spips_read,
|
|
|
|
.write = xilinx_qspips_write,
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
|
|
};
|
|
|
|
|
2012-10-15 06:37:04 +02:00
|
|
|
#define LQSPI_CACHE_SIZE 1024
|
|
|
|
|
2016-10-20 11:09:53 +02:00
|
|
|
static void lqspi_load_cache(void *opaque, hwaddr addr)
|
2012-10-15 06:37:04 +02:00
|
|
|
{
|
2013-06-03 18:17:41 +02:00
|
|
|
XilinxQSPIPS *q = opaque;
|
2012-10-15 06:37:04 +02:00
|
|
|
XilinxSPIPS *s = opaque;
|
2016-10-20 11:09:53 +02:00
|
|
|
int i;
|
|
|
|
int flash_addr = ((addr & ~(LQSPI_CACHE_SIZE - 1))
|
|
|
|
/ num_effective_busses(s));
|
|
|
|
int slave = flash_addr >> LQSPI_ADDRESS_BITS;
|
|
|
|
int cache_entry = 0;
|
|
|
|
uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE;
|
|
|
|
|
|
|
|
if (addr < q->lqspi_cached_addr ||
|
|
|
|
addr > q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
|
|
|
|
xilinx_qspips_invalidate_mmio_ptr(q);
|
2013-06-03 18:17:43 +02:00
|
|
|
s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE;
|
|
|
|
s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0;
|
2012-10-15 06:37:04 +02:00
|
|
|
|
2013-06-03 18:17:43 +02:00
|
|
|
DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]);
|
2012-10-15 06:37:04 +02:00
|
|
|
|
|
|
|
fifo8_reset(&s->tx_fifo);
|
|
|
|
fifo8_reset(&s->rx_fifo);
|
|
|
|
|
|
|
|
/* instruction */
|
2013-06-03 18:17:43 +02:00
|
|
|
DB_PRINT_L(0, "pushing read instruction: %02x\n",
|
|
|
|
(unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] &
|
|
|
|
LQSPI_CFG_INST_CODE));
|
2012-10-15 06:37:04 +02:00
|
|
|
fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE);
|
|
|
|
/* read address */
|
2013-06-03 18:17:43 +02:00
|
|
|
DB_PRINT_L(0, "pushing read address %06x\n", flash_addr);
|
2012-10-15 06:37:04 +02:00
|
|
|
fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16));
|
|
|
|
fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8));
|
|
|
|
fifo8_push(&s->tx_fifo, (uint8_t)flash_addr);
|
|
|
|
/* mode bits */
|
|
|
|
if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) {
|
|
|
|
fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG],
|
|
|
|
LQSPI_CFG_MODE_SHIFT,
|
|
|
|
LQSPI_CFG_MODE_WIDTH));
|
|
|
|
}
|
|
|
|
/* dummy bytes */
|
|
|
|
for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT,
|
|
|
|
LQSPI_CFG_DUMMY_WIDTH)); ++i) {
|
2013-06-03 18:17:43 +02:00
|
|
|
DB_PRINT_L(0, "pushing dummy byte\n");
|
2012-10-15 06:37:04 +02:00
|
|
|
fifo8_push(&s->tx_fifo, 0);
|
|
|
|
}
|
2013-06-03 18:17:42 +02:00
|
|
|
xilinx_spips_update_cs_lines(s);
|
2012-10-15 06:37:04 +02:00
|
|
|
xilinx_spips_flush_txfifo(s);
|
|
|
|
fifo8_reset(&s->rx_fifo);
|
|
|
|
|
2013-06-03 18:17:43 +02:00
|
|
|
DB_PRINT_L(0, "starting QSPI data read\n");
|
2012-10-15 06:37:04 +02:00
|
|
|
|
2013-06-03 18:17:44 +02:00
|
|
|
while (cache_entry < LQSPI_CACHE_SIZE) {
|
|
|
|
for (i = 0; i < 64; ++i) {
|
2017-12-13 18:59:21 +01:00
|
|
|
tx_data_bytes(&s->tx_fifo, 0, 1, false);
|
2013-06-03 18:17:44 +02:00
|
|
|
}
|
2012-10-15 06:37:04 +02:00
|
|
|
xilinx_spips_flush_txfifo(s);
|
2013-06-03 18:17:44 +02:00
|
|
|
for (i = 0; i < 64; ++i) {
|
2017-12-13 18:59:21 +01:00
|
|
|
rx_data_bytes(&s->rx_fifo, &q->lqspi_buf[cache_entry++], 1);
|
2013-06-03 18:17:44 +02:00
|
|
|
}
|
2012-10-15 06:37:04 +02:00
|
|
|
}
|
|
|
|
|
2013-06-03 18:17:43 +02:00
|
|
|
s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE;
|
|
|
|
s->regs[R_LQSPI_STS] |= u_page_save;
|
2012-10-15 06:37:04 +02:00
|
|
|
xilinx_spips_update_cs_lines(s);
|
|
|
|
|
2013-06-03 18:17:44 +02:00
|
|
|
q->lqspi_cached_addr = flash_addr * num_effective_busses(s);
|
2016-10-20 11:09:53 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void *lqspi_request_mmio_ptr(void *opaque, hwaddr addr, unsigned *size,
|
|
|
|
unsigned *offset)
|
|
|
|
{
|
|
|
|
XilinxQSPIPS *q = opaque;
|
2017-08-11 09:54:12 +02:00
|
|
|
hwaddr offset_within_the_region;
|
2016-10-20 11:09:53 +02:00
|
|
|
|
2017-08-11 09:54:12 +02:00
|
|
|
if (!q->mmio_execution_enabled) {
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
offset_within_the_region = addr & ~(LQSPI_CACHE_SIZE - 1);
|
2016-10-20 11:09:53 +02:00
|
|
|
lqspi_load_cache(opaque, offset_within_the_region);
|
|
|
|
*size = LQSPI_CACHE_SIZE;
|
|
|
|
*offset = offset_within_the_region;
|
|
|
|
return q->lqspi_buf;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint64_t
|
|
|
|
lqspi_read(void *opaque, hwaddr addr, unsigned int size)
|
|
|
|
{
|
|
|
|
XilinxQSPIPS *q = opaque;
|
|
|
|
uint32_t ret;
|
|
|
|
|
|
|
|
if (addr >= q->lqspi_cached_addr &&
|
|
|
|
addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
|
|
|
|
uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr];
|
|
|
|
ret = cpu_to_le32(*(uint32_t *)retp);
|
|
|
|
DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr,
|
|
|
|
(unsigned)ret);
|
|
|
|
return ret;
|
|
|
|
} else {
|
|
|
|
lqspi_load_cache(opaque, addr);
|
2012-10-15 06:37:04 +02:00
|
|
|
return lqspi_read(opaque, addr, size);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps lqspi_ops = {
|
|
|
|
.read = lqspi_read,
|
2016-10-20 11:09:53 +02:00
|
|
|
.request_ptr = lqspi_request_mmio_ptr,
|
2012-10-15 06:37:04 +02:00
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
.valid = {
|
2013-06-03 18:17:44 +02:00
|
|
|
.min_access_size = 1,
|
2012-10-15 06:37:04 +02:00
|
|
|
.max_access_size = 4
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2013-03-15 17:41:59 +01:00
|
|
|
static void xilinx_spips_realize(DeviceState *dev, Error **errp)
|
2012-08-01 12:52:36 +02:00
|
|
|
{
|
2013-03-15 17:41:59 +01:00
|
|
|
XilinxSPIPS *s = XILINX_SPIPS(dev);
|
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
2013-06-03 18:17:42 +02:00
|
|
|
XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s);
|
2016-10-23 17:42:22 +02:00
|
|
|
qemu_irq *cs;
|
2012-08-01 12:52:36 +02:00
|
|
|
int i;
|
|
|
|
|
2013-06-03 18:17:43 +02:00
|
|
|
DB_PRINT_L(0, "realized spips\n");
|
2012-08-01 12:52:36 +02:00
|
|
|
|
2012-10-15 06:37:04 +02:00
|
|
|
s->spi = g_new(SSIBus *, s->num_busses);
|
|
|
|
for (i = 0; i < s->num_busses; ++i) {
|
|
|
|
char bus_name[16];
|
|
|
|
snprintf(bus_name, 16, "spi%d", i);
|
2013-03-15 17:41:59 +01:00
|
|
|
s->spi[i] = ssi_create_bus(dev, bus_name);
|
2012-10-15 06:37:04 +02:00
|
|
|
}
|
2012-10-01 04:34:37 +02:00
|
|
|
|
2013-03-15 17:41:58 +01:00
|
|
|
s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses);
|
2017-12-13 18:59:21 +01:00
|
|
|
s->cs_lines_state = g_new0(bool, s->num_cs * s->num_busses);
|
2016-10-23 17:42:22 +02:00
|
|
|
for (i = 0, cs = s->cs_lines; i < s->num_busses; ++i, cs += s->num_cs) {
|
|
|
|
ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]);
|
|
|
|
}
|
|
|
|
|
2013-03-15 17:41:59 +01:00
|
|
|
sysbus_init_irq(sbd, &s->irq);
|
2012-10-15 06:37:04 +02:00
|
|
|
for (i = 0; i < s->num_cs * s->num_busses; ++i) {
|
2013-03-15 17:41:59 +01:00
|
|
|
sysbus_init_irq(sbd, &s->cs_lines[i]);
|
2012-08-01 12:52:36 +02:00
|
|
|
}
|
|
|
|
|
2013-06-07 03:25:08 +02:00
|
|
|
memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s,
|
2016-01-21 15:15:03 +01:00
|
|
|
"spi", XLNX_SPIPS_R_MAX * 4);
|
2013-03-15 17:41:59 +01:00
|
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
2012-08-01 12:52:36 +02:00
|
|
|
|
|
|
|
s->irqline = -1;
|
|
|
|
|
2013-06-03 18:17:42 +02:00
|
|
|
fifo8_create(&s->rx_fifo, xsc->rx_fifo_size);
|
|
|
|
fifo8_create(&s->tx_fifo, xsc->tx_fifo_size);
|
2012-08-01 12:52:36 +02:00
|
|
|
}
|
|
|
|
|
2013-06-03 18:17:41 +02:00
|
|
|
static void xilinx_qspips_realize(DeviceState *dev, Error **errp)
|
|
|
|
{
|
|
|
|
XilinxSPIPS *s = XILINX_SPIPS(dev);
|
|
|
|
XilinxQSPIPS *q = XILINX_QSPIPS(dev);
|
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
|
|
|
|
2013-06-03 18:17:43 +02:00
|
|
|
DB_PRINT_L(0, "realized qspips\n");
|
2013-06-03 18:17:41 +02:00
|
|
|
|
|
|
|
s->num_busses = 2;
|
|
|
|
s->num_cs = 2;
|
|
|
|
s->num_txrx_bytes = 4;
|
|
|
|
|
|
|
|
xilinx_spips_realize(dev, errp);
|
2013-06-07 03:25:08 +02:00
|
|
|
memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi",
|
2013-06-03 18:17:41 +02:00
|
|
|
(1 << LQSPI_ADDRESS_BITS) * 2);
|
|
|
|
sysbus_init_mmio(sbd, &s->mmlqspi);
|
|
|
|
|
|
|
|
q->lqspi_cached_addr = ~0ULL;
|
2017-08-11 09:54:12 +02:00
|
|
|
|
|
|
|
/* mmio_execution breaks migration better aborting than having strange
|
|
|
|
* bugs.
|
|
|
|
*/
|
|
|
|
if (q->mmio_execution_enabled) {
|
|
|
|
error_setg(&q->migration_blocker,
|
|
|
|
"enabling mmio_execution breaks migration");
|
|
|
|
migrate_add_blocker(q->migration_blocker, &error_fatal);
|
|
|
|
}
|
2013-06-03 18:17:41 +02:00
|
|
|
}
|
|
|
|
|
2012-08-01 12:52:36 +02:00
|
|
|
static int xilinx_spips_post_load(void *opaque, int version_id)
|
|
|
|
{
|
|
|
|
xilinx_spips_update_ixr((XilinxSPIPS *)opaque);
|
|
|
|
xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const VMStateDescription vmstate_xilinx_spips = {
|
|
|
|
.name = "xilinx_spips",
|
2012-10-15 06:37:04 +02:00
|
|
|
.version_id = 2,
|
|
|
|
.minimum_version_id = 2,
|
2012-08-01 12:52:36 +02:00
|
|
|
.post_load = xilinx_spips_post_load,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_FIFO8(tx_fifo, XilinxSPIPS),
|
|
|
|
VMSTATE_FIFO8(rx_fifo, XilinxSPIPS),
|
2016-01-21 15:15:03 +01:00
|
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VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX),
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2012-10-15 06:37:04 +02:00
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VMSTATE_UINT8(snoop_state, XilinxSPIPS),
|
2012-08-01 12:52:36 +02:00
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|
VMSTATE_END_OF_LIST()
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}
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};
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|
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|
2017-08-11 09:54:12 +02:00
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|
|
static Property xilinx_qspips_properties[] = {
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|
|
|
/* We had to turn this off for 2.10 as it is not compatible with migration.
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|
|
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* It can be enabled but will prevent the device to be migrated.
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|
|
|
* This will go aways when a fix will be released.
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|
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|
*/
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DEFINE_PROP_BOOL("x-mmio-exec", XilinxQSPIPS, mmio_execution_enabled,
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|
|
|
false),
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|
|
|
DEFINE_PROP_END_OF_LIST(),
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|
};
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|
|
|
2012-10-15 06:37:04 +02:00
|
|
|
static Property xilinx_spips_properties[] = {
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|
|
|
DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1),
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|
|
|
DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4),
|
|
|
|
DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1),
|
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
2013-06-03 18:17:41 +02:00
|
|
|
|
|
|
|
static void xilinx_qspips_class_init(ObjectClass *klass, void * data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2013-06-03 18:17:42 +02:00
|
|
|
XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
|
2013-06-03 18:17:41 +02:00
|
|
|
|
|
|
|
dc->realize = xilinx_qspips_realize;
|
2017-08-11 09:54:12 +02:00
|
|
|
dc->props = xilinx_qspips_properties;
|
2013-06-03 18:17:42 +02:00
|
|
|
xsc->reg_ops = &qspips_ops;
|
2013-06-03 18:17:42 +02:00
|
|
|
xsc->rx_fifo_size = RXFF_A_Q;
|
|
|
|
xsc->tx_fifo_size = TXFF_A_Q;
|
2013-06-03 18:17:41 +02:00
|
|
|
}
|
|
|
|
|
2012-08-01 12:52:36 +02:00
|
|
|
static void xilinx_spips_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2013-06-03 18:17:42 +02:00
|
|
|
XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
|
2012-08-01 12:52:36 +02:00
|
|
|
|
2013-03-15 17:41:59 +01:00
|
|
|
dc->realize = xilinx_spips_realize;
|
2012-08-01 12:52:36 +02:00
|
|
|
dc->reset = xilinx_spips_reset;
|
2012-10-15 06:37:04 +02:00
|
|
|
dc->props = xilinx_spips_properties;
|
2012-08-01 12:52:36 +02:00
|
|
|
dc->vmsd = &vmstate_xilinx_spips;
|
2013-06-03 18:17:42 +02:00
|
|
|
|
2013-06-03 18:17:42 +02:00
|
|
|
xsc->reg_ops = &spips_ops;
|
2013-06-03 18:17:42 +02:00
|
|
|
xsc->rx_fifo_size = RXFF_A;
|
|
|
|
xsc->tx_fifo_size = TXFF_A;
|
2012-08-01 12:52:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo xilinx_spips_info = {
|
2013-03-15 17:41:59 +01:00
|
|
|
.name = TYPE_XILINX_SPIPS,
|
2012-08-01 12:52:36 +02:00
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(XilinxSPIPS),
|
|
|
|
.class_init = xilinx_spips_class_init,
|
2013-06-03 18:17:42 +02:00
|
|
|
.class_size = sizeof(XilinxSPIPSClass),
|
2012-08-01 12:52:36 +02:00
|
|
|
};
|
|
|
|
|
2013-06-03 18:17:41 +02:00
|
|
|
static const TypeInfo xilinx_qspips_info = {
|
|
|
|
.name = TYPE_XILINX_QSPIPS,
|
|
|
|
.parent = TYPE_XILINX_SPIPS,
|
|
|
|
.instance_size = sizeof(XilinxQSPIPS),
|
|
|
|
.class_init = xilinx_qspips_class_init,
|
|
|
|
};
|
|
|
|
|
2012-08-01 12:52:36 +02:00
|
|
|
static void xilinx_spips_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&xilinx_spips_info);
|
2013-06-03 18:17:41 +02:00
|
|
|
type_register_static(&xilinx_qspips_info);
|
2012-08-01 12:52:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
type_init(xilinx_spips_register_types)
|