2021-12-17 17:57:18 +01:00
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/*
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* PMU emulation helpers for TCG IBM POWER chips
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*
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* Copyright IBM Corp. 2021
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*
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* Authors:
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* Daniel Henrique Barboza <danielhb413@gmail.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "power8-pmu.h"
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#include "cpu.h"
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#include "helper_regs.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "qemu/error-report.h"
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#include "qemu/main-loop.h"
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#include "hw/ppc/ppc.h"
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#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
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2021-12-17 17:57:18 +01:00
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#define PMC_COUNTER_NEGATIVE_VAL 0x80000000UL
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target/ppc: PMU basic cycle count for pseries TCG
This patch adds the barebones of the PMU logic by enabling cycle
counting. The overall logic goes as follows:
- MMCR0 reg initial value is set to 0x80000000 (MMCR0_FC set) to avoid
having to spin the PMU right at system init;
- to retrieve the events that are being profiled, pmc_get_event() will
check the current MMCR0 and MMCR1 value and return the appropriate
PMUEventType. For PMCs 1-4, event 0x2 is the implementation dependent
value of PMU_EVENT_INSTRUCTIONS and event 0x1E is the implementation
dependent value of PMU_EVENT_CYCLES. These events are supported by IBM
Power chips since Power8, at least, and the Linux Perf driver makes use
of these events until kernel v5.15. For PMC1, event 0xF0 is the
architected PowerISA event for cycles. Event 0xFE is the architected
PowerISA event for instructions;
- if the counter is frozen, either via the global MMCR0_FC bit or its
individual frozen counter bits, PMU_EVENT_INACTIVE is returned;
- pmu_update_cycles() will go through each counter and update the
values of all PMCs that are counting cycles. This function will be
called every time a MMCR0 update is done to keep counters values
up to date. Upcoming patches will use this function to allow the
counters to be properly updated during read/write of the PMCs
and MMCR1 writes.
Given that the base CPU frequency is fixed at 1Ghz for both powernv and
pseries clock, cycle calculation assumes that 1 nanosecond equals 1 CPU
cycle. Cycle value is then calculated by adding the elapsed time, in
nanoseconds, of the last cycle update done via pmu_update_cycles().
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17 17:57:18 +01:00
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static bool pmc_is_inactive(CPUPPCState *env, int sprn)
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{
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if (env->spr[SPR_POWER_MMCR0] & MMCR0_FC) {
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return true;
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}
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if (sprn < SPR_POWER_PMC5) {
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return env->spr[SPR_POWER_MMCR0] & MMCR0_FC14;
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}
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return env->spr[SPR_POWER_MMCR0] & MMCR0_FC56;
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}
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2021-12-17 17:57:18 +01:00
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static bool pmc_has_overflow_enabled(CPUPPCState *env, int sprn)
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{
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if (sprn == SPR_POWER_PMC1) {
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return env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE;
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}
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return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE;
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}
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target/ppc: PMU basic cycle count for pseries TCG
This patch adds the barebones of the PMU logic by enabling cycle
counting. The overall logic goes as follows:
- MMCR0 reg initial value is set to 0x80000000 (MMCR0_FC set) to avoid
having to spin the PMU right at system init;
- to retrieve the events that are being profiled, pmc_get_event() will
check the current MMCR0 and MMCR1 value and return the appropriate
PMUEventType. For PMCs 1-4, event 0x2 is the implementation dependent
value of PMU_EVENT_INSTRUCTIONS and event 0x1E is the implementation
dependent value of PMU_EVENT_CYCLES. These events are supported by IBM
Power chips since Power8, at least, and the Linux Perf driver makes use
of these events until kernel v5.15. For PMC1, event 0xF0 is the
architected PowerISA event for cycles. Event 0xFE is the architected
PowerISA event for instructions;
- if the counter is frozen, either via the global MMCR0_FC bit or its
individual frozen counter bits, PMU_EVENT_INACTIVE is returned;
- pmu_update_cycles() will go through each counter and update the
values of all PMCs that are counting cycles. This function will be
called every time a MMCR0 update is done to keep counters values
up to date. Upcoming patches will use this function to allow the
counters to be properly updated during read/write of the PMCs
and MMCR1 writes.
Given that the base CPU frequency is fixed at 1Ghz for both powernv and
pseries clock, cycle calculation assumes that 1 nanosecond equals 1 CPU
cycle. Cycle value is then calculated by adding the elapsed time, in
nanoseconds, of the last cycle update done via pmu_update_cycles().
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17 17:57:18 +01:00
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/*
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* For PMCs 1-4, IBM POWER chips has support for an implementation
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* dependent event, 0x1E, that enables cycle counting. The Linux kernel
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* makes extensive use of 0x1E, so let's also support it.
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*
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* Likewise, event 0x2 is an implementation-dependent event that IBM
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* POWER chips implement (at least since POWER8) that is equivalent to
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* PM_INST_CMPL. Let's support this event on PMCs 1-4 as well.
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*/
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static PMUEventType pmc_get_event(CPUPPCState *env, int sprn)
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{
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uint8_t mmcr1_evt_extr[] = { MMCR1_PMC1EVT_EXTR, MMCR1_PMC2EVT_EXTR,
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MMCR1_PMC3EVT_EXTR, MMCR1_PMC4EVT_EXTR };
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PMUEventType evt_type = PMU_EVENT_INVALID;
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uint8_t pmcsel;
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int i;
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if (pmc_is_inactive(env, sprn)) {
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return PMU_EVENT_INACTIVE;
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}
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if (sprn == SPR_POWER_PMC5) {
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return PMU_EVENT_INSTRUCTIONS;
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}
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if (sprn == SPR_POWER_PMC6) {
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return PMU_EVENT_CYCLES;
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}
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i = sprn - SPR_POWER_PMC1;
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pmcsel = extract64(env->spr[SPR_POWER_MMCR1], mmcr1_evt_extr[i],
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MMCR1_EVT_SIZE);
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switch (pmcsel) {
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case 0x2:
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evt_type = PMU_EVENT_INSTRUCTIONS;
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break;
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case 0x1E:
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evt_type = PMU_EVENT_CYCLES;
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break;
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case 0xF0:
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/*
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* PMC1SEL = 0xF0 is the architected PowerISA v3.1
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* event that counts cycles using PMC1.
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*/
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if (sprn == SPR_POWER_PMC1) {
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evt_type = PMU_EVENT_CYCLES;
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}
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break;
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2021-12-17 17:57:18 +01:00
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case 0xFA:
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/*
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* PMC4SEL = 0xFA is the "instructions completed
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* with run latch set" event.
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*/
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if (sprn == SPR_POWER_PMC4) {
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evt_type = PMU_EVENT_INSN_RUN_LATCH;
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}
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break;
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target/ppc: PMU basic cycle count for pseries TCG
This patch adds the barebones of the PMU logic by enabling cycle
counting. The overall logic goes as follows:
- MMCR0 reg initial value is set to 0x80000000 (MMCR0_FC set) to avoid
having to spin the PMU right at system init;
- to retrieve the events that are being profiled, pmc_get_event() will
check the current MMCR0 and MMCR1 value and return the appropriate
PMUEventType. For PMCs 1-4, event 0x2 is the implementation dependent
value of PMU_EVENT_INSTRUCTIONS and event 0x1E is the implementation
dependent value of PMU_EVENT_CYCLES. These events are supported by IBM
Power chips since Power8, at least, and the Linux Perf driver makes use
of these events until kernel v5.15. For PMC1, event 0xF0 is the
architected PowerISA event for cycles. Event 0xFE is the architected
PowerISA event for instructions;
- if the counter is frozen, either via the global MMCR0_FC bit or its
individual frozen counter bits, PMU_EVENT_INACTIVE is returned;
- pmu_update_cycles() will go through each counter and update the
values of all PMCs that are counting cycles. This function will be
called every time a MMCR0 update is done to keep counters values
up to date. Upcoming patches will use this function to allow the
counters to be properly updated during read/write of the PMCs
and MMCR1 writes.
Given that the base CPU frequency is fixed at 1Ghz for both powernv and
pseries clock, cycle calculation assumes that 1 nanosecond equals 1 CPU
cycle. Cycle value is then calculated by adding the elapsed time, in
nanoseconds, of the last cycle update done via pmu_update_cycles().
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17 17:57:18 +01:00
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case 0xFE:
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/*
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* PMC1SEL = 0xFE is the architected PowerISA v3.1
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* event to sample instructions using PMC1.
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*/
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if (sprn == SPR_POWER_PMC1) {
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evt_type = PMU_EVENT_INSTRUCTIONS;
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}
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break;
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default:
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break;
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}
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return evt_type;
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}
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2021-12-17 17:57:18 +01:00
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bool pmu_insn_cnt_enabled(CPUPPCState *env)
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{
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int sprn;
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for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) {
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2021-12-17 17:57:18 +01:00
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if (pmc_get_event(env, sprn) == PMU_EVENT_INSTRUCTIONS ||
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pmc_get_event(env, sprn) == PMU_EVENT_INSN_RUN_LATCH) {
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2021-12-17 17:57:18 +01:00
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return true;
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}
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}
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return false;
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}
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static bool pmu_increment_insns(CPUPPCState *env, uint32_t num_insns)
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{
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bool overflow_triggered = false;
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int sprn;
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/* PMC6 never counts instructions */
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for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) {
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2021-12-17 17:57:18 +01:00
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PMUEventType evt_type = pmc_get_event(env, sprn);
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bool insn_event = evt_type == PMU_EVENT_INSTRUCTIONS ||
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evt_type == PMU_EVENT_INSN_RUN_LATCH;
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if (pmc_is_inactive(env, sprn) || !insn_event) {
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2021-12-17 17:57:18 +01:00
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continue;
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}
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2021-12-17 17:57:18 +01:00
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if (evt_type == PMU_EVENT_INSTRUCTIONS) {
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env->spr[sprn] += num_insns;
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}
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if (evt_type == PMU_EVENT_INSN_RUN_LATCH &&
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env->spr[SPR_CTRL] & CTRL_RUN) {
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env->spr[sprn] += num_insns;
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}
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2021-12-17 17:57:18 +01:00
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if (env->spr[sprn] >= PMC_COUNTER_NEGATIVE_VAL &&
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pmc_has_overflow_enabled(env, sprn)) {
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overflow_triggered = true;
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/*
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* The real PMU will always trigger a counter overflow with
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* PMC_COUNTER_NEGATIVE_VAL. We don't have an easy way to
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* do that since we're counting block of instructions at
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* the end of each translation block, and we're probably
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* passing this value at this point.
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*
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* Let's write PMC_COUNTER_NEGATIVE_VAL to the overflowed
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* counter to simulate what the real hardware would do.
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*/
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env->spr[sprn] = PMC_COUNTER_NEGATIVE_VAL;
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}
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}
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return overflow_triggered;
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}
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target/ppc: PMU basic cycle count for pseries TCG
This patch adds the barebones of the PMU logic by enabling cycle
counting. The overall logic goes as follows:
- MMCR0 reg initial value is set to 0x80000000 (MMCR0_FC set) to avoid
having to spin the PMU right at system init;
- to retrieve the events that are being profiled, pmc_get_event() will
check the current MMCR0 and MMCR1 value and return the appropriate
PMUEventType. For PMCs 1-4, event 0x2 is the implementation dependent
value of PMU_EVENT_INSTRUCTIONS and event 0x1E is the implementation
dependent value of PMU_EVENT_CYCLES. These events are supported by IBM
Power chips since Power8, at least, and the Linux Perf driver makes use
of these events until kernel v5.15. For PMC1, event 0xF0 is the
architected PowerISA event for cycles. Event 0xFE is the architected
PowerISA event for instructions;
- if the counter is frozen, either via the global MMCR0_FC bit or its
individual frozen counter bits, PMU_EVENT_INACTIVE is returned;
- pmu_update_cycles() will go through each counter and update the
values of all PMCs that are counting cycles. This function will be
called every time a MMCR0 update is done to keep counters values
up to date. Upcoming patches will use this function to allow the
counters to be properly updated during read/write of the PMCs
and MMCR1 writes.
Given that the base CPU frequency is fixed at 1Ghz for both powernv and
pseries clock, cycle calculation assumes that 1 nanosecond equals 1 CPU
cycle. Cycle value is then calculated by adding the elapsed time, in
nanoseconds, of the last cycle update done via pmu_update_cycles().
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17 17:57:18 +01:00
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static void pmu_update_cycles(CPUPPCState *env)
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{
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uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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uint64_t time_delta = now - env->pmu_base_time;
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int sprn;
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for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) {
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if (pmc_get_event(env, sprn) != PMU_EVENT_CYCLES) {
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continue;
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}
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/*
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* The pseries and powernv clock runs at 1Ghz, meaning
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* that 1 nanosec equals 1 cycle.
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*/
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env->spr[sprn] += time_delta;
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}
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/* Update base_time for future calculations */
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env->pmu_base_time = now;
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}
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2021-12-17 17:57:18 +01:00
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/*
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* Helper function to retrieve the cycle overflow timer of the
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* 'sprn' counter.
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*/
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static QEMUTimer *get_cyc_overflow_timer(CPUPPCState *env, int sprn)
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{
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return env->pmu_cyc_overflow_timers[sprn - SPR_POWER_PMC1];
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}
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static void pmc_update_overflow_timer(CPUPPCState *env, int sprn)
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{
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QEMUTimer *pmc_overflow_timer = get_cyc_overflow_timer(env, sprn);
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int64_t timeout;
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/*
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* PMC5 does not have an overflow timer and this pointer
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* will be NULL.
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*/
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if (!pmc_overflow_timer) {
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return;
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}
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if (pmc_get_event(env, sprn) != PMU_EVENT_CYCLES ||
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!pmc_has_overflow_enabled(env, sprn)) {
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/* Overflow timer is not needed for this counter */
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timer_del(pmc_overflow_timer);
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return;
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}
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if (env->spr[sprn] >= PMC_COUNTER_NEGATIVE_VAL) {
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timeout = 0;
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} else {
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timeout = PMC_COUNTER_NEGATIVE_VAL - env->spr[sprn];
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}
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/*
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* Use timer_mod_anticipate() because an overflow timer might
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* be already running for this PMC.
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*/
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timer_mod_anticipate(pmc_overflow_timer, env->pmu_base_time + timeout);
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}
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static void pmu_update_overflow_timers(CPUPPCState *env)
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{
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int sprn;
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/*
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* Scroll through all PMCs and start counter overflow timers for
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* PM_CYC events, if needed.
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*/
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for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) {
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|
|
pmc_update_overflow_timer(env, sprn);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
target/ppc: PMU basic cycle count for pseries TCG
This patch adds the barebones of the PMU logic by enabling cycle
counting. The overall logic goes as follows:
- MMCR0 reg initial value is set to 0x80000000 (MMCR0_FC set) to avoid
having to spin the PMU right at system init;
- to retrieve the events that are being profiled, pmc_get_event() will
check the current MMCR0 and MMCR1 value and return the appropriate
PMUEventType. For PMCs 1-4, event 0x2 is the implementation dependent
value of PMU_EVENT_INSTRUCTIONS and event 0x1E is the implementation
dependent value of PMU_EVENT_CYCLES. These events are supported by IBM
Power chips since Power8, at least, and the Linux Perf driver makes use
of these events until kernel v5.15. For PMC1, event 0xF0 is the
architected PowerISA event for cycles. Event 0xFE is the architected
PowerISA event for instructions;
- if the counter is frozen, either via the global MMCR0_FC bit or its
individual frozen counter bits, PMU_EVENT_INACTIVE is returned;
- pmu_update_cycles() will go through each counter and update the
values of all PMCs that are counting cycles. This function will be
called every time a MMCR0 update is done to keep counters values
up to date. Upcoming patches will use this function to allow the
counters to be properly updated during read/write of the PMCs
and MMCR1 writes.
Given that the base CPU frequency is fixed at 1Ghz for both powernv and
pseries clock, cycle calculation assumes that 1 nanosecond equals 1 CPU
cycle. Cycle value is then calculated by adding the elapsed time, in
nanoseconds, of the last cycle update done via pmu_update_cycles().
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17 17:57:18 +01:00
|
|
|
void helper_store_mmcr0(CPUPPCState *env, target_ulong value)
|
|
|
|
{
|
|
|
|
pmu_update_cycles(env);
|
|
|
|
|
|
|
|
env->spr[SPR_POWER_MMCR0] = value;
|
|
|
|
|
2021-12-17 17:57:18 +01:00
|
|
|
/* MMCR0 writes can change HFLAGS_PMCCCLEAR and HFLAGS_INSN_CNT */
|
target/ppc: PMU basic cycle count for pseries TCG
This patch adds the barebones of the PMU logic by enabling cycle
counting. The overall logic goes as follows:
- MMCR0 reg initial value is set to 0x80000000 (MMCR0_FC set) to avoid
having to spin the PMU right at system init;
- to retrieve the events that are being profiled, pmc_get_event() will
check the current MMCR0 and MMCR1 value and return the appropriate
PMUEventType. For PMCs 1-4, event 0x2 is the implementation dependent
value of PMU_EVENT_INSTRUCTIONS and event 0x1E is the implementation
dependent value of PMU_EVENT_CYCLES. These events are supported by IBM
Power chips since Power8, at least, and the Linux Perf driver makes use
of these events until kernel v5.15. For PMC1, event 0xF0 is the
architected PowerISA event for cycles. Event 0xFE is the architected
PowerISA event for instructions;
- if the counter is frozen, either via the global MMCR0_FC bit or its
individual frozen counter bits, PMU_EVENT_INACTIVE is returned;
- pmu_update_cycles() will go through each counter and update the
values of all PMCs that are counting cycles. This function will be
called every time a MMCR0 update is done to keep counters values
up to date. Upcoming patches will use this function to allow the
counters to be properly updated during read/write of the PMCs
and MMCR1 writes.
Given that the base CPU frequency is fixed at 1Ghz for both powernv and
pseries clock, cycle calculation assumes that 1 nanosecond equals 1 CPU
cycle. Cycle value is then calculated by adding the elapsed time, in
nanoseconds, of the last cycle update done via pmu_update_cycles().
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17 17:57:18 +01:00
|
|
|
hreg_compute_hflags(env);
|
2021-12-17 17:57:18 +01:00
|
|
|
|
|
|
|
/* Update cycle overflow timers with the current MMCR0 state */
|
|
|
|
pmu_update_overflow_timers(env);
|
target/ppc: PMU basic cycle count for pseries TCG
This patch adds the barebones of the PMU logic by enabling cycle
counting. The overall logic goes as follows:
- MMCR0 reg initial value is set to 0x80000000 (MMCR0_FC set) to avoid
having to spin the PMU right at system init;
- to retrieve the events that are being profiled, pmc_get_event() will
check the current MMCR0 and MMCR1 value and return the appropriate
PMUEventType. For PMCs 1-4, event 0x2 is the implementation dependent
value of PMU_EVENT_INSTRUCTIONS and event 0x1E is the implementation
dependent value of PMU_EVENT_CYCLES. These events are supported by IBM
Power chips since Power8, at least, and the Linux Perf driver makes use
of these events until kernel v5.15. For PMC1, event 0xF0 is the
architected PowerISA event for cycles. Event 0xFE is the architected
PowerISA event for instructions;
- if the counter is frozen, either via the global MMCR0_FC bit or its
individual frozen counter bits, PMU_EVENT_INACTIVE is returned;
- pmu_update_cycles() will go through each counter and update the
values of all PMCs that are counting cycles. This function will be
called every time a MMCR0 update is done to keep counters values
up to date. Upcoming patches will use this function to allow the
counters to be properly updated during read/write of the PMCs
and MMCR1 writes.
Given that the base CPU frequency is fixed at 1Ghz for both powernv and
pseries clock, cycle calculation assumes that 1 nanosecond equals 1 CPU
cycle. Cycle value is then calculated by adding the elapsed time, in
nanoseconds, of the last cycle update done via pmu_update_cycles().
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17 17:57:18 +01:00
|
|
|
}
|
|
|
|
|
2021-12-17 17:57:18 +01:00
|
|
|
void helper_store_mmcr1(CPUPPCState *env, uint64_t value)
|
|
|
|
{
|
|
|
|
pmu_update_cycles(env);
|
|
|
|
|
|
|
|
env->spr[SPR_POWER_MMCR1] = value;
|
2021-12-17 17:57:18 +01:00
|
|
|
|
|
|
|
/* MMCR1 writes can change HFLAGS_INSN_CNT */
|
|
|
|
hreg_compute_hflags(env);
|
2021-12-17 17:57:18 +01:00
|
|
|
}
|
|
|
|
|
2021-12-17 17:57:18 +01:00
|
|
|
target_ulong helper_read_pmc(CPUPPCState *env, uint32_t sprn)
|
|
|
|
{
|
|
|
|
pmu_update_cycles(env);
|
|
|
|
|
|
|
|
return env->spr[sprn];
|
|
|
|
}
|
|
|
|
|
|
|
|
void helper_store_pmc(CPUPPCState *env, uint32_t sprn, uint64_t value)
|
|
|
|
{
|
|
|
|
pmu_update_cycles(env);
|
|
|
|
|
|
|
|
env->spr[sprn] = value;
|
2021-12-17 17:57:18 +01:00
|
|
|
|
|
|
|
pmc_update_overflow_timer(env, sprn);
|
2021-12-17 17:57:18 +01:00
|
|
|
}
|
|
|
|
|
2021-12-17 17:57:18 +01:00
|
|
|
static void fire_PMC_interrupt(PowerPCCPU *cpu)
|
|
|
|
{
|
|
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
|
|
|
|
if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_EBE)) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* PMC interrupt not implemented yet */
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2021-12-17 17:57:18 +01:00
|
|
|
/* This helper assumes that the PMC is running. */
|
|
|
|
void helper_insns_inc(CPUPPCState *env, uint32_t num_insns)
|
|
|
|
{
|
|
|
|
bool overflow_triggered;
|
|
|
|
PowerPCCPU *cpu;
|
|
|
|
|
|
|
|
overflow_triggered = pmu_increment_insns(env, num_insns);
|
|
|
|
|
|
|
|
if (overflow_triggered) {
|
|
|
|
cpu = env_archcpu(env);
|
|
|
|
fire_PMC_interrupt(cpu);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-12-17 17:57:18 +01:00
|
|
|
static void cpu_ppc_pmu_timer_cb(void *opaque)
|
|
|
|
{
|
|
|
|
PowerPCCPU *cpu = opaque;
|
|
|
|
|
|
|
|
fire_PMC_interrupt(cpu);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_ppc_pmu_init(CPUPPCState *env)
|
|
|
|
{
|
|
|
|
PowerPCCPU *cpu = env_archcpu(env);
|
|
|
|
int i, sprn;
|
|
|
|
|
|
|
|
for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) {
|
|
|
|
if (sprn == SPR_POWER_PMC5) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
i = sprn - SPR_POWER_PMC1;
|
|
|
|
|
|
|
|
env->pmu_cyc_overflow_timers[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL,
|
|
|
|
&cpu_ppc_pmu_timer_cb,
|
|
|
|
cpu);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
|