2007-01-17 21:03:15 +01:00
|
|
|
Unsolved issues/bugs in the mips/mipsel backend
|
|
|
|
|
-----------------------------------------------
|
|
|
|
|
|
2007-01-19 18:56:23 +01:00
|
|
|
General
|
|
|
|
|
-------
|
2007-01-17 21:03:15 +01:00
|
|
|
- [ls][dw][lr] report broken (aligned) BadVAddr
|
|
|
|
|
- Missing per-CPU instruction decoding, currently all implemented
|
|
|
|
|
instructions are regarded as valid
|
|
|
|
|
- pcnet32 does not work for little endian emulation on big endian host
|
|
|
|
|
(probably not mips specific, but observable for mips-malta)
|
2007-03-17 16:39:48 +01:00
|
|
|
- CP1 enable/disable is checked at translation time, not at execution
|
|
|
|
|
time, so it will have delayed effect.
|
2007-01-17 21:03:15 +01:00
|
|
|
|
2007-01-19 18:56:23 +01:00
|
|
|
MIPS64
|
|
|
|
|
------
|
|
|
|
|
- No 64bit TLB support
|
|
|
|
|
- no 64bit wide registers for FPU
|
|
|
|
|
- 64bit mul/div handling broken
|
|
|
|
|
|
|
|
|
|
"Generic" 4Kc system emulation
|
|
|
|
|
------------------------------
|
|
|
|
|
- Doesn't correspond to any real hardware.
|
|
|
|
|
|
|
|
|
|
MALTA system emulation
|
|
|
|
|
----------------------
|
2007-01-17 21:03:15 +01:00
|
|
|
- We fake firmware support instead of doing the real thing
|
2007-02-02 03:56:33 +01:00
|
|
|
- Real firmware falls over when trying to init RAM, presumably due
|
|
|
|
|
to lacking I2C emulation.
|
