2016-07-04 14:06:37 +02:00
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/*
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* ASPEED AST2400 SMC Controller (SPI Flash Only)
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*
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* Copyright (C) 2016 IBM Corp.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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2019-08-12 07:23:45 +02:00
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#include "migration/vmstate.h"
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2016-07-04 14:06:37 +02:00
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#include "qemu/log.h"
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2019-05-23 16:35:07 +02:00
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#include "qemu/module.h"
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2017-10-17 18:44:02 +02:00
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#include "qemu/error-report.h"
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2019-09-04 09:05:01 +02:00
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#include "qapi/error.h"
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#include "exec/address-spaces.h"
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2019-09-25 16:32:38 +02:00
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#include "qemu/units.h"
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2020-02-06 12:26:44 +01:00
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#include "trace.h"
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2016-07-04 14:06:37 +02:00
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2019-08-12 07:23:42 +02:00
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#include "hw/irq.h"
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2019-08-12 07:23:51 +02:00
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#include "hw/qdev-properties.h"
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2016-07-04 14:06:37 +02:00
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#include "hw/ssi/aspeed_smc.h"
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/* CE Type Setting Register */
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#define R_CONF (0x00 / 4)
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#define CONF_LEGACY_DISABLE (1 << 31)
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#define CONF_ENABLE_W4 20
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#define CONF_ENABLE_W3 19
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#define CONF_ENABLE_W2 18
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#define CONF_ENABLE_W1 17
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#define CONF_ENABLE_W0 16
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2017-01-20 12:15:07 +01:00
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#define CONF_FLASH_TYPE4 8
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#define CONF_FLASH_TYPE3 6
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#define CONF_FLASH_TYPE2 4
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#define CONF_FLASH_TYPE1 2
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#define CONF_FLASH_TYPE0 0
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#define CONF_FLASH_TYPE_NOR 0x0
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#define CONF_FLASH_TYPE_NAND 0x1
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2019-09-25 16:32:38 +02:00
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#define CONF_FLASH_TYPE_SPI 0x2 /* AST2600 is SPI only */
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2016-07-04 14:06:37 +02:00
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/* CE Control Register */
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#define R_CE_CTRL (0x04 / 4)
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#define CTRL_EXTENDED4 4 /* 32 bit addressing for SPI */
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#define CTRL_EXTENDED3 3 /* 32 bit addressing for SPI */
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#define CTRL_EXTENDED2 2 /* 32 bit addressing for SPI */
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#define CTRL_EXTENDED1 1 /* 32 bit addressing for SPI */
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#define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */
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/* Interrupt Control and Status Register */
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#define R_INTR_CTRL (0x08 / 4)
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#define INTR_CTRL_DMA_STATUS (1 << 11)
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#define INTR_CTRL_CMD_ABORT_STATUS (1 << 10)
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#define INTR_CTRL_WRITE_PROTECT_STATUS (1 << 9)
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#define INTR_CTRL_DMA_EN (1 << 3)
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#define INTR_CTRL_CMD_ABORT_EN (1 << 2)
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#define INTR_CTRL_WRITE_PROTECT_EN (1 << 1)
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2020-12-10 12:11:03 +01:00
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/* Command Control Register */
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#define R_CE_CMD_CTRL (0x0C / 4)
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#define CTRL_ADDR_BYTE0_DISABLE_SHIFT 4
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#define CTRL_DATA_BYTE0_DISABLE_SHIFT 0
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#define aspeed_smc_addr_byte_enabled(s, i) \
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(!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_ADDR_BYTE0_DISABLE_SHIFT + (i)))))
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#define aspeed_smc_data_byte_enabled(s, i) \
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(!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_DATA_BYTE0_DISABLE_SHIFT + (i)))))
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2016-07-04 14:06:37 +02:00
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/* CEx Control Register */
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#define R_CTRL0 (0x10 / 4)
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2019-09-25 16:32:38 +02:00
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#define CTRL_IO_QPI (1 << 31)
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#define CTRL_IO_QUAD_DATA (1 << 30)
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2018-06-26 18:50:39 +02:00
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#define CTRL_IO_DUAL_DATA (1 << 29)
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#define CTRL_IO_DUAL_ADDR_DATA (1 << 28) /* Includes dummies */
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2019-09-25 16:32:38 +02:00
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#define CTRL_IO_QUAD_ADDR_DATA (1 << 28) /* Includes dummies */
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2016-07-04 14:06:37 +02:00
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#define CTRL_CMD_SHIFT 16
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#define CTRL_CMD_MASK 0xff
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2017-01-27 16:20:20 +01:00
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#define CTRL_DUMMY_HIGH_SHIFT 14
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2017-01-20 12:15:08 +01:00
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#define CTRL_AST2400_SPI_4BYTE (1 << 13)
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2019-09-04 09:05:02 +02:00
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#define CE_CTRL_CLOCK_FREQ_SHIFT 8
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#define CE_CTRL_CLOCK_FREQ_MASK 0xf
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#define CE_CTRL_CLOCK_FREQ(div) \
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(((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT)
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2017-01-27 16:20:20 +01:00
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#define CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */
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2016-07-04 14:06:37 +02:00
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#define CTRL_CE_STOP_ACTIVE (1 << 2)
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#define CTRL_CMD_MODE_MASK 0x3
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#define CTRL_READMODE 0x0
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#define CTRL_FREADMODE 0x1
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#define CTRL_WRITEMODE 0x2
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#define CTRL_USERMODE 0x3
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#define R_CTRL1 (0x14 / 4)
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#define R_CTRL2 (0x18 / 4)
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#define R_CTRL3 (0x1C / 4)
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#define R_CTRL4 (0x20 / 4)
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/* CEx Segment Address Register */
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#define R_SEG_ADDR0 (0x30 / 4)
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2016-10-17 20:22:17 +02:00
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#define SEG_END_SHIFT 24 /* 8MB units */
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#define SEG_END_MASK 0xff
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2016-07-04 14:06:37 +02:00
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#define SEG_START_SHIFT 16 /* address bit [A29-A23] */
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2016-10-17 20:22:17 +02:00
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#define SEG_START_MASK 0xff
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2016-07-04 14:06:37 +02:00
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#define R_SEG_ADDR1 (0x34 / 4)
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#define R_SEG_ADDR2 (0x38 / 4)
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#define R_SEG_ADDR3 (0x3C / 4)
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#define R_SEG_ADDR4 (0x40 / 4)
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/* Misc Control Register #1 */
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#define R_MISC_CTRL1 (0x50 / 4)
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2019-01-29 12:46:05 +01:00
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/* SPI dummy cycle data */
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#define R_DUMMY_DATA (0x54 / 4)
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2016-07-04 14:06:37 +02:00
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/* DMA Control/Status Register */
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#define R_DMA_CTRL (0x80 / 4)
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#define DMA_CTRL_DELAY_MASK 0xf
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#define DMA_CTRL_DELAY_SHIFT 8
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#define DMA_CTRL_FREQ_MASK 0xf
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#define DMA_CTRL_FREQ_SHIFT 4
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2019-09-04 09:05:02 +02:00
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#define DMA_CTRL_CALIB (1 << 3)
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2016-07-04 14:06:37 +02:00
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#define DMA_CTRL_CKSUM (1 << 2)
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2019-09-04 09:05:01 +02:00
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#define DMA_CTRL_WRITE (1 << 1)
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#define DMA_CTRL_ENABLE (1 << 0)
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2016-07-04 14:06:37 +02:00
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/* DMA Flash Side Address */
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#define R_DMA_FLASH_ADDR (0x84 / 4)
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/* DMA DRAM Side Address */
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#define R_DMA_DRAM_ADDR (0x88 / 4)
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/* DMA Length Register */
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#define R_DMA_LEN (0x8C / 4)
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/* Checksum Calculation Result */
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#define R_DMA_CHECKSUM (0x90 / 4)
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2019-11-19 15:12:06 +01:00
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/* Read Timing Compensation Register */
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2016-07-04 14:06:37 +02:00
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#define R_TIMINGS (0x94 / 4)
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2019-09-25 16:32:38 +02:00
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/* SPI controller registers and bits (AST2400) */
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2016-07-04 14:06:37 +02:00
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#define R_SPI_CONF (0x00 / 4)
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#define SPI_CONF_ENABLE_W0 0
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#define R_SPI_CTRL0 (0x4 / 4)
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#define R_SPI_MISC_CTRL (0x10 / 4)
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#define R_SPI_TIMINGS (0x14 / 4)
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2017-01-20 12:15:08 +01:00
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#define ASPEED_SMC_R_SPI_MAX (0x20 / 4)
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#define ASPEED_SMC_R_SMC_MAX (0x20 / 4)
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2016-10-17 20:22:16 +02:00
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#define ASPEED_SOC_SMC_FLASH_BASE 0x10000000
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#define ASPEED_SOC_FMC_FLASH_BASE 0x20000000
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#define ASPEED_SOC_SPI_FLASH_BASE 0x30000000
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2016-10-17 20:22:16 +02:00
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#define ASPEED_SOC_SPI2_FLASH_BASE 0x38000000
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2016-10-17 20:22:16 +02:00
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2019-09-04 09:05:01 +02:00
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/*
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* DMA DRAM addresses should be 4 bytes aligned and the valid address
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* range is 0x40000000 - 0x5FFFFFFF (AST2400)
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* 0x80000000 - 0xBFFFFFFF (AST2500)
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*
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* DMA flash addresses should be 4 bytes aligned and the valid address
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* range is 0x20000000 - 0x2FFFFFFF.
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*
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* DMA length is from 4 bytes to 32MB
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* 0: 4 bytes
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* 0x7FFFFF: 32M bytes
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*/
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2021-05-01 10:03:51 +02:00
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#define DMA_DRAM_ADDR(s, val) ((val) & (s)->ctrl->dma_dram_mask)
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2019-09-04 09:05:01 +02:00
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#define DMA_FLASH_ADDR(s, val) ((s)->ctrl->flash_window_base | \
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((val) & (s)->ctrl->dma_flash_mask))
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#define DMA_LENGTH(val) ((val) & 0x01FFFFFC)
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2017-01-20 12:15:08 +01:00
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/* Flash opcodes. */
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#define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */
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2019-01-29 12:46:05 +01:00
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#define SNOOP_OFF 0xFF
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#define SNOOP_START 0x0
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2016-07-04 14:06:38 +02:00
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/*
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2020-10-12 14:49:53 +02:00
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* Default segments mapping addresses and size for each peripheral per
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2016-07-04 14:06:38 +02:00
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* controller. These can be changed when board is initialized with the
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2016-10-17 20:22:17 +02:00
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* Segment Address Registers.
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2016-07-04 14:06:38 +02:00
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*/
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static const AspeedSegments aspeed_segments_legacy[] = {
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{ 0x10000000, 32 * 1024 * 1024 },
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};
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static const AspeedSegments aspeed_segments_fmc[] = {
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2016-10-17 20:22:16 +02:00
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{ 0x20000000, 64 * 1024 * 1024 }, /* start address is readonly */
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2016-07-04 14:06:38 +02:00
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{ 0x24000000, 32 * 1024 * 1024 },
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{ 0x26000000, 32 * 1024 * 1024 },
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{ 0x28000000, 32 * 1024 * 1024 },
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{ 0x2A000000, 32 * 1024 * 1024 }
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};
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static const AspeedSegments aspeed_segments_spi[] = {
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{ 0x30000000, 64 * 1024 * 1024 },
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};
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2016-10-17 20:22:16 +02:00
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static const AspeedSegments aspeed_segments_ast2500_fmc[] = {
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{ 0x20000000, 128 * 1024 * 1024 }, /* start address is readonly */
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{ 0x28000000, 32 * 1024 * 1024 },
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{ 0x2A000000, 32 * 1024 * 1024 },
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};
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static const AspeedSegments aspeed_segments_ast2500_spi1[] = {
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{ 0x30000000, 32 * 1024 * 1024 }, /* start address is readonly */
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{ 0x32000000, 96 * 1024 * 1024 }, /* end address is readonly */
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};
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static const AspeedSegments aspeed_segments_ast2500_spi2[] = {
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{ 0x38000000, 32 * 1024 * 1024 }, /* start address is readonly */
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{ 0x3A000000, 96 * 1024 * 1024 }, /* end address is readonly */
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};
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2019-09-25 16:32:37 +02:00
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static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s,
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const AspeedSegments *seg);
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static void aspeed_smc_reg_to_segment(const AspeedSMCState *s, uint32_t reg,
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AspeedSegments *seg);
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2016-10-17 20:22:16 +02:00
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2019-09-25 16:32:38 +02:00
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/*
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* AST2600 definitions
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*/
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#define ASPEED26_SOC_FMC_FLASH_BASE 0x20000000
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#define ASPEED26_SOC_SPI_FLASH_BASE 0x30000000
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#define ASPEED26_SOC_SPI2_FLASH_BASE 0x50000000
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static const AspeedSegments aspeed_segments_ast2600_fmc[] = {
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{ 0x0, 128 * MiB }, /* start address is readonly */
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2020-09-01 14:21:51 +02:00
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{ 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
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2019-09-25 16:32:38 +02:00
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{ 0x0, 0 }, /* disabled */
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};
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static const AspeedSegments aspeed_segments_ast2600_spi1[] = {
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{ 0x0, 128 * MiB }, /* start address is readonly */
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{ 0x0, 0 }, /* disabled */
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};
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static const AspeedSegments aspeed_segments_ast2600_spi2[] = {
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{ 0x0, 128 * MiB }, /* start address is readonly */
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{ 0x0, 0 }, /* disabled */
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{ 0x0, 0 }, /* disabled */
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};
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static uint32_t aspeed_2600_smc_segment_to_reg(const AspeedSMCState *s,
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const AspeedSegments *seg);
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static void aspeed_2600_smc_reg_to_segment(const AspeedSMCState *s,
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uint32_t reg, AspeedSegments *seg);
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2016-07-04 14:06:37 +02:00
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static const AspeedSMCController controllers[] = {
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2017-01-20 12:15:07 +01:00
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{
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2019-09-04 09:05:00 +02:00
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.name = "aspeed.smc-ast2400",
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2017-01-20 12:15:07 +01:00
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.r_conf = R_CONF,
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.r_ce_ctrl = R_CE_CTRL,
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.r_ctrl0 = R_CTRL0,
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.r_timings = R_TIMINGS,
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2019-11-19 15:12:06 +01:00
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.nregs_timings = 1,
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2017-01-20 12:15:07 +01:00
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.conf_enable_w0 = CONF_ENABLE_W0,
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2020-10-12 14:49:53 +02:00
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.max_peripherals = 1,
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2017-01-20 12:15:07 +01:00
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.segments = aspeed_segments_legacy,
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.flash_window_base = ASPEED_SOC_SMC_FLASH_BASE,
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.flash_window_size = 0x6000000,
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.has_dma = false,
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2017-01-20 12:15:08 +01:00
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.nregs = ASPEED_SMC_R_SMC_MAX,
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2019-09-25 16:32:37 +02:00
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.segment_to_reg = aspeed_smc_segment_to_reg,
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.reg_to_segment = aspeed_smc_reg_to_segment,
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2017-01-20 12:15:07 +01:00
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|
}, {
|
2019-09-04 09:05:00 +02:00
|
|
|
.name = "aspeed.fmc-ast2400",
|
2017-01-20 12:15:07 +01:00
|
|
|
.r_conf = R_CONF,
|
|
|
|
.r_ce_ctrl = R_CE_CTRL,
|
|
|
|
.r_ctrl0 = R_CTRL0,
|
|
|
|
.r_timings = R_TIMINGS,
|
2019-11-19 15:12:06 +01:00
|
|
|
.nregs_timings = 1,
|
2017-01-20 12:15:07 +01:00
|
|
|
.conf_enable_w0 = CONF_ENABLE_W0,
|
2020-10-12 14:49:53 +02:00
|
|
|
.max_peripherals = 5,
|
2017-01-20 12:15:07 +01:00
|
|
|
.segments = aspeed_segments_fmc,
|
|
|
|
.flash_window_base = ASPEED_SOC_FMC_FLASH_BASE,
|
|
|
|
.flash_window_size = 0x10000000,
|
|
|
|
.has_dma = true,
|
2019-09-04 09:05:01 +02:00
|
|
|
.dma_flash_mask = 0x0FFFFFFC,
|
|
|
|
.dma_dram_mask = 0x1FFFFFFC,
|
2017-01-20 12:15:08 +01:00
|
|
|
.nregs = ASPEED_SMC_R_MAX,
|
2019-09-25 16:32:37 +02:00
|
|
|
.segment_to_reg = aspeed_smc_segment_to_reg,
|
|
|
|
.reg_to_segment = aspeed_smc_reg_to_segment,
|
2017-01-20 12:15:07 +01:00
|
|
|
}, {
|
2019-09-04 09:05:00 +02:00
|
|
|
.name = "aspeed.spi1-ast2400",
|
2017-01-20 12:15:07 +01:00
|
|
|
.r_conf = R_SPI_CONF,
|
|
|
|
.r_ce_ctrl = 0xff,
|
|
|
|
.r_ctrl0 = R_SPI_CTRL0,
|
|
|
|
.r_timings = R_SPI_TIMINGS,
|
2019-11-19 15:12:06 +01:00
|
|
|
.nregs_timings = 1,
|
2017-01-20 12:15:07 +01:00
|
|
|
.conf_enable_w0 = SPI_CONF_ENABLE_W0,
|
2020-10-12 14:49:53 +02:00
|
|
|
.max_peripherals = 1,
|
2017-01-20 12:15:07 +01:00
|
|
|
.segments = aspeed_segments_spi,
|
|
|
|
.flash_window_base = ASPEED_SOC_SPI_FLASH_BASE,
|
|
|
|
.flash_window_size = 0x10000000,
|
|
|
|
.has_dma = false,
|
2017-01-20 12:15:08 +01:00
|
|
|
.nregs = ASPEED_SMC_R_SPI_MAX,
|
2019-09-25 16:32:37 +02:00
|
|
|
.segment_to_reg = aspeed_smc_segment_to_reg,
|
|
|
|
.reg_to_segment = aspeed_smc_reg_to_segment,
|
2017-01-20 12:15:07 +01:00
|
|
|
}, {
|
2019-09-04 09:05:00 +02:00
|
|
|
.name = "aspeed.fmc-ast2500",
|
2017-01-20 12:15:07 +01:00
|
|
|
.r_conf = R_CONF,
|
|
|
|
.r_ce_ctrl = R_CE_CTRL,
|
|
|
|
.r_ctrl0 = R_CTRL0,
|
|
|
|
.r_timings = R_TIMINGS,
|
2019-11-19 15:12:06 +01:00
|
|
|
.nregs_timings = 1,
|
2017-01-20 12:15:07 +01:00
|
|
|
.conf_enable_w0 = CONF_ENABLE_W0,
|
2020-10-12 14:49:53 +02:00
|
|
|
.max_peripherals = 3,
|
2017-01-20 12:15:07 +01:00
|
|
|
.segments = aspeed_segments_ast2500_fmc,
|
|
|
|
.flash_window_base = ASPEED_SOC_FMC_FLASH_BASE,
|
|
|
|
.flash_window_size = 0x10000000,
|
|
|
|
.has_dma = true,
|
2019-09-04 09:05:01 +02:00
|
|
|
.dma_flash_mask = 0x0FFFFFFC,
|
|
|
|
.dma_dram_mask = 0x3FFFFFFC,
|
2017-01-20 12:15:08 +01:00
|
|
|
.nregs = ASPEED_SMC_R_MAX,
|
2019-09-25 16:32:37 +02:00
|
|
|
.segment_to_reg = aspeed_smc_segment_to_reg,
|
|
|
|
.reg_to_segment = aspeed_smc_reg_to_segment,
|
2017-01-20 12:15:07 +01:00
|
|
|
}, {
|
2019-09-04 09:05:00 +02:00
|
|
|
.name = "aspeed.spi1-ast2500",
|
2017-01-20 12:15:07 +01:00
|
|
|
.r_conf = R_CONF,
|
|
|
|
.r_ce_ctrl = R_CE_CTRL,
|
|
|
|
.r_ctrl0 = R_CTRL0,
|
|
|
|
.r_timings = R_TIMINGS,
|
2019-11-19 15:12:06 +01:00
|
|
|
.nregs_timings = 1,
|
2017-01-20 12:15:07 +01:00
|
|
|
.conf_enable_w0 = CONF_ENABLE_W0,
|
2020-10-12 14:49:53 +02:00
|
|
|
.max_peripherals = 2,
|
2017-01-20 12:15:07 +01:00
|
|
|
.segments = aspeed_segments_ast2500_spi1,
|
|
|
|
.flash_window_base = ASPEED_SOC_SPI_FLASH_BASE,
|
|
|
|
.flash_window_size = 0x8000000,
|
|
|
|
.has_dma = false,
|
2017-01-20 12:15:08 +01:00
|
|
|
.nregs = ASPEED_SMC_R_MAX,
|
2019-09-25 16:32:37 +02:00
|
|
|
.segment_to_reg = aspeed_smc_segment_to_reg,
|
|
|
|
.reg_to_segment = aspeed_smc_reg_to_segment,
|
2017-01-20 12:15:07 +01:00
|
|
|
}, {
|
2019-09-04 09:05:00 +02:00
|
|
|
.name = "aspeed.spi2-ast2500",
|
2017-01-20 12:15:07 +01:00
|
|
|
.r_conf = R_CONF,
|
|
|
|
.r_ce_ctrl = R_CE_CTRL,
|
|
|
|
.r_ctrl0 = R_CTRL0,
|
|
|
|
.r_timings = R_TIMINGS,
|
2019-11-19 15:12:06 +01:00
|
|
|
.nregs_timings = 1,
|
2017-01-20 12:15:07 +01:00
|
|
|
.conf_enable_w0 = CONF_ENABLE_W0,
|
2020-10-12 14:49:53 +02:00
|
|
|
.max_peripherals = 2,
|
2017-01-20 12:15:07 +01:00
|
|
|
.segments = aspeed_segments_ast2500_spi2,
|
|
|
|
.flash_window_base = ASPEED_SOC_SPI2_FLASH_BASE,
|
|
|
|
.flash_window_size = 0x8000000,
|
|
|
|
.has_dma = false,
|
2017-01-20 12:15:08 +01:00
|
|
|
.nregs = ASPEED_SMC_R_MAX,
|
2019-09-25 16:32:37 +02:00
|
|
|
.segment_to_reg = aspeed_smc_segment_to_reg,
|
|
|
|
.reg_to_segment = aspeed_smc_reg_to_segment,
|
2019-09-25 16:32:38 +02:00
|
|
|
}, {
|
|
|
|
.name = "aspeed.fmc-ast2600",
|
|
|
|
.r_conf = R_CONF,
|
|
|
|
.r_ce_ctrl = R_CE_CTRL,
|
|
|
|
.r_ctrl0 = R_CTRL0,
|
|
|
|
.r_timings = R_TIMINGS,
|
2019-11-19 15:12:06 +01:00
|
|
|
.nregs_timings = 1,
|
2019-09-25 16:32:38 +02:00
|
|
|
.conf_enable_w0 = CONF_ENABLE_W0,
|
2020-10-12 14:49:53 +02:00
|
|
|
.max_peripherals = 3,
|
2019-09-25 16:32:38 +02:00
|
|
|
.segments = aspeed_segments_ast2600_fmc,
|
|
|
|
.flash_window_base = ASPEED26_SOC_FMC_FLASH_BASE,
|
|
|
|
.flash_window_size = 0x10000000,
|
|
|
|
.has_dma = true,
|
2020-03-23 18:22:30 +01:00
|
|
|
.dma_flash_mask = 0x0FFFFFFC,
|
|
|
|
.dma_dram_mask = 0x3FFFFFFC,
|
2019-09-25 16:32:38 +02:00
|
|
|
.nregs = ASPEED_SMC_R_MAX,
|
|
|
|
.segment_to_reg = aspeed_2600_smc_segment_to_reg,
|
|
|
|
.reg_to_segment = aspeed_2600_smc_reg_to_segment,
|
|
|
|
}, {
|
|
|
|
.name = "aspeed.spi1-ast2600",
|
|
|
|
.r_conf = R_CONF,
|
|
|
|
.r_ce_ctrl = R_CE_CTRL,
|
|
|
|
.r_ctrl0 = R_CTRL0,
|
|
|
|
.r_timings = R_TIMINGS,
|
2019-11-19 15:12:06 +01:00
|
|
|
.nregs_timings = 2,
|
2019-09-25 16:32:38 +02:00
|
|
|
.conf_enable_w0 = CONF_ENABLE_W0,
|
2020-10-12 14:49:53 +02:00
|
|
|
.max_peripherals = 2,
|
2019-09-25 16:32:38 +02:00
|
|
|
.segments = aspeed_segments_ast2600_spi1,
|
|
|
|
.flash_window_base = ASPEED26_SOC_SPI_FLASH_BASE,
|
|
|
|
.flash_window_size = 0x10000000,
|
2020-03-23 18:22:30 +01:00
|
|
|
.has_dma = true,
|
|
|
|
.dma_flash_mask = 0x0FFFFFFC,
|
|
|
|
.dma_dram_mask = 0x3FFFFFFC,
|
2019-09-25 16:32:38 +02:00
|
|
|
.nregs = ASPEED_SMC_R_MAX,
|
|
|
|
.segment_to_reg = aspeed_2600_smc_segment_to_reg,
|
|
|
|
.reg_to_segment = aspeed_2600_smc_reg_to_segment,
|
|
|
|
}, {
|
|
|
|
.name = "aspeed.spi2-ast2600",
|
|
|
|
.r_conf = R_CONF,
|
|
|
|
.r_ce_ctrl = R_CE_CTRL,
|
|
|
|
.r_ctrl0 = R_CTRL0,
|
|
|
|
.r_timings = R_TIMINGS,
|
2019-11-19 15:12:06 +01:00
|
|
|
.nregs_timings = 3,
|
2019-09-25 16:32:38 +02:00
|
|
|
.conf_enable_w0 = CONF_ENABLE_W0,
|
2020-10-12 14:49:53 +02:00
|
|
|
.max_peripherals = 3,
|
2019-09-25 16:32:38 +02:00
|
|
|
.segments = aspeed_segments_ast2600_spi2,
|
|
|
|
.flash_window_base = ASPEED26_SOC_SPI2_FLASH_BASE,
|
|
|
|
.flash_window_size = 0x10000000,
|
2020-03-23 18:22:30 +01:00
|
|
|
.has_dma = true,
|
|
|
|
.dma_flash_mask = 0x0FFFFFFC,
|
|
|
|
.dma_dram_mask = 0x3FFFFFFC,
|
2019-09-25 16:32:38 +02:00
|
|
|
.nregs = ASPEED_SMC_R_MAX,
|
|
|
|
.segment_to_reg = aspeed_2600_smc_segment_to_reg,
|
|
|
|
.reg_to_segment = aspeed_2600_smc_reg_to_segment,
|
2017-01-20 12:15:07 +01:00
|
|
|
},
|
2016-07-04 14:06:38 +02:00
|
|
|
};
|
|
|
|
|
2016-10-17 20:22:17 +02:00
|
|
|
/*
|
2019-09-25 16:32:37 +02:00
|
|
|
* The Segment Registers of the AST2400 and AST2500 have a 8MB
|
2020-10-12 14:49:53 +02:00
|
|
|
* unit. The address range of a flash SPI peripheral is encoded with
|
2019-09-25 16:32:37 +02:00
|
|
|
* absolute addresses which should be part of the overall controller
|
|
|
|
* window.
|
2016-10-17 20:22:17 +02:00
|
|
|
*/
|
2019-09-25 16:32:37 +02:00
|
|
|
static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s,
|
|
|
|
const AspeedSegments *seg)
|
2016-10-17 20:22:17 +02:00
|
|
|
{
|
|
|
|
uint32_t reg = 0;
|
|
|
|
reg |= ((seg->addr >> 23) & SEG_START_MASK) << SEG_START_SHIFT;
|
|
|
|
reg |= (((seg->addr + seg->size) >> 23) & SEG_END_MASK) << SEG_END_SHIFT;
|
|
|
|
return reg;
|
|
|
|
}
|
|
|
|
|
2019-09-25 16:32:37 +02:00
|
|
|
static void aspeed_smc_reg_to_segment(const AspeedSMCState *s,
|
|
|
|
uint32_t reg, AspeedSegments *seg)
|
2016-10-17 20:22:17 +02:00
|
|
|
{
|
|
|
|
seg->addr = ((reg >> SEG_START_SHIFT) & SEG_START_MASK) << 23;
|
|
|
|
seg->size = (((reg >> SEG_END_SHIFT) & SEG_END_MASK) << 23) - seg->addr;
|
|
|
|
}
|
|
|
|
|
2019-09-25 16:32:38 +02:00
|
|
|
/*
|
|
|
|
* The Segment Registers of the AST2600 have a 1MB unit. The address
|
2020-10-12 14:49:53 +02:00
|
|
|
* range of a flash SPI peripheral is encoded with offsets in the overall
|
2019-09-25 16:32:38 +02:00
|
|
|
* controller window. The previous SoC AST2400 and AST2500 used
|
|
|
|
* absolute addresses. Only bits [27:20] are relevant and the end
|
|
|
|
* address is an upper bound limit.
|
|
|
|
*/
|
|
|
|
#define AST2600_SEG_ADDR_MASK 0x0ff00000
|
|
|
|
|
|
|
|
static uint32_t aspeed_2600_smc_segment_to_reg(const AspeedSMCState *s,
|
|
|
|
const AspeedSegments *seg)
|
|
|
|
{
|
|
|
|
uint32_t reg = 0;
|
|
|
|
|
|
|
|
/* Disabled segments have a nil register */
|
|
|
|
if (!seg->size) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
reg |= (seg->addr & AST2600_SEG_ADDR_MASK) >> 16; /* start offset */
|
|
|
|
reg |= (seg->addr + seg->size - 1) & AST2600_SEG_ADDR_MASK; /* end offset */
|
|
|
|
return reg;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_2600_smc_reg_to_segment(const AspeedSMCState *s,
|
|
|
|
uint32_t reg, AspeedSegments *seg)
|
|
|
|
{
|
|
|
|
uint32_t start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK;
|
|
|
|
uint32_t end_offset = reg & AST2600_SEG_ADDR_MASK;
|
|
|
|
|
2019-11-19 15:12:05 +01:00
|
|
|
if (reg) {
|
|
|
|
seg->addr = s->ctrl->flash_window_base + start_offset;
|
|
|
|
seg->size = end_offset + MiB - start_offset;
|
|
|
|
} else {
|
|
|
|
seg->addr = s->ctrl->flash_window_base;
|
|
|
|
seg->size = 0;
|
|
|
|
}
|
2019-09-25 16:32:38 +02:00
|
|
|
}
|
|
|
|
|
2016-10-17 20:22:17 +02:00
|
|
|
static bool aspeed_smc_flash_overlap(const AspeedSMCState *s,
|
|
|
|
const AspeedSegments *new,
|
|
|
|
int cs)
|
|
|
|
{
|
|
|
|
AspeedSegments seg;
|
|
|
|
int i;
|
|
|
|
|
2020-10-12 14:49:53 +02:00
|
|
|
for (i = 0; i < s->ctrl->max_peripherals; i++) {
|
2016-10-17 20:22:17 +02:00
|
|
|
if (i == cs) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2019-09-25 16:32:37 +02:00
|
|
|
s->ctrl->reg_to_segment(s, s->regs[R_SEG_ADDR0 + i], &seg);
|
2016-10-17 20:22:17 +02:00
|
|
|
|
|
|
|
if (new->addr + new->size > seg.addr &&
|
|
|
|
new->addr < seg.addr + seg.size) {
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: new segment CS%d [ 0x%"
|
|
|
|
HWADDR_PRIx" - 0x%"HWADDR_PRIx" ] overlaps with "
|
|
|
|
"CS%d [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n",
|
|
|
|
s->ctrl->name, cs, new->addr, new->addr + new->size,
|
|
|
|
i, seg.addr, seg.addr + seg.size);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2019-11-19 15:12:04 +01:00
|
|
|
static void aspeed_smc_flash_set_segment_region(AspeedSMCState *s, int cs,
|
|
|
|
uint64_t regval)
|
|
|
|
{
|
|
|
|
AspeedSMCFlash *fl = &s->flashes[cs];
|
|
|
|
AspeedSegments seg;
|
|
|
|
|
|
|
|
s->ctrl->reg_to_segment(s, regval, &seg);
|
|
|
|
|
|
|
|
memory_region_transaction_begin();
|
|
|
|
memory_region_set_size(&fl->mmio, seg.size);
|
|
|
|
memory_region_set_address(&fl->mmio, seg.addr - s->ctrl->flash_window_base);
|
2019-11-19 15:12:05 +01:00
|
|
|
memory_region_set_enabled(&fl->mmio, !!seg.size);
|
2019-11-19 15:12:04 +01:00
|
|
|
memory_region_transaction_commit();
|
|
|
|
|
|
|
|
s->regs[R_SEG_ADDR0 + cs] = regval;
|
|
|
|
}
|
|
|
|
|
2016-10-17 20:22:17 +02:00
|
|
|
static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs,
|
|
|
|
uint64_t new)
|
|
|
|
{
|
|
|
|
AspeedSegments seg;
|
|
|
|
|
2019-09-25 16:32:37 +02:00
|
|
|
s->ctrl->reg_to_segment(s, new, &seg);
|
2016-10-17 20:22:17 +02:00
|
|
|
|
2020-02-06 12:26:44 +01:00
|
|
|
trace_aspeed_smc_flash_set_segment(cs, new, seg.addr, seg.addr + seg.size);
|
|
|
|
|
2016-10-17 20:22:17 +02:00
|
|
|
/* The start address of CS0 is read-only */
|
|
|
|
if (cs == 0 && seg.addr != s->ctrl->flash_window_base) {
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: Tried to change CS0 start address to 0x%"
|
|
|
|
HWADDR_PRIx "\n", s->ctrl->name, seg.addr);
|
2016-12-27 15:59:28 +01:00
|
|
|
seg.addr = s->ctrl->flash_window_base;
|
2019-09-25 16:32:37 +02:00
|
|
|
new = s->ctrl->segment_to_reg(s, &seg);
|
2016-10-17 20:22:17 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The end address of the AST2500 spi controllers is also
|
|
|
|
* read-only.
|
|
|
|
*/
|
|
|
|
if ((s->ctrl->segments == aspeed_segments_ast2500_spi1 ||
|
|
|
|
s->ctrl->segments == aspeed_segments_ast2500_spi2) &&
|
2020-10-12 14:49:53 +02:00
|
|
|
cs == s->ctrl->max_peripherals &&
|
2016-10-17 20:22:17 +02:00
|
|
|
seg.addr + seg.size != s->ctrl->segments[cs].addr +
|
|
|
|
s->ctrl->segments[cs].size) {
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: Tried to change CS%d end address to 0x%"
|
2016-12-27 15:59:28 +01:00
|
|
|
HWADDR_PRIx "\n", s->ctrl->name, cs, seg.addr + seg.size);
|
|
|
|
seg.size = s->ctrl->segments[cs].addr + s->ctrl->segments[cs].size -
|
|
|
|
seg.addr;
|
2019-09-25 16:32:37 +02:00
|
|
|
new = s->ctrl->segment_to_reg(s, &seg);
|
2016-10-17 20:22:17 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Keep the segment in the overall flash window */
|
2019-11-19 15:12:05 +01:00
|
|
|
if (seg.size &&
|
|
|
|
(seg.addr + seg.size <= s->ctrl->flash_window_base ||
|
|
|
|
seg.addr > s->ctrl->flash_window_base + s->ctrl->flash_window_size)) {
|
2016-10-17 20:22:17 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: new segment for CS%d is invalid : "
|
|
|
|
"[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n",
|
|
|
|
s->ctrl->name, cs, seg.addr, seg.addr + seg.size);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check start address vs. alignment */
|
2016-12-27 15:59:28 +01:00
|
|
|
if (seg.size && !QEMU_IS_ALIGNED(seg.addr, seg.size)) {
|
2016-10-17 20:22:17 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: new segment for CS%d is not "
|
|
|
|
"aligned : [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n",
|
|
|
|
s->ctrl->name, cs, seg.addr, seg.addr + seg.size);
|
|
|
|
}
|
|
|
|
|
2016-12-27 15:59:28 +01:00
|
|
|
/* And segments should not overlap (in the specs) */
|
|
|
|
aspeed_smc_flash_overlap(s, &seg, cs);
|
2016-10-17 20:22:17 +02:00
|
|
|
|
|
|
|
/* All should be fine now to move the region */
|
2019-11-19 15:12:04 +01:00
|
|
|
aspeed_smc_flash_set_segment_region(s, cs, new);
|
2016-10-17 20:22:17 +02:00
|
|
|
}
|
|
|
|
|
2016-07-04 14:06:38 +02:00
|
|
|
static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr,
|
|
|
|
unsigned size)
|
|
|
|
{
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: To 0x%" HWADDR_PRIx " of size %u"
|
|
|
|
PRIx64 "\n", __func__, addr, size);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_smc_flash_default_write(void *opaque, hwaddr addr,
|
|
|
|
uint64_t data, unsigned size)
|
|
|
|
{
|
2018-09-25 15:02:33 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: To 0x%" HWADDR_PRIx " of size %u: 0x%"
|
|
|
|
PRIx64 "\n", __func__, addr, size, data);
|
2016-07-04 14:06:38 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps aspeed_smc_flash_default_ops = {
|
|
|
|
.read = aspeed_smc_flash_default_read,
|
|
|
|
.write = aspeed_smc_flash_default_write,
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 1,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2017-01-20 12:15:07 +01:00
|
|
|
static inline int aspeed_smc_flash_mode(const AspeedSMCFlash *fl)
|
2016-07-04 14:06:38 +02:00
|
|
|
{
|
2017-01-20 12:15:07 +01:00
|
|
|
const AspeedSMCState *s = fl->controller;
|
|
|
|
|
|
|
|
return s->regs[s->r_ctrl0 + fl->id] & CTRL_CMD_MODE_MASK;
|
2016-07-04 14:06:38 +02:00
|
|
|
}
|
|
|
|
|
2017-01-20 12:15:08 +01:00
|
|
|
static inline bool aspeed_smc_is_writable(const AspeedSMCFlash *fl)
|
2016-07-04 14:06:38 +02:00
|
|
|
{
|
2017-01-20 12:15:08 +01:00
|
|
|
const AspeedSMCState *s = fl->controller;
|
|
|
|
|
|
|
|
return s->regs[s->r_conf] & (1 << (s->conf_enable_w0 + fl->id));
|
2016-07-04 14:06:38 +02:00
|
|
|
}
|
|
|
|
|
2017-01-20 12:15:08 +01:00
|
|
|
static inline int aspeed_smc_flash_cmd(const AspeedSMCFlash *fl)
|
2016-07-04 14:06:38 +02:00
|
|
|
{
|
2017-01-20 12:15:07 +01:00
|
|
|
const AspeedSMCState *s = fl->controller;
|
2017-01-20 12:15:08 +01:00
|
|
|
int cmd = (s->regs[s->r_ctrl0 + fl->id] >> CTRL_CMD_SHIFT) & CTRL_CMD_MASK;
|
2017-01-20 12:15:07 +01:00
|
|
|
|
2019-09-25 16:32:38 +02:00
|
|
|
/*
|
|
|
|
* In read mode, the default SPI command is READ (0x3). In other
|
|
|
|
* modes, the command should necessarily be defined
|
|
|
|
*
|
|
|
|
* TODO: add support for READ4 (0x13) on AST2600
|
|
|
|
*/
|
2017-01-20 12:15:08 +01:00
|
|
|
if (aspeed_smc_flash_mode(fl) == CTRL_READMODE) {
|
|
|
|
cmd = SPI_OP_READ;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!cmd) {
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: no command defined for mode %d\n",
|
|
|
|
__func__, aspeed_smc_flash_mode(fl));
|
|
|
|
}
|
|
|
|
|
|
|
|
return cmd;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int aspeed_smc_flash_is_4byte(const AspeedSMCFlash *fl)
|
|
|
|
{
|
|
|
|
const AspeedSMCState *s = fl->controller;
|
|
|
|
|
|
|
|
if (s->ctrl->segments == aspeed_segments_spi) {
|
|
|
|
return s->regs[s->r_ctrl0] & CTRL_AST2400_SPI_4BYTE;
|
|
|
|
} else {
|
|
|
|
return s->regs[s->r_ce_ctrl] & (1 << (CTRL_EXTENDED0 + fl->id));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-02-06 12:26:45 +01:00
|
|
|
static void aspeed_smc_flash_do_select(AspeedSMCFlash *fl, bool unselect)
|
2017-01-20 12:15:08 +01:00
|
|
|
{
|
2020-02-06 12:26:45 +01:00
|
|
|
AspeedSMCState *s = fl->controller;
|
|
|
|
|
|
|
|
trace_aspeed_smc_flash_select(fl->id, unselect ? "un" : "");
|
2017-01-20 12:15:08 +01:00
|
|
|
|
2020-02-06 12:26:45 +01:00
|
|
|
qemu_set_irq(s->cs_lines[fl->id], unselect);
|
2017-01-20 12:15:08 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_smc_flash_select(AspeedSMCFlash *fl)
|
|
|
|
{
|
2020-02-06 12:26:45 +01:00
|
|
|
aspeed_smc_flash_do_select(fl, false);
|
2017-01-20 12:15:08 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_smc_flash_unselect(AspeedSMCFlash *fl)
|
|
|
|
{
|
2020-02-06 12:26:45 +01:00
|
|
|
aspeed_smc_flash_do_select(fl, true);
|
2017-01-20 12:15:08 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
|
|
|
|
uint32_t addr)
|
|
|
|
{
|
|
|
|
const AspeedSMCState *s = fl->controller;
|
|
|
|
AspeedSegments seg;
|
|
|
|
|
2019-09-25 16:32:37 +02:00
|
|
|
s->ctrl->reg_to_segment(s, s->regs[R_SEG_ADDR0 + fl->id], &seg);
|
2017-02-10 18:40:30 +01:00
|
|
|
if ((addr % seg.size) != addr) {
|
2017-01-20 12:15:08 +01:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: invalid address 0x%08x for CS%d segment : "
|
|
|
|
"[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n",
|
|
|
|
s->ctrl->name, addr, fl->id, seg.addr,
|
|
|
|
seg.addr + seg.size);
|
2017-02-10 18:40:30 +01:00
|
|
|
addr %= seg.size;
|
2017-01-20 12:15:08 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
return addr;
|
|
|
|
}
|
|
|
|
|
2017-01-27 16:20:20 +01:00
|
|
|
static int aspeed_smc_flash_dummies(const AspeedSMCFlash *fl)
|
|
|
|
{
|
|
|
|
const AspeedSMCState *s = fl->controller;
|
|
|
|
uint32_t r_ctrl0 = s->regs[s->r_ctrl0 + fl->id];
|
|
|
|
uint32_t dummy_high = (r_ctrl0 >> CTRL_DUMMY_HIGH_SHIFT) & 0x1;
|
|
|
|
uint32_t dummy_low = (r_ctrl0 >> CTRL_DUMMY_LOW_SHIFT) & 0x3;
|
2018-06-26 18:50:39 +02:00
|
|
|
uint32_t dummies = ((dummy_high << 2) | dummy_low) * 8;
|
2017-01-27 16:20:20 +01:00
|
|
|
|
2018-06-26 18:50:39 +02:00
|
|
|
if (r_ctrl0 & CTRL_IO_DUAL_ADDR_DATA) {
|
|
|
|
dummies /= 2;
|
|
|
|
}
|
|
|
|
|
|
|
|
return dummies;
|
2017-01-27 16:20:20 +01:00
|
|
|
}
|
|
|
|
|
2018-06-26 18:50:39 +02:00
|
|
|
static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr)
|
2017-01-20 12:15:08 +01:00
|
|
|
{
|
|
|
|
const AspeedSMCState *s = fl->controller;
|
|
|
|
uint8_t cmd = aspeed_smc_flash_cmd(fl);
|
2020-12-10 12:11:03 +01:00
|
|
|
int i = aspeed_smc_flash_is_4byte(fl) ? 4 : 3;
|
2017-01-20 12:15:08 +01:00
|
|
|
|
|
|
|
/* Flash access can not exceed CS segment */
|
|
|
|
addr = aspeed_smc_check_segment_addr(fl, addr);
|
|
|
|
|
|
|
|
ssi_transfer(s->spi, cmd);
|
2020-12-10 12:11:03 +01:00
|
|
|
while (i--) {
|
|
|
|
if (aspeed_smc_addr_byte_enabled(s, i)) {
|
|
|
|
ssi_transfer(s->spi, (addr >> (i * 8)) & 0xff);
|
|
|
|
}
|
2017-01-20 12:15:08 +01:00
|
|
|
}
|
2018-06-26 18:50:39 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Use fake transfers to model dummy bytes. The value should
|
|
|
|
* be configured to some non-zero value in fast read mode and
|
|
|
|
* zero in read mode. But, as the HW allows inconsistent
|
|
|
|
* settings, let's check for fast read mode.
|
|
|
|
*/
|
|
|
|
if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) {
|
|
|
|
for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) {
|
2019-01-29 12:46:05 +01:00
|
|
|
ssi_transfer(fl->controller->spi, s->regs[R_DUMMY_DATA] & 0xff);
|
2018-06-26 18:50:39 +02:00
|
|
|
}
|
|
|
|
}
|
2016-07-04 14:06:38 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size)
|
|
|
|
{
|
|
|
|
AspeedSMCFlash *fl = opaque;
|
2017-01-20 12:15:08 +01:00
|
|
|
AspeedSMCState *s = fl->controller;
|
2016-07-04 14:06:38 +02:00
|
|
|
uint64_t ret = 0;
|
|
|
|
int i;
|
|
|
|
|
2017-01-20 12:15:08 +01:00
|
|
|
switch (aspeed_smc_flash_mode(fl)) {
|
|
|
|
case CTRL_USERMODE:
|
2016-07-04 14:06:38 +02:00
|
|
|
for (i = 0; i < size; i++) {
|
|
|
|
ret |= ssi_transfer(s->spi, 0x0) << (8 * i);
|
|
|
|
}
|
2017-01-20 12:15:08 +01:00
|
|
|
break;
|
|
|
|
case CTRL_READMODE:
|
|
|
|
case CTRL_FREADMODE:
|
|
|
|
aspeed_smc_flash_select(fl);
|
2018-06-26 18:50:39 +02:00
|
|
|
aspeed_smc_flash_setup(fl, addr);
|
2017-01-27 16:20:20 +01:00
|
|
|
|
2017-01-20 12:15:08 +01:00
|
|
|
for (i = 0; i < size; i++) {
|
|
|
|
ret |= ssi_transfer(s->spi, 0x0) << (8 * i);
|
|
|
|
}
|
|
|
|
|
|
|
|
aspeed_smc_flash_unselect(fl);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid flash mode %d\n",
|
|
|
|
__func__, aspeed_smc_flash_mode(fl));
|
2016-07-04 14:06:38 +02:00
|
|
|
}
|
|
|
|
|
2020-02-06 12:26:44 +01:00
|
|
|
trace_aspeed_smc_flash_read(fl->id, addr, size, ret,
|
|
|
|
aspeed_smc_flash_mode(fl));
|
2016-07-04 14:06:38 +02:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2019-01-29 12:46:05 +01:00
|
|
|
/*
|
|
|
|
* TODO (clg@kaod.org): stolen from xilinx_spips.c. Should move to a
|
|
|
|
* common include header.
|
|
|
|
*/
|
|
|
|
typedef enum {
|
|
|
|
READ = 0x3, READ_4 = 0x13,
|
|
|
|
FAST_READ = 0xb, FAST_READ_4 = 0x0c,
|
|
|
|
DOR = 0x3b, DOR_4 = 0x3c,
|
|
|
|
QOR = 0x6b, QOR_4 = 0x6c,
|
|
|
|
DIOR = 0xbb, DIOR_4 = 0xbc,
|
|
|
|
QIOR = 0xeb, QIOR_4 = 0xec,
|
|
|
|
|
|
|
|
PP = 0x2, PP_4 = 0x12,
|
|
|
|
DPP = 0xa2,
|
|
|
|
QPP = 0x32, QPP_4 = 0x34,
|
|
|
|
} FlashCMD;
|
|
|
|
|
|
|
|
static int aspeed_smc_num_dummies(uint8_t command)
|
|
|
|
{
|
|
|
|
switch (command) { /* check for dummies */
|
|
|
|
case READ: /* no dummy bytes/cycles */
|
|
|
|
case PP:
|
|
|
|
case DPP:
|
|
|
|
case QPP:
|
|
|
|
case READ_4:
|
|
|
|
case PP_4:
|
|
|
|
case QPP_4:
|
|
|
|
return 0;
|
|
|
|
case FAST_READ:
|
|
|
|
case DOR:
|
|
|
|
case QOR:
|
2020-03-16 16:52:24 +01:00
|
|
|
case FAST_READ_4:
|
2019-01-29 12:46:05 +01:00
|
|
|
case DOR_4:
|
|
|
|
case QOR_4:
|
|
|
|
return 1;
|
|
|
|
case DIOR:
|
|
|
|
case DIOR_4:
|
|
|
|
return 2;
|
|
|
|
case QIOR:
|
|
|
|
case QIOR_4:
|
|
|
|
return 4;
|
|
|
|
default:
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, uint64_t data,
|
|
|
|
unsigned size)
|
|
|
|
{
|
|
|
|
AspeedSMCState *s = fl->controller;
|
|
|
|
uint8_t addr_width = aspeed_smc_flash_is_4byte(fl) ? 4 : 3;
|
|
|
|
|
2020-02-06 12:26:44 +01:00
|
|
|
trace_aspeed_smc_do_snoop(fl->id, s->snoop_index, s->snoop_dummies,
|
|
|
|
(uint8_t) data & 0xff);
|
|
|
|
|
2019-01-29 12:46:05 +01:00
|
|
|
if (s->snoop_index == SNOOP_OFF) {
|
|
|
|
return false; /* Do nothing */
|
|
|
|
|
|
|
|
} else if (s->snoop_index == SNOOP_START) {
|
|
|
|
uint8_t cmd = data & 0xff;
|
|
|
|
int ndummies = aspeed_smc_num_dummies(cmd);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* No dummy cycles are expected with the current command. Turn
|
|
|
|
* off snooping and let the transfer proceed normally.
|
|
|
|
*/
|
|
|
|
if (ndummies <= 0) {
|
|
|
|
s->snoop_index = SNOOP_OFF;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
s->snoop_dummies = ndummies * 8;
|
|
|
|
|
|
|
|
} else if (s->snoop_index >= addr_width + 1) {
|
|
|
|
|
|
|
|
/* The SPI transfer has reached the dummy cycles sequence */
|
|
|
|
for (; s->snoop_dummies; s->snoop_dummies--) {
|
|
|
|
ssi_transfer(s->spi, s->regs[R_DUMMY_DATA] & 0xff);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If no more dummy cycles are expected, turn off snooping */
|
|
|
|
if (!s->snoop_dummies) {
|
|
|
|
s->snoop_index = SNOOP_OFF;
|
|
|
|
} else {
|
|
|
|
s->snoop_index += size;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Dummy cycles have been faked already. Ignore the current
|
|
|
|
* SPI transfer
|
|
|
|
*/
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
s->snoop_index += size;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2016-07-04 14:06:38 +02:00
|
|
|
static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data,
|
2018-09-25 15:02:33 +02:00
|
|
|
unsigned size)
|
2016-07-04 14:06:38 +02:00
|
|
|
{
|
|
|
|
AspeedSMCFlash *fl = opaque;
|
2017-01-20 12:15:08 +01:00
|
|
|
AspeedSMCState *s = fl->controller;
|
2016-07-04 14:06:38 +02:00
|
|
|
int i;
|
|
|
|
|
2020-02-06 12:26:44 +01:00
|
|
|
trace_aspeed_smc_flash_write(fl->id, addr, size, data,
|
|
|
|
aspeed_smc_flash_mode(fl));
|
|
|
|
|
2017-01-20 12:15:07 +01:00
|
|
|
if (!aspeed_smc_is_writable(fl)) {
|
2016-07-04 14:06:38 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: flash is not writable at 0x%"
|
|
|
|
HWADDR_PRIx "\n", __func__, addr);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2017-01-20 12:15:08 +01:00
|
|
|
switch (aspeed_smc_flash_mode(fl)) {
|
|
|
|
case CTRL_USERMODE:
|
2019-01-29 12:46:05 +01:00
|
|
|
if (aspeed_smc_do_snoop(fl, data, size)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2017-01-20 12:15:08 +01:00
|
|
|
for (i = 0; i < size; i++) {
|
|
|
|
ssi_transfer(s->spi, (data >> (8 * i)) & 0xff);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case CTRL_WRITEMODE:
|
|
|
|
aspeed_smc_flash_select(fl);
|
2018-06-26 18:50:39 +02:00
|
|
|
aspeed_smc_flash_setup(fl, addr);
|
2017-01-20 12:15:08 +01:00
|
|
|
|
|
|
|
for (i = 0; i < size; i++) {
|
|
|
|
ssi_transfer(s->spi, (data >> (8 * i)) & 0xff);
|
|
|
|
}
|
2016-07-04 14:06:38 +02:00
|
|
|
|
2017-01-20 12:15:08 +01:00
|
|
|
aspeed_smc_flash_unselect(fl);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid flash mode %d\n",
|
|
|
|
__func__, aspeed_smc_flash_mode(fl));
|
2016-07-04 14:06:38 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps aspeed_smc_flash_ops = {
|
|
|
|
.read = aspeed_smc_flash_read,
|
|
|
|
.write = aspeed_smc_flash_write,
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 1,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
2016-07-04 14:06:37 +02:00
|
|
|
};
|
|
|
|
|
2020-02-06 12:26:45 +01:00
|
|
|
static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t value)
|
2016-07-04 14:06:37 +02:00
|
|
|
{
|
2019-01-29 12:46:05 +01:00
|
|
|
AspeedSMCState *s = fl->controller;
|
2020-02-06 12:26:45 +01:00
|
|
|
bool unselect;
|
|
|
|
|
|
|
|
/* User mode selects the CS, other modes unselect */
|
|
|
|
unselect = (value & CTRL_CMD_MODE_MASK) != CTRL_USERMODE;
|
|
|
|
|
|
|
|
/* A change of CTRL_CE_STOP_ACTIVE from 0 to 1, unselects the CS */
|
|
|
|
if (!(s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE) &&
|
|
|
|
value & CTRL_CE_STOP_ACTIVE) {
|
|
|
|
unselect = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
s->regs[s->r_ctrl0 + fl->id] = value;
|
2019-01-29 12:46:05 +01:00
|
|
|
|
2020-02-06 12:26:45 +01:00
|
|
|
s->snoop_index = unselect ? SNOOP_OFF : SNOOP_START;
|
2016-07-04 14:06:37 +02:00
|
|
|
|
2020-02-06 12:26:45 +01:00
|
|
|
aspeed_smc_flash_do_select(fl, unselect);
|
2016-07-04 14:06:37 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_smc_reset(DeviceState *d)
|
|
|
|
{
|
|
|
|
AspeedSMCState *s = ASPEED_SMC(d);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
memset(s->regs, 0, sizeof s->regs);
|
|
|
|
|
2020-10-12 14:49:53 +02:00
|
|
|
/* Unselect all peripherals */
|
2016-07-04 14:06:37 +02:00
|
|
|
for (i = 0; i < s->num_cs; ++i) {
|
|
|
|
s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE;
|
2017-01-20 12:15:07 +01:00
|
|
|
qemu_set_irq(s->cs_lines[i], true);
|
2016-07-04 14:06:37 +02:00
|
|
|
}
|
|
|
|
|
2019-11-19 15:12:04 +01:00
|
|
|
/* setup the default segment register values and regions for all */
|
2020-10-12 14:49:53 +02:00
|
|
|
for (i = 0; i < s->ctrl->max_peripherals; ++i) {
|
2019-11-19 15:12:04 +01:00
|
|
|
aspeed_smc_flash_set_segment_region(s, i,
|
|
|
|
s->ctrl->segment_to_reg(s, &s->ctrl->segments[i]));
|
2016-10-17 20:22:17 +02:00
|
|
|
}
|
2017-01-20 12:15:07 +01:00
|
|
|
|
2019-09-25 16:32:38 +02:00
|
|
|
/* HW strapping flash type for the AST2600 controllers */
|
|
|
|
if (s->ctrl->segments == aspeed_segments_ast2600_fmc) {
|
|
|
|
/* flash type is fixed to SPI for all */
|
|
|
|
s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0);
|
|
|
|
s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1);
|
|
|
|
s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE2);
|
|
|
|
}
|
|
|
|
|
2018-06-26 18:50:39 +02:00
|
|
|
/* HW strapping flash type for FMC controllers */
|
2017-01-20 12:15:07 +01:00
|
|
|
if (s->ctrl->segments == aspeed_segments_ast2500_fmc) {
|
|
|
|
/* flash type is fixed to SPI for CE0 and CE1 */
|
|
|
|
s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0);
|
|
|
|
s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* HW strapping for AST2400 FMC controllers (SCU70). Let's use the
|
|
|
|
* configuration of the palmetto-bmc machine */
|
|
|
|
if (s->ctrl->segments == aspeed_segments_fmc) {
|
|
|
|
s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0);
|
|
|
|
}
|
2019-01-29 12:46:05 +01:00
|
|
|
|
|
|
|
s->snoop_index = SNOOP_OFF;
|
|
|
|
s->snoop_dummies = 0;
|
2016-07-04 14:06:37 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
|
|
|
|
{
|
|
|
|
AspeedSMCState *s = ASPEED_SMC(opaque);
|
|
|
|
|
|
|
|
addr >>= 2;
|
|
|
|
|
2016-07-14 17:51:38 +02:00
|
|
|
if (addr == s->r_conf ||
|
2019-11-19 15:12:06 +01:00
|
|
|
(addr >= s->r_timings &&
|
|
|
|
addr < s->r_timings + s->ctrl->nregs_timings) ||
|
2016-07-14 17:51:38 +02:00
|
|
|
addr == s->r_ce_ctrl ||
|
2020-12-10 12:11:03 +01:00
|
|
|
addr == R_CE_CMD_CTRL ||
|
2016-07-14 17:51:38 +02:00
|
|
|
addr == R_INTR_CTRL ||
|
2019-01-29 12:46:05 +01:00
|
|
|
addr == R_DUMMY_DATA ||
|
2019-09-04 09:05:01 +02:00
|
|
|
(s->ctrl->has_dma && addr == R_DMA_CTRL) ||
|
|
|
|
(s->ctrl->has_dma && addr == R_DMA_FLASH_ADDR) ||
|
|
|
|
(s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) ||
|
|
|
|
(s->ctrl->has_dma && addr == R_DMA_LEN) ||
|
|
|
|
(s->ctrl->has_dma && addr == R_DMA_CHECKSUM) ||
|
2020-10-12 14:49:53 +02:00
|
|
|
(addr >= R_SEG_ADDR0 &&
|
|
|
|
addr < R_SEG_ADDR0 + s->ctrl->max_peripherals) ||
|
|
|
|
(addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_peripherals)) {
|
2020-02-06 12:26:44 +01:00
|
|
|
|
|
|
|
trace_aspeed_smc_read(addr, size, s->regs[addr]);
|
|
|
|
|
2016-07-14 17:51:38 +02:00
|
|
|
return s->regs[addr];
|
|
|
|
} else {
|
2016-07-04 14:06:37 +02:00
|
|
|
qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
|
2016-07-14 17:51:38 +02:00
|
|
|
__func__, addr);
|
2019-01-29 12:46:05 +01:00
|
|
|
return -1;
|
2016-07-04 14:06:37 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-09-04 09:05:02 +02:00
|
|
|
static uint8_t aspeed_smc_hclk_divisor(uint8_t hclk_mask)
|
|
|
|
{
|
|
|
|
/* HCLK/1 .. HCLK/16 */
|
|
|
|
const uint8_t hclk_divisors[] = {
|
|
|
|
15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0
|
|
|
|
};
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(hclk_divisors); i++) {
|
|
|
|
if (hclk_mask == hclk_divisors[i]) {
|
|
|
|
return i + 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "invalid HCLK mask %x", hclk_mask);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* When doing calibration, the SPI clock rate in the CE0 Control
|
|
|
|
* Register and the read delay cycles in the Read Timing Compensation
|
|
|
|
* Register are set using bit[11:4] of the DMA Control Register.
|
|
|
|
*/
|
|
|
|
static void aspeed_smc_dma_calibration(AspeedSMCState *s)
|
|
|
|
{
|
|
|
|
uint8_t delay =
|
|
|
|
(s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK;
|
|
|
|
uint8_t hclk_mask =
|
|
|
|
(s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK;
|
|
|
|
uint8_t hclk_div = aspeed_smc_hclk_divisor(hclk_mask);
|
|
|
|
uint32_t hclk_shift = (hclk_div - 1) << 2;
|
|
|
|
uint8_t cs;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The Read Timing Compensation Register values apply to all CS on
|
|
|
|
* the SPI bus and only HCLK/1 - HCLK/5 can have tunable delays
|
|
|
|
*/
|
|
|
|
if (hclk_div && hclk_div < 6) {
|
|
|
|
s->regs[s->r_timings] &= ~(0xf << hclk_shift);
|
|
|
|
s->regs[s->r_timings] |= delay << hclk_shift;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* TODO: compute the CS from the DMA address and the segment
|
|
|
|
* registers. This is not really a problem for now because the
|
|
|
|
* Timing Register values apply to all CS and software uses CS0 to
|
|
|
|
* do calibration.
|
|
|
|
*/
|
|
|
|
cs = 0;
|
|
|
|
s->regs[s->r_ctrl0 + cs] &=
|
|
|
|
~(CE_CTRL_CLOCK_FREQ_MASK << CE_CTRL_CLOCK_FREQ_SHIFT);
|
|
|
|
s->regs[s->r_ctrl0 + cs] |= CE_CTRL_CLOCK_FREQ(hclk_div);
|
|
|
|
}
|
|
|
|
|
2019-09-04 09:05:03 +02:00
|
|
|
/*
|
|
|
|
* Emulate read errors in the DMA Checksum Register for high
|
|
|
|
* frequencies and optimistic settings of the Read Timing Compensation
|
|
|
|
* Register. This will help in tuning the SPI timing calibration
|
|
|
|
* algorithm.
|
|
|
|
*/
|
|
|
|
static bool aspeed_smc_inject_read_failure(AspeedSMCState *s)
|
|
|
|
{
|
|
|
|
uint8_t delay =
|
|
|
|
(s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK;
|
|
|
|
uint8_t hclk_mask =
|
|
|
|
(s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Typical values of a palmetto-bmc machine.
|
|
|
|
*/
|
|
|
|
switch (aspeed_smc_hclk_divisor(hclk_mask)) {
|
|
|
|
case 4 ... 16:
|
|
|
|
return false;
|
|
|
|
case 3: /* at least one HCLK cycle delay */
|
|
|
|
return (delay & 0x7) < 1;
|
|
|
|
case 2: /* at least two HCLK cycle delay */
|
|
|
|
return (delay & 0x7) < 2;
|
|
|
|
case 1: /* (> 100MHz) is above the max freq of the controller */
|
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
g_assert_not_reached();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-09-04 09:05:01 +02:00
|
|
|
/*
|
|
|
|
* Accumulate the result of the reads to provide a checksum that will
|
|
|
|
* be used to validate the read timing settings.
|
|
|
|
*/
|
|
|
|
static void aspeed_smc_dma_checksum(AspeedSMCState *s)
|
|
|
|
{
|
|
|
|
MemTxResult result;
|
|
|
|
uint32_t data;
|
|
|
|
|
|
|
|
if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: invalid direction for DMA checksum\n", __func__);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2019-09-04 09:05:02 +02:00
|
|
|
if (s->regs[R_DMA_CTRL] & DMA_CTRL_CALIB) {
|
|
|
|
aspeed_smc_dma_calibration(s);
|
|
|
|
}
|
|
|
|
|
2019-09-04 09:05:01 +02:00
|
|
|
while (s->regs[R_DMA_LEN]) {
|
|
|
|
data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
|
|
|
|
MEMTXATTRS_UNSPECIFIED, &result);
|
|
|
|
if (result != MEMTX_OK) {
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash read failed @%08x\n",
|
|
|
|
__func__, s->regs[R_DMA_FLASH_ADDR]);
|
|
|
|
return;
|
|
|
|
}
|
2020-02-06 12:26:44 +01:00
|
|
|
trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data);
|
2019-09-04 09:05:01 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* When the DMA is on-going, the DMA registers are updated
|
|
|
|
* with the current working addresses and length.
|
|
|
|
*/
|
|
|
|
s->regs[R_DMA_CHECKSUM] += data;
|
|
|
|
s->regs[R_DMA_FLASH_ADDR] += 4;
|
|
|
|
s->regs[R_DMA_LEN] -= 4;
|
|
|
|
}
|
2019-09-04 09:05:03 +02:00
|
|
|
|
|
|
|
if (s->inject_failure && aspeed_smc_inject_read_failure(s)) {
|
|
|
|
s->regs[R_DMA_CHECKSUM] = 0xbadc0de;
|
|
|
|
}
|
|
|
|
|
2019-09-04 09:05:01 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_smc_dma_rw(AspeedSMCState *s)
|
|
|
|
{
|
|
|
|
MemTxResult result;
|
|
|
|
uint32_t data;
|
|
|
|
|
2020-03-23 18:22:30 +01:00
|
|
|
trace_aspeed_smc_dma_rw(s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE ?
|
|
|
|
"write" : "read",
|
|
|
|
s->regs[R_DMA_FLASH_ADDR],
|
|
|
|
s->regs[R_DMA_DRAM_ADDR],
|
|
|
|
s->regs[R_DMA_LEN]);
|
2019-09-04 09:05:01 +02:00
|
|
|
while (s->regs[R_DMA_LEN]) {
|
|
|
|
if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {
|
|
|
|
data = address_space_ldl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR],
|
|
|
|
MEMTXATTRS_UNSPECIFIED, &result);
|
|
|
|
if (result != MEMTX_OK) {
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM read failed @%08x\n",
|
|
|
|
__func__, s->regs[R_DMA_DRAM_ADDR]);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
address_space_stl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
|
|
|
|
data, MEMTXATTRS_UNSPECIFIED, &result);
|
|
|
|
if (result != MEMTX_OK) {
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash write failed @%08x\n",
|
|
|
|
__func__, s->regs[R_DMA_FLASH_ADDR]);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
|
|
|
|
MEMTXATTRS_UNSPECIFIED, &result);
|
|
|
|
if (result != MEMTX_OK) {
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash read failed @%08x\n",
|
|
|
|
__func__, s->regs[R_DMA_FLASH_ADDR]);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
address_space_stl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR],
|
|
|
|
data, MEMTXATTRS_UNSPECIFIED, &result);
|
|
|
|
if (result != MEMTX_OK) {
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM write failed @%08x\n",
|
|
|
|
__func__, s->regs[R_DMA_DRAM_ADDR]);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* When the DMA is on-going, the DMA registers are updated
|
|
|
|
* with the current working addresses and length.
|
|
|
|
*/
|
|
|
|
s->regs[R_DMA_FLASH_ADDR] += 4;
|
|
|
|
s->regs[R_DMA_DRAM_ADDR] += 4;
|
|
|
|
s->regs[R_DMA_LEN] -= 4;
|
2019-09-04 09:05:04 +02:00
|
|
|
s->regs[R_DMA_CHECKSUM] += data;
|
2019-09-04 09:05:01 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_smc_dma_stop(AspeedSMCState *s)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* When the DMA is disabled, INTR_CTRL_DMA_STATUS=0 means the
|
|
|
|
* engine is idle
|
|
|
|
*/
|
|
|
|
s->regs[R_INTR_CTRL] &= ~INTR_CTRL_DMA_STATUS;
|
|
|
|
s->regs[R_DMA_CHECKSUM] = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Lower the DMA irq in any case. The IRQ control register could
|
|
|
|
* have been cleared before disabling the DMA.
|
|
|
|
*/
|
|
|
|
qemu_irq_lower(s->irq);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* When INTR_CTRL_DMA_STATUS=1, the DMA has completed and a new DMA
|
|
|
|
* can start even if the result of the previous was not collected.
|
|
|
|
*/
|
|
|
|
static bool aspeed_smc_dma_in_progress(AspeedSMCState *s)
|
|
|
|
{
|
|
|
|
return s->regs[R_DMA_CTRL] & DMA_CTRL_ENABLE &&
|
|
|
|
!(s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_STATUS);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_smc_dma_done(AspeedSMCState *s)
|
|
|
|
{
|
|
|
|
s->regs[R_INTR_CTRL] |= INTR_CTRL_DMA_STATUS;
|
|
|
|
if (s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_EN) {
|
|
|
|
qemu_irq_raise(s->irq);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint64_t dma_ctrl)
|
|
|
|
{
|
|
|
|
if (!(dma_ctrl & DMA_CTRL_ENABLE)) {
|
|
|
|
s->regs[R_DMA_CTRL] = dma_ctrl;
|
|
|
|
|
|
|
|
aspeed_smc_dma_stop(s);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (aspeed_smc_dma_in_progress(s)) {
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA in progress\n", __func__);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
s->regs[R_DMA_CTRL] = dma_ctrl;
|
|
|
|
|
|
|
|
if (s->regs[R_DMA_CTRL] & DMA_CTRL_CKSUM) {
|
|
|
|
aspeed_smc_dma_checksum(s);
|
|
|
|
} else {
|
|
|
|
aspeed_smc_dma_rw(s);
|
|
|
|
}
|
|
|
|
|
|
|
|
aspeed_smc_dma_done(s);
|
|
|
|
}
|
|
|
|
|
2016-07-04 14:06:37 +02:00
|
|
|
static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
|
|
|
|
unsigned int size)
|
|
|
|
{
|
|
|
|
AspeedSMCState *s = ASPEED_SMC(opaque);
|
|
|
|
uint32_t value = data;
|
|
|
|
|
|
|
|
addr >>= 2;
|
|
|
|
|
2020-02-06 12:26:44 +01:00
|
|
|
trace_aspeed_smc_write(addr, size, data);
|
|
|
|
|
2016-07-14 17:51:38 +02:00
|
|
|
if (addr == s->r_conf ||
|
2019-11-19 15:12:06 +01:00
|
|
|
(addr >= s->r_timings &&
|
|
|
|
addr < s->r_timings + s->ctrl->nregs_timings) ||
|
2016-07-14 17:51:38 +02:00
|
|
|
addr == s->r_ce_ctrl) {
|
|
|
|
s->regs[addr] = value;
|
|
|
|
} else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) {
|
2017-01-20 12:15:07 +01:00
|
|
|
int cs = addr - s->r_ctrl0;
|
2020-02-06 12:26:45 +01:00
|
|
|
aspeed_smc_flash_update_ctrl(&s->flashes[cs], value);
|
2016-10-17 20:22:17 +02:00
|
|
|
} else if (addr >= R_SEG_ADDR0 &&
|
2020-10-12 14:49:53 +02:00
|
|
|
addr < R_SEG_ADDR0 + s->ctrl->max_peripherals) {
|
2016-10-17 20:22:17 +02:00
|
|
|
int cs = addr - R_SEG_ADDR0;
|
|
|
|
|
|
|
|
if (value != s->regs[R_SEG_ADDR0 + cs]) {
|
|
|
|
aspeed_smc_flash_set_segment(s, cs, value);
|
|
|
|
}
|
2020-12-10 12:11:03 +01:00
|
|
|
} else if (addr == R_CE_CMD_CTRL) {
|
|
|
|
s->regs[addr] = value & 0xff;
|
2019-01-29 12:46:05 +01:00
|
|
|
} else if (addr == R_DUMMY_DATA) {
|
|
|
|
s->regs[addr] = value & 0xff;
|
2019-09-04 09:05:01 +02:00
|
|
|
} else if (addr == R_INTR_CTRL) {
|
|
|
|
s->regs[addr] = value;
|
|
|
|
} else if (s->ctrl->has_dma && addr == R_DMA_CTRL) {
|
|
|
|
aspeed_smc_dma_ctrl(s, value);
|
|
|
|
} else if (s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) {
|
|
|
|
s->regs[addr] = DMA_DRAM_ADDR(s, value);
|
|
|
|
} else if (s->ctrl->has_dma && addr == R_DMA_FLASH_ADDR) {
|
|
|
|
s->regs[addr] = DMA_FLASH_ADDR(s, value);
|
|
|
|
} else if (s->ctrl->has_dma && addr == R_DMA_LEN) {
|
|
|
|
s->regs[addr] = DMA_LENGTH(value);
|
2016-07-14 17:51:38 +02:00
|
|
|
} else {
|
2016-07-04 14:06:37 +02:00
|
|
|
qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
|
|
|
|
__func__, addr);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps aspeed_smc_ops = {
|
|
|
|
.read = aspeed_smc_read,
|
|
|
|
.write = aspeed_smc_write,
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
|
|
};
|
|
|
|
|
2019-09-04 09:05:01 +02:00
|
|
|
/*
|
|
|
|
* Initialize the custom address spaces for DMAs
|
|
|
|
*/
|
|
|
|
static void aspeed_smc_dma_setup(AspeedSMCState *s, Error **errp)
|
|
|
|
{
|
|
|
|
char *name;
|
|
|
|
|
|
|
|
if (!s->dram_mr) {
|
|
|
|
error_setg(errp, TYPE_ASPEED_SMC ": 'dram' link not set");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
name = g_strdup_printf("%s-dma-flash", s->ctrl->name);
|
|
|
|
address_space_init(&s->flash_as, &s->mmio_flash, name);
|
|
|
|
g_free(name);
|
|
|
|
|
|
|
|
name = g_strdup_printf("%s-dma-dram", s->ctrl->name);
|
|
|
|
address_space_init(&s->dram_as, s->dram_mr, name);
|
|
|
|
g_free(name);
|
|
|
|
}
|
|
|
|
|
2016-07-04 14:06:37 +02:00
|
|
|
static void aspeed_smc_realize(DeviceState *dev, Error **errp)
|
|
|
|
{
|
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
|
|
|
AspeedSMCState *s = ASPEED_SMC(dev);
|
|
|
|
AspeedSMCClass *mc = ASPEED_SMC_GET_CLASS(s);
|
|
|
|
int i;
|
2016-07-04 14:06:38 +02:00
|
|
|
char name[32];
|
|
|
|
hwaddr offset = 0;
|
2016-07-04 14:06:37 +02:00
|
|
|
|
|
|
|
s->ctrl = mc->ctrl;
|
|
|
|
|
|
|
|
/* keep a copy under AspeedSMCState to speed up accesses */
|
|
|
|
s->r_conf = s->ctrl->r_conf;
|
|
|
|
s->r_ce_ctrl = s->ctrl->r_ce_ctrl;
|
|
|
|
s->r_ctrl0 = s->ctrl->r_ctrl0;
|
|
|
|
s->r_timings = s->ctrl->r_timings;
|
|
|
|
s->conf_enable_w0 = s->ctrl->conf_enable_w0;
|
|
|
|
|
|
|
|
/* Enforce some real HW limits */
|
2020-10-12 14:49:53 +02:00
|
|
|
if (s->num_cs > s->ctrl->max_peripherals) {
|
2016-07-04 14:06:37 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: num_cs cannot exceed: %d\n",
|
2020-10-12 14:49:53 +02:00
|
|
|
__func__, s->ctrl->max_peripherals);
|
|
|
|
s->num_cs = s->ctrl->max_peripherals;
|
2016-07-04 14:06:37 +02:00
|
|
|
}
|
|
|
|
|
2019-09-04 09:05:01 +02:00
|
|
|
/* DMA irq. Keep it first for the initialization in the SoC */
|
|
|
|
sysbus_init_irq(sbd, &s->irq);
|
|
|
|
|
2016-07-04 14:06:37 +02:00
|
|
|
s->spi = ssi_create_bus(dev, "spi");
|
|
|
|
|
2020-10-12 14:49:53 +02:00
|
|
|
/* Setup cs_lines for peripherals */
|
2016-07-04 14:06:37 +02:00
|
|
|
s->cs_lines = g_new0(qemu_irq, s->num_cs);
|
|
|
|
|
|
|
|
for (i = 0; i < s->num_cs; ++i) {
|
|
|
|
sysbus_init_irq(sbd, &s->cs_lines[i]);
|
|
|
|
}
|
|
|
|
|
2016-10-17 20:22:17 +02:00
|
|
|
/* The memory region for the controller registers */
|
2016-07-04 14:06:37 +02:00
|
|
|
memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_ops, s,
|
2017-01-20 12:15:08 +01:00
|
|
|
s->ctrl->name, s->ctrl->nregs * 4);
|
2016-07-04 14:06:37 +02:00
|
|
|
sysbus_init_mmio(sbd, &s->mmio);
|
2016-07-04 14:06:38 +02:00
|
|
|
|
|
|
|
/*
|
2016-10-17 20:22:17 +02:00
|
|
|
* The container memory region representing the address space
|
|
|
|
* window in which the flash modules are mapped. The size and
|
|
|
|
* address depends on the SoC model and controller type.
|
2016-07-04 14:06:38 +02:00
|
|
|
*/
|
|
|
|
snprintf(name, sizeof(name), "%s.flash", s->ctrl->name);
|
|
|
|
|
|
|
|
memory_region_init_io(&s->mmio_flash, OBJECT(s),
|
|
|
|
&aspeed_smc_flash_default_ops, s, name,
|
2016-10-17 20:22:16 +02:00
|
|
|
s->ctrl->flash_window_size);
|
2016-07-04 14:06:38 +02:00
|
|
|
sysbus_init_mmio(sbd, &s->mmio_flash);
|
|
|
|
|
2020-10-12 14:49:53 +02:00
|
|
|
s->flashes = g_new0(AspeedSMCFlash, s->ctrl->max_peripherals);
|
2016-07-04 14:06:38 +02:00
|
|
|
|
2016-10-17 20:22:17 +02:00
|
|
|
/*
|
2020-10-12 14:49:53 +02:00
|
|
|
* Let's create a sub memory region for each possible peripheral. All
|
2016-10-17 20:22:17 +02:00
|
|
|
* have a configurable memory segment in the overall flash mapping
|
|
|
|
* window of the controller but, there is not necessarily a flash
|
|
|
|
* module behind to handle the memory accesses. This depends on
|
|
|
|
* the board configuration.
|
|
|
|
*/
|
2020-10-12 14:49:53 +02:00
|
|
|
for (i = 0; i < s->ctrl->max_peripherals; ++i) {
|
2016-07-04 14:06:38 +02:00
|
|
|
AspeedSMCFlash *fl = &s->flashes[i];
|
|
|
|
|
|
|
|
snprintf(name, sizeof(name), "%s.%d", s->ctrl->name, i);
|
|
|
|
|
|
|
|
fl->id = i;
|
|
|
|
fl->controller = s;
|
|
|
|
fl->size = s->ctrl->segments[i].size;
|
|
|
|
memory_region_init_io(&fl->mmio, OBJECT(s), &aspeed_smc_flash_ops,
|
|
|
|
fl, name, fl->size);
|
|
|
|
memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio);
|
|
|
|
offset += fl->size;
|
|
|
|
}
|
2019-09-04 09:05:01 +02:00
|
|
|
|
|
|
|
/* DMA support */
|
|
|
|
if (s->ctrl->has_dma) {
|
|
|
|
aspeed_smc_dma_setup(s, errp);
|
|
|
|
}
|
2016-07-04 14:06:37 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static const VMStateDescription vmstate_aspeed_smc = {
|
|
|
|
.name = "aspeed.smc",
|
2019-01-29 12:46:05 +01:00
|
|
|
.version_id = 2,
|
|
|
|
.minimum_version_id = 2,
|
2016-07-04 14:06:37 +02:00
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_UINT32_ARRAY(regs, AspeedSMCState, ASPEED_SMC_R_MAX),
|
2019-01-29 12:46:05 +01:00
|
|
|
VMSTATE_UINT8(snoop_index, AspeedSMCState),
|
|
|
|
VMSTATE_UINT8(snoop_dummies, AspeedSMCState),
|
2016-07-04 14:06:37 +02:00
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static Property aspeed_smc_properties[] = {
|
|
|
|
DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1),
|
2019-09-04 09:05:03 +02:00
|
|
|
DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, false),
|
2019-09-04 09:05:01 +02:00
|
|
|
DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr,
|
|
|
|
TYPE_MEMORY_REGION, MemoryRegion *),
|
2016-07-04 14:06:37 +02:00
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
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static void aspeed_smc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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AspeedSMCClass *mc = ASPEED_SMC_CLASS(klass);
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dc->realize = aspeed_smc_realize;
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dc->reset = aspeed_smc_reset;
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2020-01-10 16:30:32 +01:00
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device_class_set_props(dc, aspeed_smc_properties);
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2016-07-04 14:06:37 +02:00
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dc->vmsd = &vmstate_aspeed_smc;
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mc->ctrl = data;
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}
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static const TypeInfo aspeed_smc_info = {
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.name = TYPE_ASPEED_SMC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AspeedSMCState),
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.class_size = sizeof(AspeedSMCClass),
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.abstract = true,
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};
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static void aspeed_smc_register_types(void)
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{
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int i;
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type_register_static(&aspeed_smc_info);
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for (i = 0; i < ARRAY_SIZE(controllers); ++i) {
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TypeInfo ti = {
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.name = controllers[i].name,
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.parent = TYPE_ASPEED_SMC,
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.class_init = aspeed_smc_class_init,
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.class_data = (void *)&controllers[i],
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};
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type_register(&ti);
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}
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}
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type_init(aspeed_smc_register_types)
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