2020-09-11 07:20:52 +02:00
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/*
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* Machine definitions for boards featuring an NPCM7xx SoC.
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "exec/address-spaces.h"
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#include "hw/arm/npcm7xx.h"
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#include "hw/core/cpu.h"
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2020-09-11 07:20:54 +02:00
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#include "hw/loader.h"
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2020-09-11 07:20:58 +02:00
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#include "hw/qdev-properties.h"
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2020-09-11 07:20:52 +02:00
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#include "qapi/error.h"
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2020-09-11 07:20:54 +02:00
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#include "qemu-common.h"
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2020-09-11 07:20:52 +02:00
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#include "qemu/units.h"
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2020-09-11 07:20:54 +02:00
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#include "sysemu/sysemu.h"
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2020-09-11 07:20:52 +02:00
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#define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7
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#define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff
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2020-09-11 07:20:54 +02:00
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static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin";
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static void npcm7xx_load_bootrom(MachineState *machine, NPCM7xxState *soc)
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{
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2020-10-26 15:30:16 +01:00
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const char *bios_name = machine->firmware ?: npcm7xx_default_bootrom;
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2020-09-11 07:20:54 +02:00
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g_autofree char *filename = NULL;
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int ret;
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
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if (!filename) {
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error_report("Could not find ROM image '%s'", bios_name);
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if (!machine->kernel_filename) {
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/* We can't boot without a bootrom or a kernel image. */
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exit(1);
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}
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return;
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}
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ret = load_image_mr(filename, &soc->irom);
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if (ret < 0) {
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error_report("Failed to load ROM image '%s'", filename);
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exit(1);
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}
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}
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2020-09-11 07:20:58 +02:00
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static void npcm7xx_connect_flash(NPCM7xxFIUState *fiu, int cs_no,
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const char *flash_type, DriveInfo *dinfo)
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{
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DeviceState *flash;
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qemu_irq flash_cs;
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flash = qdev_new(flash_type);
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if (dinfo) {
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qdev_prop_set_drive(flash, "drive", blk_by_legacy_dinfo(dinfo));
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}
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qdev_realize_and_unref(flash, BUS(fiu->spi), &error_fatal);
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flash_cs = qdev_get_gpio_in_named(flash, SSI_GPIO_CS, 0);
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qdev_connect_gpio_out_named(DEVICE(fiu), "cs", cs_no, flash_cs);
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}
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2020-09-11 07:20:52 +02:00
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static void npcm7xx_connect_dram(NPCM7xxState *soc, MemoryRegion *dram)
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{
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memory_region_add_subregion(get_system_memory(), NPCM7XX_DRAM_BA, dram);
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object_property_set_link(OBJECT(soc), "dram-mr", OBJECT(dram),
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&error_abort);
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}
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static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
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uint32_t hw_straps)
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{
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NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
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MachineClass *mc = &nmc->parent;
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Object *obj;
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if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
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error_report("This board can only be used with %s",
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mc->default_cpu_type);
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exit(1);
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}
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obj = object_new_with_props(nmc->soc_type, OBJECT(machine), "soc",
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&error_abort, NULL);
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object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abort);
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return NPCM7XX(obj);
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}
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static void npcm750_evb_init(MachineState *machine)
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{
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NPCM7xxState *soc;
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soc = npcm7xx_create_soc(machine, NPCM750_EVB_POWER_ON_STRAPS);
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npcm7xx_connect_dram(soc, machine->ram);
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qdev_realize(DEVICE(soc), NULL, &error_fatal);
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2020-09-11 07:20:54 +02:00
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npcm7xx_load_bootrom(machine, soc);
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2020-09-11 07:20:58 +02:00
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npcm7xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0));
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2020-09-11 07:20:52 +02:00
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npcm7xx_load_kernel(machine, soc);
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}
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static void quanta_gsj_init(MachineState *machine)
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{
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NPCM7xxState *soc;
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soc = npcm7xx_create_soc(machine, QUANTA_GSJ_POWER_ON_STRAPS);
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npcm7xx_connect_dram(soc, machine->ram);
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qdev_realize(DEVICE(soc), NULL, &error_fatal);
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2020-09-11 07:20:54 +02:00
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npcm7xx_load_bootrom(machine, soc);
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2020-09-11 07:20:58 +02:00
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npcm7xx_connect_flash(&soc->fiu[0], 0, "mx25l25635e",
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drive_get(IF_MTD, 0, 0));
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2020-09-11 07:20:52 +02:00
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npcm7xx_load_kernel(machine, soc);
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}
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static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *type)
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{
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NPCM7xxClass *sc = NPCM7XX_CLASS(object_class_by_name(type));
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MachineClass *mc = MACHINE_CLASS(nmc);
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nmc->soc_type = type;
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mc->default_cpus = mc->min_cpus = mc->max_cpus = sc->num_cpus;
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}
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static void npcm7xx_machine_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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mc->no_floppy = 1;
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mc->no_cdrom = 1;
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mc->no_parallel = 1;
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mc->default_ram_id = "ram";
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mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
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}
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/*
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* Schematics:
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* https://github.com/Nuvoton-Israel/nuvoton-info/blob/master/npcm7xx-poleg/evaluation-board/board_deliverables/NPCM750x_EB_ver.A1.1_COMPLETE.pdf
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*/
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static void npcm750_evb_machine_class_init(ObjectClass *oc, void *data)
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{
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NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
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MachineClass *mc = MACHINE_CLASS(oc);
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npcm7xx_set_soc_type(nmc, TYPE_NPCM750);
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mc->desc = "Nuvoton NPCM750 Evaluation Board (Cortex A9)";
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mc->init = npcm750_evb_init;
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mc->default_ram_size = 512 * MiB;
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};
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static void gsj_machine_class_init(ObjectClass *oc, void *data)
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{
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NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
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MachineClass *mc = MACHINE_CLASS(oc);
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npcm7xx_set_soc_type(nmc, TYPE_NPCM730);
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mc->desc = "Quanta GSJ (Cortex A9)";
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mc->init = quanta_gsj_init;
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mc->default_ram_size = 512 * MiB;
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};
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static const TypeInfo npcm7xx_machine_types[] = {
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{
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.name = TYPE_NPCM7XX_MACHINE,
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.parent = TYPE_MACHINE,
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.instance_size = sizeof(NPCM7xxMachine),
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.class_size = sizeof(NPCM7xxMachineClass),
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.class_init = npcm7xx_machine_class_init,
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.abstract = true,
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}, {
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.name = MACHINE_TYPE_NAME("npcm750-evb"),
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.parent = TYPE_NPCM7XX_MACHINE,
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.class_init = npcm750_evb_machine_class_init,
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}, {
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.name = MACHINE_TYPE_NAME("quanta-gsj"),
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.parent = TYPE_NPCM7XX_MACHINE,
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.class_init = gsj_machine_class_init,
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},
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};
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DEFINE_TYPES(npcm7xx_machine_types)
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