2005-07-02 16:58:51 +02:00
|
|
|
#if !defined(__QEMU_MIPS_EXEC_H__)
|
|
|
|
#define __QEMU_MIPS_EXEC_H__
|
|
|
|
|
2005-12-17 02:11:12 +01:00
|
|
|
//#define DEBUG_OP
|
2005-07-02 16:58:51 +02:00
|
|
|
|
2006-12-21 02:19:56 +01:00
|
|
|
#include "config.h"
|
2005-07-02 16:58:51 +02:00
|
|
|
#include "mips-defs.h"
|
|
|
|
#include "dyngen-exec.h"
|
2007-04-29 23:26:37 +02:00
|
|
|
#include "cpu-defs.h"
|
2005-07-02 16:58:51 +02:00
|
|
|
|
|
|
|
register struct CPUMIPSState *env asm(AREG0);
|
|
|
|
|
|
|
|
#include "cpu.h"
|
|
|
|
#include "exec-all.h"
|
|
|
|
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2005-10-30 19:16:26 +01:00
|
|
|
#include "softmmu_exec.h"
|
2005-07-02 16:58:51 +02:00
|
|
|
#endif /* !defined(CONFIG_USER_ONLY) */
|
|
|
|
|
2006-12-06 19:19:33 +01:00
|
|
|
void do_mtc0_status_debug(uint32_t old, uint32_t val);
|
|
|
|
void do_mtc0_status_irqraise_debug(void);
|
2006-06-14 14:56:19 +02:00
|
|
|
void dump_fpu(CPUState *env);
|
2007-09-16 23:08:06 +02:00
|
|
|
void fpu_dump_state(CPUState *env, FILE *f,
|
2006-06-14 14:56:19 +02:00
|
|
|
int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
|
|
|
|
int flags);
|
2005-07-02 16:58:51 +02:00
|
|
|
|
|
|
|
int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
|
2007-10-14 09:07:08 +02:00
|
|
|
int mmu_idx, int is_softmmu);
|
2005-07-02 16:58:51 +02:00
|
|
|
void do_interrupt (CPUState *env);
|
2007-05-13 15:49:44 +02:00
|
|
|
void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);
|
2005-07-02 16:58:51 +02:00
|
|
|
|
|
|
|
void cpu_loop_exit(void);
|
|
|
|
void do_raise_exception_err (uint32_t exception, int error_code);
|
|
|
|
void do_raise_exception (uint32_t exception);
|
|
|
|
|
|
|
|
uint32_t cpu_mips_get_random (CPUState *env);
|
|
|
|
uint32_t cpu_mips_get_count (CPUState *env);
|
|
|
|
void cpu_mips_store_count (CPUState *env, uint32_t value);
|
|
|
|
void cpu_mips_store_compare (CPUState *env, uint32_t value);
|
2007-09-25 18:53:15 +02:00
|
|
|
void cpu_mips_start_count(CPUState *env);
|
|
|
|
void cpu_mips_stop_count(CPUState *env);
|
2007-03-31 18:54:14 +02:00
|
|
|
void cpu_mips_update_irq (CPUState *env);
|
2005-07-02 16:58:51 +02:00
|
|
|
void cpu_mips_clock_init (CPUState *env);
|
2006-12-06 18:42:40 +01:00
|
|
|
void cpu_mips_tlb_flush (CPUState *env, int flush_global);
|
2005-07-02 16:58:51 +02:00
|
|
|
|
2008-07-23 18:16:31 +02:00
|
|
|
static inline void env_to_regs(void)
|
2007-06-03 19:44:37 +02:00
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2008-07-23 18:16:31 +02:00
|
|
|
static inline void regs_to_env(void)
|
2007-06-03 19:44:37 +02:00
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2008-07-23 18:16:31 +02:00
|
|
|
static inline int cpu_halted(CPUState *env)
|
2007-09-27 01:52:06 +02:00
|
|
|
{
|
2007-06-03 19:44:37 +02:00
|
|
|
if (!env->halted)
|
|
|
|
return 0;
|
|
|
|
if (env->interrupt_request &
|
|
|
|
(CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
|
|
|
|
env->halted = 0;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
return EXCP_HALTED;
|
|
|
|
}
|
|
|
|
|
2008-07-23 18:16:31 +02:00
|
|
|
static inline void compute_hflags(CPUState *env)
|
2007-09-27 01:52:06 +02:00
|
|
|
{
|
2007-12-30 16:36:58 +01:00
|
|
|
env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
|
2008-11-11 12:39:33 +01:00
|
|
|
MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
|
|
|
|
MIPS_HFLAG_UX);
|
2007-09-27 01:52:06 +02:00
|
|
|
if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
|
|
|
|
!(env->CP0_Status & (1 << CP0St_ERL)) &&
|
2007-09-29 21:21:36 +02:00
|
|
|
!(env->hflags & MIPS_HFLAG_DM)) {
|
2007-10-28 20:45:05 +01:00
|
|
|
env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
|
2007-09-29 21:21:36 +02:00
|
|
|
}
|
2007-11-08 19:05:37 +01:00
|
|
|
#if defined(TARGET_MIPS64)
|
2007-10-28 20:45:05 +01:00
|
|
|
if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
|
2007-09-27 01:52:06 +02:00
|
|
|
(env->CP0_Status & (1 << CP0St_PX)) ||
|
|
|
|
(env->CP0_Status & (1 << CP0St_UX)))
|
|
|
|
env->hflags |= MIPS_HFLAG_64;
|
2008-11-11 12:39:33 +01:00
|
|
|
if (env->CP0_Status & (1 << CP0St_UX))
|
|
|
|
env->hflags |= MIPS_HFLAG_UX;
|
2007-09-27 01:52:06 +02:00
|
|
|
#endif
|
2007-09-29 21:21:36 +02:00
|
|
|
if ((env->CP0_Status & (1 << CP0St_CU0)) ||
|
2007-10-28 20:45:05 +01:00
|
|
|
!(env->hflags & MIPS_HFLAG_KSU))
|
2007-09-27 01:52:06 +02:00
|
|
|
env->hflags |= MIPS_HFLAG_CP0;
|
|
|
|
if (env->CP0_Status & (1 << CP0St_CU1))
|
|
|
|
env->hflags |= MIPS_HFLAG_FPU;
|
|
|
|
if (env->CP0_Status & (1 << CP0St_FR))
|
|
|
|
env->hflags |= MIPS_HFLAG_F64;
|
2007-12-30 16:36:58 +01:00
|
|
|
if (env->insn_flags & ISA_MIPS32R2) {
|
2008-09-18 13:57:27 +02:00
|
|
|
if (env->active_fpu.fcr0 & (1 << FCR0_F64))
|
2007-12-30 16:36:58 +01:00
|
|
|
env->hflags |= MIPS_HFLAG_COP1X;
|
|
|
|
} else if (env->insn_flags & ISA_MIPS32) {
|
|
|
|
if (env->hflags & MIPS_HFLAG_64)
|
|
|
|
env->hflags |= MIPS_HFLAG_COP1X;
|
|
|
|
} else if (env->insn_flags & ISA_MIPS4) {
|
|
|
|
/* All supported MIPS IV CPUs use the XX (CU3) to enable
|
|
|
|
and disable the MIPS IV extensions to the MIPS III ISA.
|
|
|
|
Some other MIPS IV CPUs ignore the bit, so the check here
|
|
|
|
would be too restrictive for them. */
|
|
|
|
if (env->CP0_Status & (1 << CP0St_CU3))
|
|
|
|
env->hflags |= MIPS_HFLAG_COP1X;
|
|
|
|
}
|
2007-09-27 01:52:06 +02:00
|
|
|
}
|
|
|
|
|
2005-07-02 16:58:51 +02:00
|
|
|
#endif /* !defined(__QEMU_MIPS_EXEC_H__) */
|