2015-09-07 11:39:30 +02:00
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/*
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* i.MX Fast Ethernet Controller emulation.
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*
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* Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
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*
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* Based on Coldfire Fast Ethernet Controller emulation.
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*
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* Copyright (c) 2007 CodeSourcery.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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2016-01-26 19:17:05 +01:00
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#include "qemu/osdep.h"
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2015-09-07 11:39:30 +02:00
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#include "hw/net/imx_fec.h"
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#include "sysemu/dma.h"
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/* For crc32 */
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#include <zlib.h>
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2015-10-25 15:16:21 +01:00
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#ifndef DEBUG_IMX_FEC
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#define DEBUG_IMX_FEC 0
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2015-09-07 11:39:30 +02:00
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#endif
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2015-10-25 15:16:21 +01:00
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#define FEC_PRINTF(fmt, args...) \
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do { \
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if (DEBUG_IMX_FEC) { \
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fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_FEC, \
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__func__, ##args); \
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} \
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2015-09-07 11:39:30 +02:00
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} while (0)
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2015-10-25 15:16:21 +01:00
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#ifndef DEBUG_IMX_PHY
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#define DEBUG_IMX_PHY 0
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2015-09-07 11:39:30 +02:00
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#endif
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2015-10-25 15:16:21 +01:00
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#define PHY_PRINTF(fmt, args...) \
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do { \
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if (DEBUG_IMX_PHY) { \
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fprintf(stderr, "[%s.phy]%s: " fmt , TYPE_IMX_FEC, \
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__func__, ##args); \
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} \
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2015-09-07 11:39:30 +02:00
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} while (0)
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static const VMStateDescription vmstate_imx_fec = {
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.name = TYPE_IMX_FEC,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(irq_state, IMXFECState),
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VMSTATE_UINT32(eir, IMXFECState),
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VMSTATE_UINT32(eimr, IMXFECState),
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VMSTATE_UINT32(rx_enabled, IMXFECState),
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VMSTATE_UINT32(rx_descriptor, IMXFECState),
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VMSTATE_UINT32(tx_descriptor, IMXFECState),
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VMSTATE_UINT32(ecr, IMXFECState),
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VMSTATE_UINT32(mmfr, IMXFECState),
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VMSTATE_UINT32(mscr, IMXFECState),
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VMSTATE_UINT32(mibc, IMXFECState),
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VMSTATE_UINT32(rcr, IMXFECState),
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VMSTATE_UINT32(tcr, IMXFECState),
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VMSTATE_UINT32(tfwr, IMXFECState),
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VMSTATE_UINT32(frsr, IMXFECState),
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VMSTATE_UINT32(erdsr, IMXFECState),
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VMSTATE_UINT32(etdsr, IMXFECState),
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VMSTATE_UINT32(emrbr, IMXFECState),
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VMSTATE_UINT32(miigsk_cfgr, IMXFECState),
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VMSTATE_UINT32(miigsk_enr, IMXFECState),
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VMSTATE_UINT32(phy_status, IMXFECState),
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VMSTATE_UINT32(phy_control, IMXFECState),
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VMSTATE_UINT32(phy_advertise, IMXFECState),
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VMSTATE_UINT32(phy_int, IMXFECState),
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VMSTATE_UINT32(phy_int_mask, IMXFECState),
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VMSTATE_END_OF_LIST()
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}
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};
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#define PHY_INT_ENERGYON (1 << 7)
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#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
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#define PHY_INT_FAULT (1 << 5)
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#define PHY_INT_DOWN (1 << 4)
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#define PHY_INT_AUTONEG_LP (1 << 3)
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#define PHY_INT_PARFAULT (1 << 2)
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#define PHY_INT_AUTONEG_PAGE (1 << 1)
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static void imx_fec_update(IMXFECState *s);
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/*
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* The MII phy could raise a GPIO to the processor which in turn
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* could be handled as an interrpt by the OS.
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* For now we don't handle any GPIO/interrupt line, so the OS will
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* have to poll for the PHY status.
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*/
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static void phy_update_irq(IMXFECState *s)
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{
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imx_fec_update(s);
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}
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static void phy_update_link(IMXFECState *s)
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{
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/* Autonegotiation status mirrors link status. */
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if (qemu_get_queue(s->nic)->link_down) {
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PHY_PRINTF("link is down\n");
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s->phy_status &= ~0x0024;
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s->phy_int |= PHY_INT_DOWN;
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} else {
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PHY_PRINTF("link is up\n");
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s->phy_status |= 0x0024;
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s->phy_int |= PHY_INT_ENERGYON;
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s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
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}
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phy_update_irq(s);
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}
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static void imx_fec_set_link(NetClientState *nc)
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{
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phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc)));
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}
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static void phy_reset(IMXFECState *s)
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{
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s->phy_status = 0x7809;
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s->phy_control = 0x3000;
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s->phy_advertise = 0x01e1;
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s->phy_int_mask = 0;
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s->phy_int = 0;
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phy_update_link(s);
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}
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static uint32_t do_phy_read(IMXFECState *s, int reg)
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{
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uint32_t val;
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if (reg > 31) {
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/* we only advertise one phy */
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return 0;
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}
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switch (reg) {
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case 0: /* Basic Control */
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val = s->phy_control;
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break;
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case 1: /* Basic Status */
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val = s->phy_status;
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break;
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case 2: /* ID1 */
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val = 0x0007;
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break;
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case 3: /* ID2 */
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val = 0xc0d1;
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break;
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case 4: /* Auto-neg advertisement */
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val = s->phy_advertise;
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break;
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case 5: /* Auto-neg Link Partner Ability */
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val = 0x0f71;
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break;
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case 6: /* Auto-neg Expansion */
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val = 1;
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break;
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case 29: /* Interrupt source. */
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val = s->phy_int;
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s->phy_int = 0;
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phy_update_irq(s);
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break;
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case 30: /* Interrupt mask */
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val = s->phy_int_mask;
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break;
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case 17:
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case 18:
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case 27:
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case 31:
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2015-10-25 15:16:21 +01:00
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qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n",
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2015-09-07 11:39:30 +02:00
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TYPE_IMX_FEC, __func__, reg);
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val = 0;
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break;
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default:
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2015-10-25 15:16:21 +01:00
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qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
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2015-09-07 11:39:30 +02:00
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TYPE_IMX_FEC, __func__, reg);
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val = 0;
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break;
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}
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PHY_PRINTF("read 0x%04x @ %d\n", val, reg);
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return val;
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}
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static void do_phy_write(IMXFECState *s, int reg, uint32_t val)
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{
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PHY_PRINTF("write 0x%04x @ %d\n", val, reg);
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if (reg > 31) {
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/* we only advertise one phy */
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return;
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}
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switch (reg) {
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case 0: /* Basic Control */
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if (val & 0x8000) {
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phy_reset(s);
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} else {
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s->phy_control = val & 0x7980;
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/* Complete autonegotiation immediately. */
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if (val & 0x1000) {
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s->phy_status |= 0x0020;
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}
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}
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break;
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case 4: /* Auto-neg advertisement */
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s->phy_advertise = (val & 0x2d7f) | 0x80;
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break;
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case 30: /* Interrupt mask */
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s->phy_int_mask = val & 0xff;
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phy_update_irq(s);
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break;
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case 17:
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case 18:
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case 27:
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case 31:
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2015-10-25 15:16:21 +01:00
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qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n",
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2015-09-07 11:39:30 +02:00
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TYPE_IMX_FEC, __func__, reg);
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break;
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default:
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2015-10-25 15:16:21 +01:00
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qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
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2015-09-07 11:39:30 +02:00
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TYPE_IMX_FEC, __func__, reg);
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break;
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}
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}
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static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr)
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{
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dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd));
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}
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static void imx_fec_write_bd(IMXFECBufDesc *bd, dma_addr_t addr)
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{
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dma_memory_write(&address_space_memory, addr, bd, sizeof(*bd));
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}
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static void imx_fec_update(IMXFECState *s)
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{
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uint32_t active;
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uint32_t changed;
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active = s->eir & s->eimr;
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changed = active ^ s->irq_state;
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if (changed) {
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qemu_set_irq(s->irq, active);
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}
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s->irq_state = active;
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}
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static void imx_fec_do_tx(IMXFECState *s)
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{
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int frame_size = 0;
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uint8_t frame[FEC_MAX_FRAME_SIZE];
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uint8_t *ptr = frame;
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uint32_t addr = s->tx_descriptor;
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while (1) {
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IMXFECBufDesc bd;
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int len;
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imx_fec_read_bd(&bd, addr);
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FEC_PRINTF("tx_bd %x flags %04x len %d data %08x\n",
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addr, bd.flags, bd.length, bd.data);
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if ((bd.flags & FEC_BD_R) == 0) {
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/* Run out of descriptors to transmit. */
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break;
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}
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len = bd.length;
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if (frame_size + len > FEC_MAX_FRAME_SIZE) {
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len = FEC_MAX_FRAME_SIZE - frame_size;
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s->eir |= FEC_INT_BABT;
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}
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dma_memory_read(&address_space_memory, bd.data, ptr, len);
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ptr += len;
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frame_size += len;
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if (bd.flags & FEC_BD_L) {
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/* Last buffer in frame. */
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qemu_send_packet(qemu_get_queue(s->nic), frame, len);
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ptr = frame;
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frame_size = 0;
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s->eir |= FEC_INT_TXF;
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}
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s->eir |= FEC_INT_TXB;
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bd.flags &= ~FEC_BD_R;
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/* Write back the modified descriptor. */
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imx_fec_write_bd(&bd, addr);
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/* Advance to the next descriptor. */
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if ((bd.flags & FEC_BD_W) != 0) {
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addr = s->etdsr;
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} else {
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addr += 8;
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}
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}
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s->tx_descriptor = addr;
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imx_fec_update(s);
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}
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static void imx_fec_enable_rx(IMXFECState *s)
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{
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IMXFECBufDesc bd;
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uint32_t tmp;
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imx_fec_read_bd(&bd, s->rx_descriptor);
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tmp = ((bd.flags & FEC_BD_E) != 0);
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if (!tmp) {
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FEC_PRINTF("RX buffer full\n");
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} else if (!s->rx_enabled) {
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qemu_flush_queued_packets(qemu_get_queue(s->nic));
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}
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s->rx_enabled = tmp;
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}
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static void imx_fec_reset(DeviceState *d)
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{
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IMXFECState *s = IMX_FEC(d);
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/* Reset the FEC */
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s->eir = 0;
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s->eimr = 0;
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s->rx_enabled = 0;
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s->ecr = 0;
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s->mscr = 0;
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s->mibc = 0xc0000000;
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s->rcr = 0x05ee0001;
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s->tcr = 0;
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s->tfwr = 0;
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s->frsr = 0x500;
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s->miigsk_cfgr = 0;
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s->miigsk_enr = 0x6;
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/* We also reset the PHY */
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phy_reset(s);
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}
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static uint64_t imx_fec_read(void *opaque, hwaddr addr, unsigned size)
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{
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|
|
IMXFECState *s = IMX_FEC(opaque);
|
|
|
|
|
2015-10-25 15:16:21 +01:00
|
|
|
FEC_PRINTF("reading from @ 0x%" HWADDR_PRIx "\n", addr);
|
2015-09-07 11:39:30 +02:00
|
|
|
|
|
|
|
switch (addr & 0x3ff) {
|
|
|
|
case 0x004:
|
|
|
|
return s->eir;
|
|
|
|
case 0x008:
|
|
|
|
return s->eimr;
|
|
|
|
case 0x010:
|
|
|
|
return s->rx_enabled ? (1 << 24) : 0; /* RDAR */
|
|
|
|
case 0x014:
|
|
|
|
return 0; /* TDAR */
|
|
|
|
case 0x024:
|
|
|
|
return s->ecr;
|
|
|
|
case 0x040:
|
|
|
|
return s->mmfr;
|
|
|
|
case 0x044:
|
|
|
|
return s->mscr;
|
|
|
|
case 0x064:
|
|
|
|
return s->mibc; /* MIBC */
|
|
|
|
case 0x084:
|
|
|
|
return s->rcr;
|
|
|
|
case 0x0c4:
|
|
|
|
return s->tcr;
|
|
|
|
case 0x0e4: /* PALR */
|
|
|
|
return (s->conf.macaddr.a[0] << 24)
|
|
|
|
| (s->conf.macaddr.a[1] << 16)
|
|
|
|
| (s->conf.macaddr.a[2] << 8)
|
|
|
|
| s->conf.macaddr.a[3];
|
|
|
|
break;
|
|
|
|
case 0x0e8: /* PAUR */
|
|
|
|
return (s->conf.macaddr.a[4] << 24)
|
|
|
|
| (s->conf.macaddr.a[5] << 16)
|
|
|
|
| 0x8808;
|
|
|
|
case 0x0ec:
|
|
|
|
return 0x10000; /* OPD */
|
|
|
|
case 0x118:
|
|
|
|
return 0;
|
|
|
|
case 0x11c:
|
|
|
|
return 0;
|
|
|
|
case 0x120:
|
|
|
|
return 0;
|
|
|
|
case 0x124:
|
|
|
|
return 0;
|
|
|
|
case 0x144:
|
|
|
|
return s->tfwr;
|
|
|
|
case 0x14c:
|
|
|
|
return 0x600;
|
|
|
|
case 0x150:
|
|
|
|
return s->frsr;
|
|
|
|
case 0x180:
|
|
|
|
return s->erdsr;
|
|
|
|
case 0x184:
|
|
|
|
return s->etdsr;
|
|
|
|
case 0x188:
|
|
|
|
return s->emrbr;
|
|
|
|
case 0x300:
|
|
|
|
return s->miigsk_cfgr;
|
|
|
|
case 0x308:
|
|
|
|
return s->miigsk_enr;
|
|
|
|
default:
|
2015-10-25 15:16:21 +01:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
|
|
|
|
HWADDR_PRIx "\n", TYPE_IMX_FEC, __func__, addr);
|
2015-09-07 11:39:30 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void imx_fec_write(void *opaque, hwaddr addr,
|
|
|
|
uint64_t value, unsigned size)
|
|
|
|
{
|
|
|
|
IMXFECState *s = IMX_FEC(opaque);
|
|
|
|
|
2015-10-25 15:16:21 +01:00
|
|
|
FEC_PRINTF("writing 0x%08x @ 0x%" HWADDR_PRIx "\n", (int)value, addr);
|
2015-09-07 11:39:30 +02:00
|
|
|
|
|
|
|
switch (addr & 0x3ff) {
|
|
|
|
case 0x004: /* EIR */
|
|
|
|
s->eir &= ~value;
|
|
|
|
break;
|
|
|
|
case 0x008: /* EIMR */
|
|
|
|
s->eimr = value;
|
|
|
|
break;
|
|
|
|
case 0x010: /* RDAR */
|
|
|
|
if ((s->ecr & FEC_EN) && !s->rx_enabled) {
|
|
|
|
imx_fec_enable_rx(s);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 0x014: /* TDAR */
|
|
|
|
if (s->ecr & FEC_EN) {
|
|
|
|
imx_fec_do_tx(s);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 0x024: /* ECR */
|
|
|
|
s->ecr = value;
|
|
|
|
if (value & FEC_RESET) {
|
|
|
|
imx_fec_reset(DEVICE(s));
|
|
|
|
}
|
|
|
|
if ((s->ecr & FEC_EN) == 0) {
|
|
|
|
s->rx_enabled = 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 0x040: /* MMFR */
|
|
|
|
/* store the value */
|
|
|
|
s->mmfr = value;
|
|
|
|
if (extract32(value, 28, 1)) {
|
|
|
|
do_phy_write(s, extract32(value, 18, 9), extract32(value, 0, 16));
|
|
|
|
} else {
|
|
|
|
s->mmfr = do_phy_read(s, extract32(value, 18, 9));
|
|
|
|
}
|
|
|
|
/* raise the interrupt as the PHY operation is done */
|
|
|
|
s->eir |= FEC_INT_MII;
|
|
|
|
break;
|
|
|
|
case 0x044: /* MSCR */
|
|
|
|
s->mscr = value & 0xfe;
|
|
|
|
break;
|
|
|
|
case 0x064: /* MIBC */
|
|
|
|
/* TODO: Implement MIB. */
|
|
|
|
s->mibc = (value & 0x80000000) ? 0xc0000000 : 0;
|
|
|
|
break;
|
|
|
|
case 0x084: /* RCR */
|
|
|
|
s->rcr = value & 0x07ff003f;
|
|
|
|
/* TODO: Implement LOOP mode. */
|
|
|
|
break;
|
|
|
|
case 0x0c4: /* TCR */
|
|
|
|
/* We transmit immediately, so raise GRA immediately. */
|
|
|
|
s->tcr = value;
|
|
|
|
if (value & 1) {
|
|
|
|
s->eir |= FEC_INT_GRA;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 0x0e4: /* PALR */
|
|
|
|
s->conf.macaddr.a[0] = value >> 24;
|
|
|
|
s->conf.macaddr.a[1] = value >> 16;
|
|
|
|
s->conf.macaddr.a[2] = value >> 8;
|
|
|
|
s->conf.macaddr.a[3] = value;
|
|
|
|
break;
|
|
|
|
case 0x0e8: /* PAUR */
|
|
|
|
s->conf.macaddr.a[4] = value >> 24;
|
|
|
|
s->conf.macaddr.a[5] = value >> 16;
|
|
|
|
break;
|
|
|
|
case 0x0ec: /* OPDR */
|
|
|
|
break;
|
|
|
|
case 0x118: /* IAUR */
|
|
|
|
case 0x11c: /* IALR */
|
|
|
|
case 0x120: /* GAUR */
|
|
|
|
case 0x124: /* GALR */
|
|
|
|
/* TODO: implement MAC hash filtering. */
|
|
|
|
break;
|
|
|
|
case 0x144: /* TFWR */
|
|
|
|
s->tfwr = value & 3;
|
|
|
|
break;
|
|
|
|
case 0x14c: /* FRBR */
|
|
|
|
/* FRBR writes ignored. */
|
|
|
|
break;
|
|
|
|
case 0x150: /* FRSR */
|
|
|
|
s->frsr = (value & 0x3fc) | 0x400;
|
|
|
|
break;
|
|
|
|
case 0x180: /* ERDSR */
|
|
|
|
s->erdsr = value & ~3;
|
|
|
|
s->rx_descriptor = s->erdsr;
|
|
|
|
break;
|
|
|
|
case 0x184: /* ETDSR */
|
|
|
|
s->etdsr = value & ~3;
|
|
|
|
s->tx_descriptor = s->etdsr;
|
|
|
|
break;
|
|
|
|
case 0x188: /* EMRBR */
|
|
|
|
s->emrbr = value & 0x7f0;
|
|
|
|
break;
|
|
|
|
case 0x300: /* MIIGSK_CFGR */
|
|
|
|
s->miigsk_cfgr = value & 0x53;
|
|
|
|
break;
|
|
|
|
case 0x308: /* MIIGSK_ENR */
|
|
|
|
s->miigsk_enr = (value & 0x2) ? 0x6 : 0;
|
|
|
|
break;
|
|
|
|
default:
|
2015-10-25 15:16:21 +01:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
|
|
|
|
HWADDR_PRIx "\n", TYPE_IMX_FEC, __func__, addr);
|
2015-09-07 11:39:30 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
imx_fec_update(s);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int imx_fec_can_receive(NetClientState *nc)
|
|
|
|
{
|
|
|
|
IMXFECState *s = IMX_FEC(qemu_get_nic_opaque(nc));
|
|
|
|
|
|
|
|
return s->rx_enabled;
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf,
|
|
|
|
size_t len)
|
|
|
|
{
|
|
|
|
IMXFECState *s = IMX_FEC(qemu_get_nic_opaque(nc));
|
|
|
|
IMXFECBufDesc bd;
|
|
|
|
uint32_t flags = 0;
|
|
|
|
uint32_t addr;
|
|
|
|
uint32_t crc;
|
|
|
|
uint32_t buf_addr;
|
|
|
|
uint8_t *crc_ptr;
|
|
|
|
unsigned int buf_len;
|
|
|
|
size_t size = len;
|
|
|
|
|
|
|
|
FEC_PRINTF("len %d\n", (int)size);
|
|
|
|
|
|
|
|
if (!s->rx_enabled) {
|
2015-10-25 15:16:21 +01:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Unexpected packet\n",
|
2015-09-07 11:39:30 +02:00
|
|
|
TYPE_IMX_FEC, __func__);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* 4 bytes for the CRC. */
|
|
|
|
size += 4;
|
|
|
|
crc = cpu_to_be32(crc32(~0, buf, size));
|
|
|
|
crc_ptr = (uint8_t *) &crc;
|
|
|
|
|
|
|
|
/* Huge frames are truncted. */
|
|
|
|
if (size > FEC_MAX_FRAME_SIZE) {
|
|
|
|
size = FEC_MAX_FRAME_SIZE;
|
|
|
|
flags |= FEC_BD_TR | FEC_BD_LG;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Frames larger than the user limit just set error flags. */
|
|
|
|
if (size > (s->rcr >> 16)) {
|
|
|
|
flags |= FEC_BD_LG;
|
|
|
|
}
|
|
|
|
|
|
|
|
addr = s->rx_descriptor;
|
|
|
|
while (size > 0) {
|
|
|
|
imx_fec_read_bd(&bd, addr);
|
|
|
|
if ((bd.flags & FEC_BD_E) == 0) {
|
|
|
|
/* No descriptors available. Bail out. */
|
|
|
|
/*
|
|
|
|
* FIXME: This is wrong. We should probably either
|
|
|
|
* save the remainder for when more RX buffers are
|
|
|
|
* available, or flag an error.
|
|
|
|
*/
|
2015-10-25 15:16:21 +01:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Lost end of frame\n",
|
2015-09-07 11:39:30 +02:00
|
|
|
TYPE_IMX_FEC, __func__);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
buf_len = (size <= s->emrbr) ? size : s->emrbr;
|
|
|
|
bd.length = buf_len;
|
|
|
|
size -= buf_len;
|
2015-10-25 15:16:21 +01:00
|
|
|
|
|
|
|
FEC_PRINTF("rx_bd 0x%x length %d\n", addr, bd.length);
|
|
|
|
|
2015-09-07 11:39:30 +02:00
|
|
|
/* The last 4 bytes are the CRC. */
|
|
|
|
if (size < 4) {
|
|
|
|
buf_len += size - 4;
|
|
|
|
}
|
|
|
|
buf_addr = bd.data;
|
|
|
|
dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
|
|
|
|
buf += buf_len;
|
|
|
|
if (size < 4) {
|
|
|
|
dma_memory_write(&address_space_memory, buf_addr + buf_len,
|
|
|
|
crc_ptr, 4 - size);
|
|
|
|
crc_ptr += 4 - size;
|
|
|
|
}
|
|
|
|
bd.flags &= ~FEC_BD_E;
|
|
|
|
if (size == 0) {
|
|
|
|
/* Last buffer in frame. */
|
|
|
|
bd.flags |= flags | FEC_BD_L;
|
|
|
|
FEC_PRINTF("rx frame flags %04x\n", bd.flags);
|
|
|
|
s->eir |= FEC_INT_RXF;
|
|
|
|
} else {
|
|
|
|
s->eir |= FEC_INT_RXB;
|
|
|
|
}
|
|
|
|
imx_fec_write_bd(&bd, addr);
|
|
|
|
/* Advance to the next descriptor. */
|
|
|
|
if ((bd.flags & FEC_BD_W) != 0) {
|
|
|
|
addr = s->erdsr;
|
|
|
|
} else {
|
|
|
|
addr += 8;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
s->rx_descriptor = addr;
|
|
|
|
imx_fec_enable_rx(s);
|
|
|
|
imx_fec_update(s);
|
|
|
|
return len;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps imx_fec_ops = {
|
|
|
|
.read = imx_fec_read,
|
|
|
|
.write = imx_fec_write,
|
|
|
|
.valid.min_access_size = 4,
|
|
|
|
.valid.max_access_size = 4,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void imx_fec_cleanup(NetClientState *nc)
|
|
|
|
{
|
|
|
|
IMXFECState *s = IMX_FEC(qemu_get_nic_opaque(nc));
|
|
|
|
|
|
|
|
s->nic = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static NetClientInfo net_imx_fec_info = {
|
|
|
|
.type = NET_CLIENT_OPTIONS_KIND_NIC,
|
|
|
|
.size = sizeof(NICState),
|
|
|
|
.can_receive = imx_fec_can_receive,
|
|
|
|
.receive = imx_fec_receive,
|
|
|
|
.cleanup = imx_fec_cleanup,
|
|
|
|
.link_status_changed = imx_fec_set_link,
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
static void imx_fec_realize(DeviceState *dev, Error **errp)
|
|
|
|
{
|
|
|
|
IMXFECState *s = IMX_FEC(dev);
|
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
|
|
|
|
|
|
|
memory_region_init_io(&s->iomem, OBJECT(dev), &imx_fec_ops, s,
|
|
|
|
TYPE_IMX_FEC, 0x400);
|
|
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
|
|
|
sysbus_init_irq(sbd, &s->irq);
|
|
|
|
qemu_macaddr_default_if_unset(&s->conf.macaddr);
|
|
|
|
|
|
|
|
s->conf.peers.ncs[0] = nd_table[0].netdev;
|
|
|
|
|
|
|
|
s->nic = qemu_new_nic(&net_imx_fec_info, &s->conf,
|
|
|
|
object_get_typename(OBJECT(dev)), DEVICE(dev)->id,
|
|
|
|
s);
|
|
|
|
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
|
|
|
|
}
|
|
|
|
|
|
|
|
static Property imx_fec_properties[] = {
|
|
|
|
DEFINE_NIC_PROPERTIES(IMXFECState, conf),
|
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
|
|
|
static void imx_fec_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
dc->vmsd = &vmstate_imx_fec;
|
|
|
|
dc->reset = imx_fec_reset;
|
|
|
|
dc->props = imx_fec_properties;
|
|
|
|
dc->realize = imx_fec_realize;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo imx_fec_info = {
|
|
|
|
.name = TYPE_IMX_FEC,
|
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(IMXFECState),
|
|
|
|
.class_init = imx_fec_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void imx_fec_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&imx_fec_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(imx_fec_register_types)
|