2007-01-15 19:32:02 +01:00
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/*
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* QEMU GT64120 PCI host
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*
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2007-01-24 02:47:51 +01:00
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* Copyright (c) 2006,2007 Aurelien Jarno
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2007-09-16 23:08:06 +02:00
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*
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2007-01-15 19:32:02 +01:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2016-01-18 18:35:00 +01:00
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#include "qemu/osdep.h"
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qdev: Convert uses of qdev_create() with Coccinelle
This is the transformation explained in the commit before previous.
Takes care of just one pattern that needs conversion. More to come in
this series.
Coccinelle script:
@ depends on !(file in "hw/arm/highbank.c")@
expression bus, type_name, dev, expr;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr;
identifier DOWN;
@@
- dev = DOWN(qdev_create(bus, type_name));
+ dev = DOWN(qdev_new(type_name));
... when != dev = expr
- qdev_init_nofail(DEVICE(dev));
+ qdev_realize_and_unref(DEVICE(dev), bus, &error_fatal);
@@
expression bus, type_name, expr;
identifier dev;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr, errp;
symbol true;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
@@
expression bus, type_name, expr, errp;
identifier dev;
symbol true;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
The first rule exempts hw/arm/highbank.c, because it matches along two
control flow paths there, with different @type_name. Covered by the
next commit's manual conversions.
Missing #include "qapi/error.h" added manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-10-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 07:31:58 +02:00
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#include "qapi/error.h"
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2019-06-25 00:28:41 +02:00
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#include "qemu/units.h"
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2019-06-25 00:28:39 +02:00
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#include "qemu/log.h"
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2013-02-05 17:06:20 +01:00
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#include "hw/mips/mips.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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2019-02-02 01:13:12 +01:00
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#include "hw/southbridge/piix.h"
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2019-08-12 07:23:45 +02:00
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#include "migration/vmstate.h"
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2019-12-12 17:15:43 +01:00
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#include "hw/intc/i8259.h"
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2019-08-12 07:23:42 +02:00
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#include "hw/irq.h"
|
2012-12-17 18:19:49 +01:00
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#include "exec/address-spaces.h"
|
2019-06-25 00:28:40 +02:00
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#include "trace.h"
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2020-09-03 22:43:22 +02:00
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#include "qom/object.h"
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2007-06-07 19:00:37 +02:00
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2019-06-25 00:28:36 +02:00
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#define GT_REGS (0x1000 >> 2)
|
2007-01-15 19:32:02 +01:00
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/* CPU Configuration */
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2019-06-25 00:28:36 +02:00
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#define GT_CPU (0x000 >> 2)
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#define GT_MULTI (0x120 >> 2)
|
2007-01-15 19:32:02 +01:00
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/* CPU Address Decode */
|
2019-06-25 00:28:36 +02:00
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#define GT_SCS10LD (0x008 >> 2)
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#define GT_SCS10HD (0x010 >> 2)
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#define GT_SCS32LD (0x018 >> 2)
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#define GT_SCS32HD (0x020 >> 2)
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#define GT_CS20LD (0x028 >> 2)
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#define GT_CS20HD (0x030 >> 2)
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#define GT_CS3BOOTLD (0x038 >> 2)
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#define GT_CS3BOOTHD (0x040 >> 2)
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#define GT_PCI0IOLD (0x048 >> 2)
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#define GT_PCI0IOHD (0x050 >> 2)
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#define GT_PCI0M0LD (0x058 >> 2)
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#define GT_PCI0M0HD (0x060 >> 2)
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#define GT_PCI0M1LD (0x080 >> 2)
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#define GT_PCI0M1HD (0x088 >> 2)
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#define GT_PCI1IOLD (0x090 >> 2)
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#define GT_PCI1IOHD (0x098 >> 2)
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#define GT_PCI1M0LD (0x0a0 >> 2)
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#define GT_PCI1M0HD (0x0a8 >> 2)
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#define GT_PCI1M1LD (0x0b0 >> 2)
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#define GT_PCI1M1HD (0x0b8 >> 2)
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#define GT_ISD (0x068 >> 2)
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#define GT_SCS10AR (0x0d0 >> 2)
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#define GT_SCS32AR (0x0d8 >> 2)
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#define GT_CS20R (0x0e0 >> 2)
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#define GT_CS3BOOTR (0x0e8 >> 2)
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#define GT_PCI0IOREMAP (0x0f0 >> 2)
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#define GT_PCI0M0REMAP (0x0f8 >> 2)
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#define GT_PCI0M1REMAP (0x100 >> 2)
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#define GT_PCI1IOREMAP (0x108 >> 2)
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#define GT_PCI1M0REMAP (0x110 >> 2)
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#define GT_PCI1M1REMAP (0x118 >> 2)
|
2007-01-15 19:32:02 +01:00
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/* CPU Error Report */
|
2019-06-25 00:28:36 +02:00
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#define GT_CPUERR_ADDRLO (0x070 >> 2)
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#define GT_CPUERR_ADDRHI (0x078 >> 2)
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#define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
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#define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
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#define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
|
2007-01-15 19:32:02 +01:00
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/* CPU Sync Barrier */
|
2019-06-25 00:28:36 +02:00
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#define GT_PCI0SYNC (0x0c0 >> 2)
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#define GT_PCI1SYNC (0x0c8 >> 2)
|
2007-01-15 19:32:02 +01:00
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/* SDRAM and Device Address Decode */
|
2019-06-25 00:28:36 +02:00
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#define GT_SCS0LD (0x400 >> 2)
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#define GT_SCS0HD (0x404 >> 2)
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#define GT_SCS1LD (0x408 >> 2)
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#define GT_SCS1HD (0x40c >> 2)
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#define GT_SCS2LD (0x410 >> 2)
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#define GT_SCS2HD (0x414 >> 2)
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#define GT_SCS3LD (0x418 >> 2)
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#define GT_SCS3HD (0x41c >> 2)
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#define GT_CS0LD (0x420 >> 2)
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#define GT_CS0HD (0x424 >> 2)
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#define GT_CS1LD (0x428 >> 2)
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#define GT_CS1HD (0x42c >> 2)
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#define GT_CS2LD (0x430 >> 2)
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#define GT_CS2HD (0x434 >> 2)
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#define GT_CS3LD (0x438 >> 2)
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#define GT_CS3HD (0x43c >> 2)
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#define GT_BOOTLD (0x440 >> 2)
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#define GT_BOOTHD (0x444 >> 2)
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#define GT_ADERR (0x470 >> 2)
|
2007-01-15 19:32:02 +01:00
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/* SDRAM Configuration */
|
2019-06-25 00:28:36 +02:00
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#define GT_SDRAM_CFG (0x448 >> 2)
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#define GT_SDRAM_OPMODE (0x474 >> 2)
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#define GT_SDRAM_BM (0x478 >> 2)
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#define GT_SDRAM_ADDRDECODE (0x47c >> 2)
|
2007-01-15 19:32:02 +01:00
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/* SDRAM Parameters */
|
2019-06-25 00:28:36 +02:00
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#define GT_SDRAM_B0 (0x44c >> 2)
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#define GT_SDRAM_B1 (0x450 >> 2)
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#define GT_SDRAM_B2 (0x454 >> 2)
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#define GT_SDRAM_B3 (0x458 >> 2)
|
2007-01-15 19:32:02 +01:00
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/* Device Parameters */
|
2019-06-25 00:28:36 +02:00
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#define GT_DEV_B0 (0x45c >> 2)
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#define GT_DEV_B1 (0x460 >> 2)
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#define GT_DEV_B2 (0x464 >> 2)
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#define GT_DEV_B3 (0x468 >> 2)
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#define GT_DEV_BOOT (0x46c >> 2)
|
2007-01-15 19:32:02 +01:00
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/* ECC */
|
2019-06-25 00:28:36 +02:00
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#define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
|
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#define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
|
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#define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
|
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#define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
|
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#define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
|
2007-01-15 19:32:02 +01:00
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/* DMA Record */
|
2019-06-25 00:28:36 +02:00
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#define GT_DMA0_CNT (0x800 >> 2)
|
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#define GT_DMA1_CNT (0x804 >> 2)
|
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#define GT_DMA2_CNT (0x808 >> 2)
|
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#define GT_DMA3_CNT (0x80c >> 2)
|
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#define GT_DMA0_SA (0x810 >> 2)
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#define GT_DMA1_SA (0x814 >> 2)
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#define GT_DMA2_SA (0x818 >> 2)
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#define GT_DMA3_SA (0x81c >> 2)
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#define GT_DMA0_DA (0x820 >> 2)
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#define GT_DMA1_DA (0x824 >> 2)
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#define GT_DMA2_DA (0x828 >> 2)
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#define GT_DMA3_DA (0x82c >> 2)
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#define GT_DMA0_NEXT (0x830 >> 2)
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#define GT_DMA1_NEXT (0x834 >> 2)
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#define GT_DMA2_NEXT (0x838 >> 2)
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#define GT_DMA3_NEXT (0x83c >> 2)
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#define GT_DMA0_CUR (0x870 >> 2)
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#define GT_DMA1_CUR (0x874 >> 2)
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#define GT_DMA2_CUR (0x878 >> 2)
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#define GT_DMA3_CUR (0x87c >> 2)
|
2007-01-15 19:32:02 +01:00
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/* DMA Channel Control */
|
2019-06-25 00:28:36 +02:00
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#define GT_DMA0_CTRL (0x840 >> 2)
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#define GT_DMA1_CTRL (0x844 >> 2)
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#define GT_DMA2_CTRL (0x848 >> 2)
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#define GT_DMA3_CTRL (0x84c >> 2)
|
2007-01-15 19:32:02 +01:00
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/* DMA Arbiter */
|
2019-06-25 00:28:36 +02:00
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#define GT_DMA_ARB (0x860 >> 2)
|
2007-01-15 19:32:02 +01:00
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/* Timer/Counter */
|
2019-06-25 00:28:36 +02:00
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#define GT_TC0 (0x850 >> 2)
|
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#define GT_TC1 (0x854 >> 2)
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#define GT_TC2 (0x858 >> 2)
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#define GT_TC3 (0x85c >> 2)
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#define GT_TC_CONTROL (0x864 >> 2)
|
2007-01-15 19:32:02 +01:00
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/* PCI Internal */
|
2019-06-25 00:28:36 +02:00
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#define GT_PCI0_CMD (0xc00 >> 2)
|
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#define GT_PCI0_TOR (0xc04 >> 2)
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#define GT_PCI0_BS_SCS10 (0xc08 >> 2)
|
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#define GT_PCI0_BS_SCS32 (0xc0c >> 2)
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#define GT_PCI0_BS_CS20 (0xc10 >> 2)
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#define GT_PCI0_BS_CS3BT (0xc14 >> 2)
|
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#define GT_PCI1_IACK (0xc30 >> 2)
|
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#define GT_PCI0_IACK (0xc34 >> 2)
|
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#define GT_PCI0_BARE (0xc3c >> 2)
|
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#define GT_PCI0_PREFMBR (0xc40 >> 2)
|
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#define GT_PCI0_SCS10_BAR (0xc48 >> 2)
|
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#define GT_PCI0_SCS32_BAR (0xc4c >> 2)
|
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#define GT_PCI0_CS20_BAR (0xc50 >> 2)
|
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#define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
|
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#define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
|
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#define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
|
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#define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
|
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#define GT_PCI1_CMD (0xc80 >> 2)
|
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|
#define GT_PCI1_TOR (0xc84 >> 2)
|
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|
#define GT_PCI1_BS_SCS10 (0xc88 >> 2)
|
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|
#define GT_PCI1_BS_SCS32 (0xc8c >> 2)
|
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|
#define GT_PCI1_BS_CS20 (0xc90 >> 2)
|
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|
#define GT_PCI1_BS_CS3BT (0xc94 >> 2)
|
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|
#define GT_PCI1_BARE (0xcbc >> 2)
|
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|
#define GT_PCI1_PREFMBR (0xcc0 >> 2)
|
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|
#define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
|
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|
#define GT_PCI1_SCS32_BAR (0xccc >> 2)
|
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|
#define GT_PCI1_CS20_BAR (0xcd0 >> 2)
|
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|
#define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
|
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|
|
#define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
|
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|
|
#define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
|
|
|
|
#define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
|
|
|
|
#define GT_PCI1_CFGADDR (0xcf0 >> 2)
|
|
|
|
#define GT_PCI1_CFGDATA (0xcf4 >> 2)
|
|
|
|
#define GT_PCI0_CFGADDR (0xcf8 >> 2)
|
|
|
|
#define GT_PCI0_CFGDATA (0xcfc >> 2)
|
2007-01-15 19:32:02 +01:00
|
|
|
|
|
|
|
/* Interrupts */
|
2019-06-25 00:28:36 +02:00
|
|
|
#define GT_INTRCAUSE (0xc18 >> 2)
|
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|
|
#define GT_INTRMASK (0xc1c >> 2)
|
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|
|
#define GT_PCI0_ICMASK (0xc24 >> 2)
|
|
|
|
#define GT_PCI0_SERR0MASK (0xc28 >> 2)
|
|
|
|
#define GT_CPU_INTSEL (0xc70 >> 2)
|
|
|
|
#define GT_PCI0_INTSEL (0xc74 >> 2)
|
|
|
|
#define GT_HINTRCAUSE (0xc98 >> 2)
|
|
|
|
#define GT_HINTRMASK (0xc9c >> 2)
|
|
|
|
#define GT_PCI0_HICMASK (0xca4 >> 2)
|
|
|
|
#define GT_PCI1_SERR1MASK (0xca8 >> 2)
|
2007-01-15 19:32:02 +01:00
|
|
|
|
2007-07-11 18:44:32 +02:00
|
|
|
#define PCI_MAPPING_ENTRY(regname) \
|
2012-10-23 12:30:10 +02:00
|
|
|
hwaddr regname ##_start; \
|
|
|
|
hwaddr regname ##_length; \
|
2011-08-15 16:17:21 +02:00
|
|
|
MemoryRegion regname ##_mem
|
2007-07-11 18:44:32 +02:00
|
|
|
|
2012-08-20 19:08:01 +02:00
|
|
|
#define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
|
|
|
|
|
2020-09-16 20:25:19 +02:00
|
|
|
OBJECT_DECLARE_SIMPLE_TYPE(GT64120State, GT64120_PCI_HOST_BRIDGE)
|
2012-08-20 19:08:01 +02:00
|
|
|
|
2020-09-03 22:43:22 +02:00
|
|
|
struct GT64120State {
|
2012-08-20 19:08:09 +02:00
|
|
|
PCIHostState parent_obj;
|
2012-08-20 19:08:01 +02:00
|
|
|
|
2007-01-15 19:32:02 +01:00
|
|
|
uint32_t regs[GT_REGS];
|
2007-07-11 18:44:32 +02:00
|
|
|
PCI_MAPPING_ENTRY(PCI0IO);
|
2015-02-01 09:12:55 +01:00
|
|
|
PCI_MAPPING_ENTRY(PCI0M0);
|
|
|
|
PCI_MAPPING_ENTRY(PCI0M1);
|
2007-07-11 18:44:32 +02:00
|
|
|
PCI_MAPPING_ENTRY(ISD);
|
2015-02-01 09:12:55 +01:00
|
|
|
MemoryRegion pci0_mem;
|
|
|
|
AddressSpace pci0_mem_as;
|
2020-09-03 22:43:22 +02:00
|
|
|
};
|
2007-01-15 19:32:02 +01:00
|
|
|
|
2007-07-11 18:44:32 +02:00
|
|
|
/* Adjust range to avoid touching space which isn't mappable via PCI */
|
2019-06-25 00:28:35 +02:00
|
|
|
/*
|
|
|
|
* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
|
|
|
|
* 0x1fc00000 - 0x1fd00000
|
|
|
|
*/
|
|
|
|
static void check_reserved_space(hwaddr *start, hwaddr *length)
|
2007-07-11 18:44:32 +02:00
|
|
|
{
|
2012-10-23 12:30:10 +02:00
|
|
|
hwaddr begin = *start;
|
|
|
|
hwaddr end = *start + *length;
|
2007-07-11 18:44:32 +02:00
|
|
|
|
2019-06-25 00:28:37 +02:00
|
|
|
if (end >= 0x1e000000LL && end < 0x1f100000LL) {
|
2007-07-11 18:44:32 +02:00
|
|
|
end = 0x1e000000LL;
|
2019-06-25 00:28:37 +02:00
|
|
|
}
|
|
|
|
if (begin >= 0x1e000000LL && begin < 0x1f100000LL) {
|
2007-07-11 18:44:32 +02:00
|
|
|
begin = 0x1f100000LL;
|
2019-06-25 00:28:37 +02:00
|
|
|
}
|
|
|
|
if (end >= 0x1fc00000LL && end < 0x1fd00000LL) {
|
2007-07-11 18:44:32 +02:00
|
|
|
end = 0x1fc00000LL;
|
2019-06-25 00:28:37 +02:00
|
|
|
}
|
|
|
|
if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) {
|
2007-07-11 18:44:32 +02:00
|
|
|
begin = 0x1fd00000LL;
|
2019-06-25 00:28:37 +02:00
|
|
|
}
|
2007-07-11 18:44:32 +02:00
|
|
|
/* XXX: This is broken when a reserved range splits the requested range */
|
2019-06-25 00:28:37 +02:00
|
|
|
if (end >= 0x1f100000LL && begin < 0x1e000000LL) {
|
2007-07-11 18:44:32 +02:00
|
|
|
end = 0x1e000000LL;
|
2019-06-25 00:28:37 +02:00
|
|
|
}
|
|
|
|
if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) {
|
2007-07-11 18:44:32 +02:00
|
|
|
end = 0x1fc00000LL;
|
2019-06-25 00:28:37 +02:00
|
|
|
}
|
2007-07-11 18:44:32 +02:00
|
|
|
|
|
|
|
*start = begin;
|
|
|
|
*length = end - begin;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void gt64120_isd_mapping(GT64120State *s)
|
|
|
|
{
|
2015-11-06 16:34:06 +01:00
|
|
|
/* Bits 14:0 of ISD map to bits 35:21 of the start address. */
|
|
|
|
hwaddr start = ((hwaddr)s->regs[GT_ISD] << 21) & 0xFFFE00000ull;
|
2012-10-23 12:30:10 +02:00
|
|
|
hwaddr length = 0x1000;
|
2007-07-11 18:44:32 +02:00
|
|
|
|
2011-08-15 16:17:21 +02:00
|
|
|
if (s->ISD_length) {
|
|
|
|
memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
|
|
|
|
}
|
2007-07-11 18:44:32 +02:00
|
|
|
check_reserved_space(&start, &length);
|
|
|
|
length = 0x1000;
|
|
|
|
/* Map new address */
|
2019-06-25 00:28:40 +02:00
|
|
|
trace_gt64120_isd_remap(s->ISD_length, s->ISD_start, length, start);
|
2007-07-11 18:44:32 +02:00
|
|
|
s->ISD_start = start;
|
|
|
|
s->ISD_length = length;
|
2011-08-15 16:17:21 +02:00
|
|
|
memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
|
2007-07-11 18:44:32 +02:00
|
|
|
}
|
|
|
|
|
2007-06-12 23:06:52 +02:00
|
|
|
static void gt64120_pci_mapping(GT64120State *s)
|
2007-06-10 17:08:43 +02:00
|
|
|
{
|
2015-02-01 09:12:55 +01:00
|
|
|
/* Update PCI0IO mapping */
|
|
|
|
if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) {
|
|
|
|
/* Unmap old IO address */
|
|
|
|
if (s->PCI0IO_length) {
|
|
|
|
memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem);
|
|
|
|
object_unparent(OBJECT(&s->PCI0IO_mem));
|
|
|
|
}
|
|
|
|
/* Map new IO address */
|
|
|
|
s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
|
|
|
|
s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) -
|
|
|
|
(s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
|
|
|
|
if (s->PCI0IO_length) {
|
|
|
|
memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "pci0-io",
|
|
|
|
get_system_io(), 0, s->PCI0IO_length);
|
|
|
|
memory_region_add_subregion(get_system_memory(), s->PCI0IO_start,
|
|
|
|
&s->PCI0IO_mem);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Update PCI0M0 mapping */
|
|
|
|
if ((s->regs[GT_PCI0M0LD] & 0x7f) <= s->regs[GT_PCI0M0HD]) {
|
|
|
|
/* Unmap old MEM address */
|
|
|
|
if (s->PCI0M0_length) {
|
|
|
|
memory_region_del_subregion(get_system_memory(), &s->PCI0M0_mem);
|
|
|
|
object_unparent(OBJECT(&s->PCI0M0_mem));
|
|
|
|
}
|
|
|
|
/* Map new mem address */
|
|
|
|
s->PCI0M0_start = s->regs[GT_PCI0M0LD] << 21;
|
|
|
|
s->PCI0M0_length = ((s->regs[GT_PCI0M0HD] + 1) -
|
|
|
|
(s->regs[GT_PCI0M0LD] & 0x7f)) << 21;
|
|
|
|
if (s->PCI0M0_length) {
|
|
|
|
memory_region_init_alias(&s->PCI0M0_mem, OBJECT(s), "pci0-mem0",
|
|
|
|
&s->pci0_mem, s->PCI0M0_start,
|
|
|
|
s->PCI0M0_length);
|
|
|
|
memory_region_add_subregion(get_system_memory(), s->PCI0M0_start,
|
|
|
|
&s->PCI0M0_mem);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Update PCI0M1 mapping */
|
|
|
|
if ((s->regs[GT_PCI0M1LD] & 0x7f) <= s->regs[GT_PCI0M1HD]) {
|
|
|
|
/* Unmap old MEM address */
|
|
|
|
if (s->PCI0M1_length) {
|
|
|
|
memory_region_del_subregion(get_system_memory(), &s->PCI0M1_mem);
|
|
|
|
object_unparent(OBJECT(&s->PCI0M1_mem));
|
|
|
|
}
|
|
|
|
/* Map new mem address */
|
|
|
|
s->PCI0M1_start = s->regs[GT_PCI0M1LD] << 21;
|
|
|
|
s->PCI0M1_length = ((s->regs[GT_PCI0M1HD] + 1) -
|
|
|
|
(s->regs[GT_PCI0M1LD] & 0x7f)) << 21;
|
|
|
|
if (s->PCI0M1_length) {
|
|
|
|
memory_region_init_alias(&s->PCI0M1_mem, OBJECT(s), "pci0-mem1",
|
|
|
|
&s->pci0_mem, s->PCI0M1_start,
|
|
|
|
s->PCI0M1_length);
|
|
|
|
memory_region_add_subregion(get_system_memory(), s->PCI0M1_start,
|
|
|
|
&s->PCI0M1_mem);
|
|
|
|
}
|
2007-06-12 23:06:52 +02:00
|
|
|
}
|
2007-06-10 17:08:43 +02:00
|
|
|
}
|
|
|
|
|
2014-06-20 15:59:58 +02:00
|
|
|
static int gt64120_post_load(void *opaque, int version_id)
|
|
|
|
{
|
|
|
|
GT64120State *s = opaque;
|
|
|
|
|
|
|
|
gt64120_isd_mapping(s);
|
|
|
|
gt64120_pci_mapping(s);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const VMStateDescription vmstate_gt64120 = {
|
|
|
|
.name = "gt64120",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
|
|
|
.post_load = gt64120_post_load,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_UINT32_ARRAY(regs, GT64120State, GT_REGS),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2019-06-25 00:28:38 +02:00
|
|
|
static void gt64120_writel(void *opaque, hwaddr addr,
|
|
|
|
uint64_t val, unsigned size)
|
2007-01-15 19:32:02 +01:00
|
|
|
{
|
|
|
|
GT64120State *s = opaque;
|
2012-08-20 19:08:09 +02:00
|
|
|
PCIHostState *phb = PCI_HOST_BRIDGE(s);
|
2021-03-04 19:25:11 +01:00
|
|
|
uint32_t saddr = addr >> 2;
|
2007-01-15 19:32:02 +01:00
|
|
|
|
2021-03-04 19:02:56 +01:00
|
|
|
trace_gt64120_write(addr, val);
|
2019-06-25 00:28:37 +02:00
|
|
|
if (!(s->regs[GT_CPU] & 0x00001000)) {
|
2007-10-20 21:47:14 +02:00
|
|
|
val = bswap32(val);
|
2019-06-25 00:28:37 +02:00
|
|
|
}
|
2007-01-18 00:35:01 +01:00
|
|
|
|
2007-01-15 19:32:02 +01:00
|
|
|
switch (saddr) {
|
2007-01-18 00:35:01 +01:00
|
|
|
|
|
|
|
/* CPU Configuration */
|
2007-01-15 19:32:02 +01:00
|
|
|
case GT_CPU:
|
|
|
|
s->regs[GT_CPU] = val;
|
|
|
|
break;
|
|
|
|
case GT_MULTI:
|
2018-12-13 23:37:37 +01:00
|
|
|
/* Read-only register as only one GT64xxx is present on the CPU bus */
|
2007-01-15 19:32:02 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
/* CPU Address Decode */
|
|
|
|
case GT_PCI0IOLD:
|
|
|
|
s->regs[GT_PCI0IOLD] = val & 0x00007fff;
|
|
|
|
s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
|
2007-06-12 23:06:52 +02:00
|
|
|
gt64120_pci_mapping(s);
|
2007-01-15 19:32:02 +01:00
|
|
|
break;
|
|
|
|
case GT_PCI0M0LD:
|
|
|
|
s->regs[GT_PCI0M0LD] = val & 0x00007fff;
|
|
|
|
s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
|
2015-02-01 09:12:55 +01:00
|
|
|
gt64120_pci_mapping(s);
|
2007-01-15 19:32:02 +01:00
|
|
|
break;
|
|
|
|
case GT_PCI0M1LD:
|
|
|
|
s->regs[GT_PCI0M1LD] = val & 0x00007fff;
|
|
|
|
s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
|
2015-02-01 09:12:55 +01:00
|
|
|
gt64120_pci_mapping(s);
|
2007-01-15 19:32:02 +01:00
|
|
|
break;
|
|
|
|
case GT_PCI1IOLD:
|
|
|
|
s->regs[GT_PCI1IOLD] = val & 0x00007fff;
|
|
|
|
s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
|
|
|
|
break;
|
|
|
|
case GT_PCI1M0LD:
|
|
|
|
s->regs[GT_PCI1M0LD] = val & 0x00007fff;
|
|
|
|
s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
|
|
|
|
break;
|
|
|
|
case GT_PCI1M1LD:
|
|
|
|
s->regs[GT_PCI1M1LD] = val & 0x00007fff;
|
|
|
|
s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
|
|
|
|
break;
|
2015-02-01 09:12:55 +01:00
|
|
|
case GT_PCI0M0HD:
|
|
|
|
case GT_PCI0M1HD:
|
2007-01-15 19:32:02 +01:00
|
|
|
case GT_PCI0IOHD:
|
2007-07-12 00:45:45 +02:00
|
|
|
s->regs[saddr] = val & 0x0000007f;
|
|
|
|
gt64120_pci_mapping(s);
|
|
|
|
break;
|
2007-01-15 19:32:02 +01:00
|
|
|
case GT_PCI1IOHD:
|
|
|
|
case GT_PCI1M0HD:
|
|
|
|
case GT_PCI1M1HD:
|
|
|
|
s->regs[saddr] = val & 0x0000007f;
|
|
|
|
break;
|
2007-07-11 18:44:32 +02:00
|
|
|
case GT_ISD:
|
|
|
|
s->regs[saddr] = val & 0x00007fff;
|
|
|
|
gt64120_isd_mapping(s);
|
|
|
|
break;
|
|
|
|
|
2007-01-15 19:32:02 +01:00
|
|
|
case GT_PCI0IOREMAP:
|
|
|
|
case GT_PCI0M0REMAP:
|
|
|
|
case GT_PCI0M1REMAP:
|
|
|
|
case GT_PCI1IOREMAP:
|
|
|
|
case GT_PCI1M0REMAP:
|
|
|
|
case GT_PCI1M1REMAP:
|
|
|
|
s->regs[saddr] = val & 0x000007ff;
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* CPU Error Report */
|
|
|
|
case GT_CPUERR_ADDRLO:
|
|
|
|
case GT_CPUERR_ADDRHI:
|
|
|
|
case GT_CPUERR_DATALO:
|
|
|
|
case GT_CPUERR_DATAHI:
|
|
|
|
case GT_CPUERR_PARITY:
|
2018-12-13 23:37:37 +01:00
|
|
|
/* Read-only registers, do nothing */
|
2019-06-25 00:28:39 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"gt64120: Read-only register write "
|
2021-03-03 00:20:21 +01:00
|
|
|
"reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
|
2019-06-25 00:28:39 +02:00
|
|
|
saddr << 2, size, size << 1, val);
|
2007-01-18 00:35:01 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
/* CPU Sync Barrier */
|
|
|
|
case GT_PCI0SYNC:
|
|
|
|
case GT_PCI1SYNC:
|
2018-12-13 23:37:37 +01:00
|
|
|
/* Read-only registers, do nothing */
|
2019-06-25 00:28:39 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"gt64120: Read-only register write "
|
2021-03-03 00:20:21 +01:00
|
|
|
"reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
|
2019-06-25 00:28:39 +02:00
|
|
|
saddr << 2, size, size << 1, val);
|
2007-01-15 19:32:02 +01:00
|
|
|
break;
|
|
|
|
|
2007-06-07 19:00:37 +02:00
|
|
|
/* SDRAM and Device Address Decode */
|
|
|
|
case GT_SCS0LD:
|
|
|
|
case GT_SCS0HD:
|
|
|
|
case GT_SCS1LD:
|
|
|
|
case GT_SCS1HD:
|
|
|
|
case GT_SCS2LD:
|
|
|
|
case GT_SCS2HD:
|
|
|
|
case GT_SCS3LD:
|
|
|
|
case GT_SCS3HD:
|
|
|
|
case GT_CS0LD:
|
|
|
|
case GT_CS0HD:
|
|
|
|
case GT_CS1LD:
|
|
|
|
case GT_CS1HD:
|
|
|
|
case GT_CS2LD:
|
|
|
|
case GT_CS2HD:
|
|
|
|
case GT_CS3LD:
|
|
|
|
case GT_CS3HD:
|
|
|
|
case GT_BOOTLD:
|
|
|
|
case GT_BOOTHD:
|
|
|
|
case GT_ADERR:
|
|
|
|
/* SDRAM Configuration */
|
|
|
|
case GT_SDRAM_CFG:
|
|
|
|
case GT_SDRAM_OPMODE:
|
|
|
|
case GT_SDRAM_BM:
|
|
|
|
case GT_SDRAM_ADDRDECODE:
|
|
|
|
/* Accept and ignore SDRAM interleave configuration */
|
|
|
|
s->regs[saddr] = val;
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* Device Parameters */
|
|
|
|
case GT_DEV_B0:
|
|
|
|
case GT_DEV_B1:
|
|
|
|
case GT_DEV_B2:
|
|
|
|
case GT_DEV_B3:
|
|
|
|
case GT_DEV_BOOT:
|
|
|
|
/* Not implemented */
|
2019-06-25 00:28:39 +02:00
|
|
|
qemu_log_mask(LOG_UNIMP,
|
|
|
|
"gt64120: Unimplemented device register write "
|
2021-03-03 00:20:21 +01:00
|
|
|
"reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
|
2019-06-25 00:28:39 +02:00
|
|
|
saddr << 2, size, size << 1, val);
|
2007-06-07 19:00:37 +02:00
|
|
|
break;
|
|
|
|
|
2007-01-15 19:32:02 +01:00
|
|
|
/* ECC */
|
|
|
|
case GT_ECC_ERRDATALO:
|
|
|
|
case GT_ECC_ERRDATAHI:
|
|
|
|
case GT_ECC_MEM:
|
|
|
|
case GT_ECC_CALC:
|
|
|
|
case GT_ECC_ERRADDR:
|
2007-01-18 00:35:01 +01:00
|
|
|
/* Read-only registers, do nothing */
|
2019-06-25 00:28:39 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"gt64120: Read-only register write "
|
2021-03-03 00:20:21 +01:00
|
|
|
"reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
|
2019-06-25 00:28:39 +02:00
|
|
|
saddr << 2, size, size << 1, val);
|
2007-01-15 19:32:02 +01:00
|
|
|
break;
|
|
|
|
|
2007-06-07 19:00:37 +02:00
|
|
|
/* DMA Record */
|
|
|
|
case GT_DMA0_CNT:
|
|
|
|
case GT_DMA1_CNT:
|
|
|
|
case GT_DMA2_CNT:
|
|
|
|
case GT_DMA3_CNT:
|
|
|
|
case GT_DMA0_SA:
|
|
|
|
case GT_DMA1_SA:
|
|
|
|
case GT_DMA2_SA:
|
|
|
|
case GT_DMA3_SA:
|
|
|
|
case GT_DMA0_DA:
|
|
|
|
case GT_DMA1_DA:
|
|
|
|
case GT_DMA2_DA:
|
|
|
|
case GT_DMA3_DA:
|
|
|
|
case GT_DMA0_NEXT:
|
|
|
|
case GT_DMA1_NEXT:
|
|
|
|
case GT_DMA2_NEXT:
|
|
|
|
case GT_DMA3_NEXT:
|
|
|
|
case GT_DMA0_CUR:
|
|
|
|
case GT_DMA1_CUR:
|
|
|
|
case GT_DMA2_CUR:
|
|
|
|
case GT_DMA3_CUR:
|
|
|
|
|
|
|
|
/* DMA Channel Control */
|
|
|
|
case GT_DMA0_CTRL:
|
|
|
|
case GT_DMA1_CTRL:
|
|
|
|
case GT_DMA2_CTRL:
|
|
|
|
case GT_DMA3_CTRL:
|
|
|
|
|
|
|
|
/* DMA Arbiter */
|
|
|
|
case GT_DMA_ARB:
|
|
|
|
/* Not implemented */
|
2019-06-25 00:28:39 +02:00
|
|
|
qemu_log_mask(LOG_UNIMP,
|
|
|
|
"gt64120: Unimplemented DMA register write "
|
2021-03-03 00:20:21 +01:00
|
|
|
"reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
|
2019-06-25 00:28:39 +02:00
|
|
|
saddr << 2, size, size << 1, val);
|
2007-06-07 19:00:37 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
/* Timer/Counter */
|
|
|
|
case GT_TC0:
|
|
|
|
case GT_TC1:
|
|
|
|
case GT_TC2:
|
|
|
|
case GT_TC3:
|
|
|
|
case GT_TC_CONTROL:
|
|
|
|
/* Not implemented */
|
2019-06-25 00:28:39 +02:00
|
|
|
qemu_log_mask(LOG_UNIMP,
|
|
|
|
"gt64120: Unimplemented timer register write "
|
2021-03-03 00:20:21 +01:00
|
|
|
"reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
|
2019-06-25 00:28:39 +02:00
|
|
|
saddr << 2, size, size << 1, val);
|
2007-06-07 19:00:37 +02:00
|
|
|
break;
|
|
|
|
|
2007-01-15 19:32:02 +01:00
|
|
|
/* PCI Internal */
|
|
|
|
case GT_PCI0_CMD:
|
|
|
|
case GT_PCI1_CMD:
|
|
|
|
s->regs[saddr] = val & 0x0401fc0f;
|
|
|
|
break;
|
2007-06-07 19:00:37 +02:00
|
|
|
case GT_PCI0_TOR:
|
|
|
|
case GT_PCI0_BS_SCS10:
|
|
|
|
case GT_PCI0_BS_SCS32:
|
|
|
|
case GT_PCI0_BS_CS20:
|
|
|
|
case GT_PCI0_BS_CS3BT:
|
|
|
|
case GT_PCI1_IACK:
|
|
|
|
case GT_PCI0_IACK:
|
|
|
|
case GT_PCI0_BARE:
|
|
|
|
case GT_PCI0_PREFMBR:
|
|
|
|
case GT_PCI0_SCS10_BAR:
|
|
|
|
case GT_PCI0_SCS32_BAR:
|
|
|
|
case GT_PCI0_CS20_BAR:
|
|
|
|
case GT_PCI0_CS3BT_BAR:
|
|
|
|
case GT_PCI0_SSCS10_BAR:
|
|
|
|
case GT_PCI0_SSCS32_BAR:
|
|
|
|
case GT_PCI0_SCS3BT_BAR:
|
|
|
|
case GT_PCI1_TOR:
|
|
|
|
case GT_PCI1_BS_SCS10:
|
|
|
|
case GT_PCI1_BS_SCS32:
|
|
|
|
case GT_PCI1_BS_CS20:
|
|
|
|
case GT_PCI1_BS_CS3BT:
|
|
|
|
case GT_PCI1_BARE:
|
|
|
|
case GT_PCI1_PREFMBR:
|
|
|
|
case GT_PCI1_SCS10_BAR:
|
|
|
|
case GT_PCI1_SCS32_BAR:
|
|
|
|
case GT_PCI1_CS20_BAR:
|
|
|
|
case GT_PCI1_CS3BT_BAR:
|
|
|
|
case GT_PCI1_SSCS10_BAR:
|
|
|
|
case GT_PCI1_SSCS32_BAR:
|
|
|
|
case GT_PCI1_SCS3BT_BAR:
|
|
|
|
case GT_PCI1_CFGADDR:
|
|
|
|
case GT_PCI1_CFGDATA:
|
|
|
|
/* not implemented */
|
2019-06-25 00:28:39 +02:00
|
|
|
qemu_log_mask(LOG_UNIMP,
|
2021-03-03 00:20:21 +01:00
|
|
|
"gt64120: Unimplemented PCI register write "
|
|
|
|
"reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
|
2019-06-25 00:28:39 +02:00
|
|
|
saddr << 2, size, size << 1, val);
|
2007-06-07 19:00:37 +02:00
|
|
|
break;
|
2007-01-15 19:32:02 +01:00
|
|
|
case GT_PCI0_CFGADDR:
|
2012-08-20 19:08:09 +02:00
|
|
|
phb->config_reg = val & 0x80fffffc;
|
2007-01-15 19:32:02 +01:00
|
|
|
break;
|
|
|
|
case GT_PCI0_CFGDATA:
|
2012-08-20 19:08:09 +02:00
|
|
|
if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
|
2008-03-10 01:12:14 +01:00
|
|
|
val = bswap32(val);
|
2012-08-20 19:08:09 +02:00
|
|
|
}
|
|
|
|
if (phb->config_reg & (1u << 31)) {
|
|
|
|
pci_data_write(phb->bus, phb->config_reg, val, 4);
|
|
|
|
}
|
2007-06-07 19:00:37 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
/* Interrupts */
|
|
|
|
case GT_INTRCAUSE:
|
|
|
|
/* not really implemented */
|
|
|
|
s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
|
|
|
|
s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
|
2021-03-03 00:10:01 +01:00
|
|
|
trace_gt64120_write_intreg("INTRCAUSE", size, val);
|
2007-06-07 19:00:37 +02:00
|
|
|
break;
|
|
|
|
case GT_INTRMASK:
|
|
|
|
s->regs[saddr] = val & 0x3c3ffffe;
|
2021-03-03 00:10:01 +01:00
|
|
|
trace_gt64120_write_intreg("INTRMASK", size, val);
|
2007-06-07 19:00:37 +02:00
|
|
|
break;
|
|
|
|
case GT_PCI0_ICMASK:
|
|
|
|
s->regs[saddr] = val & 0x03fffffe;
|
2021-03-03 00:10:01 +01:00
|
|
|
trace_gt64120_write_intreg("ICMASK", size, val);
|
2007-06-07 19:00:37 +02:00
|
|
|
break;
|
|
|
|
case GT_PCI0_SERR0MASK:
|
|
|
|
s->regs[saddr] = val & 0x0000003f;
|
2021-03-03 00:10:01 +01:00
|
|
|
trace_gt64120_write_intreg("SERR0MASK", size, val);
|
2007-06-07 19:00:37 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
/* Reserved when only PCI_0 is configured. */
|
|
|
|
case GT_HINTRCAUSE:
|
|
|
|
case GT_CPU_INTSEL:
|
|
|
|
case GT_PCI0_INTSEL:
|
|
|
|
case GT_HINTRMASK:
|
|
|
|
case GT_PCI0_HICMASK:
|
|
|
|
case GT_PCI1_SERR1MASK:
|
|
|
|
/* not implemented */
|
2007-01-15 19:32:02 +01:00
|
|
|
break;
|
|
|
|
|
2007-01-18 00:35:01 +01:00
|
|
|
/* SDRAM Parameters */
|
|
|
|
case GT_SDRAM_B0:
|
|
|
|
case GT_SDRAM_B1:
|
|
|
|
case GT_SDRAM_B2:
|
|
|
|
case GT_SDRAM_B3:
|
2019-06-25 00:28:35 +02:00
|
|
|
/*
|
|
|
|
* We don't simulate electrical parameters of the SDRAM.
|
|
|
|
* Accept, but ignore the values.
|
|
|
|
*/
|
2007-01-18 00:35:01 +01:00
|
|
|
s->regs[saddr] = val;
|
|
|
|
break;
|
|
|
|
|
2007-01-15 19:32:02 +01:00
|
|
|
default:
|
2019-06-25 00:28:39 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"gt64120: Illegal register write "
|
2021-03-03 00:20:21 +01:00
|
|
|
"reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
|
2019-06-25 00:28:39 +02:00
|
|
|
saddr << 2, size, size << 1, val);
|
2007-01-15 19:32:02 +01:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-06-25 00:28:38 +02:00
|
|
|
static uint64_t gt64120_readl(void *opaque,
|
|
|
|
hwaddr addr, unsigned size)
|
2007-01-15 19:32:02 +01:00
|
|
|
{
|
|
|
|
GT64120State *s = opaque;
|
2012-08-20 19:08:09 +02:00
|
|
|
PCIHostState *phb = PCI_HOST_BRIDGE(s);
|
2007-01-15 19:32:02 +01:00
|
|
|
uint32_t val;
|
2021-03-04 19:25:11 +01:00
|
|
|
uint32_t saddr = addr >> 2;
|
2007-01-15 19:32:02 +01:00
|
|
|
|
|
|
|
switch (saddr) {
|
|
|
|
|
2007-01-18 00:35:01 +01:00
|
|
|
/* CPU Configuration */
|
|
|
|
case GT_MULTI:
|
2019-06-25 00:28:35 +02:00
|
|
|
/*
|
|
|
|
* Only one GT64xxx is present on the CPU bus, return
|
|
|
|
* the initial value.
|
|
|
|
*/
|
2007-01-18 00:35:01 +01:00
|
|
|
val = s->regs[saddr];
|
|
|
|
break;
|
|
|
|
|
2007-01-15 19:32:02 +01:00
|
|
|
/* CPU Error Report */
|
|
|
|
case GT_CPUERR_ADDRLO:
|
|
|
|
case GT_CPUERR_ADDRHI:
|
|
|
|
case GT_CPUERR_DATALO:
|
|
|
|
case GT_CPUERR_DATAHI:
|
|
|
|
case GT_CPUERR_PARITY:
|
2019-06-25 00:28:35 +02:00
|
|
|
/* Emulated memory has no error, always return the initial values. */
|
2007-01-18 00:35:01 +01:00
|
|
|
val = s->regs[saddr];
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* CPU Sync Barrier */
|
|
|
|
case GT_PCI0SYNC:
|
|
|
|
case GT_PCI1SYNC:
|
2019-06-25 00:28:35 +02:00
|
|
|
/*
|
|
|
|
* Reading those register should empty all FIFO on the PCI
|
|
|
|
* bus, which are not emulated. The return value should be
|
|
|
|
* a random value that should be ignored.
|
|
|
|
*/
|
2007-09-16 23:08:06 +02:00
|
|
|
val = 0xc000ffee;
|
2007-01-15 19:32:02 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
/* ECC */
|
|
|
|
case GT_ECC_ERRDATALO:
|
|
|
|
case GT_ECC_ERRDATAHI:
|
|
|
|
case GT_ECC_MEM:
|
|
|
|
case GT_ECC_CALC:
|
|
|
|
case GT_ECC_ERRADDR:
|
2019-06-25 00:28:35 +02:00
|
|
|
/* Emulated memory has no error, always return the initial values. */
|
2007-01-18 00:35:01 +01:00
|
|
|
val = s->regs[saddr];
|
2007-01-15 19:32:02 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
case GT_CPU:
|
2007-06-07 19:00:37 +02:00
|
|
|
case GT_SCS10LD:
|
|
|
|
case GT_SCS10HD:
|
|
|
|
case GT_SCS32LD:
|
|
|
|
case GT_SCS32HD:
|
|
|
|
case GT_CS20LD:
|
|
|
|
case GT_CS20HD:
|
|
|
|
case GT_CS3BOOTLD:
|
|
|
|
case GT_CS3BOOTHD:
|
|
|
|
case GT_SCS10AR:
|
|
|
|
case GT_SCS32AR:
|
|
|
|
case GT_CS20R:
|
|
|
|
case GT_CS3BOOTR:
|
2007-01-15 19:32:02 +01:00
|
|
|
case GT_PCI0IOLD:
|
|
|
|
case GT_PCI0M0LD:
|
|
|
|
case GT_PCI0M1LD:
|
|
|
|
case GT_PCI1IOLD:
|
|
|
|
case GT_PCI1M0LD:
|
|
|
|
case GT_PCI1M1LD:
|
|
|
|
case GT_PCI0IOHD:
|
|
|
|
case GT_PCI0M0HD:
|
|
|
|
case GT_PCI0M1HD:
|
|
|
|
case GT_PCI1IOHD:
|
|
|
|
case GT_PCI1M0HD:
|
|
|
|
case GT_PCI1M1HD:
|
|
|
|
case GT_PCI0IOREMAP:
|
|
|
|
case GT_PCI0M0REMAP:
|
|
|
|
case GT_PCI0M1REMAP:
|
|
|
|
case GT_PCI1IOREMAP:
|
|
|
|
case GT_PCI1M0REMAP:
|
|
|
|
case GT_PCI1M1REMAP:
|
2007-06-07 19:00:37 +02:00
|
|
|
case GT_ISD:
|
2007-01-15 19:32:02 +01:00
|
|
|
val = s->regs[saddr];
|
|
|
|
break;
|
|
|
|
case GT_PCI0_IACK:
|
2007-09-16 23:08:06 +02:00
|
|
|
/* Read the IRQ number */
|
2007-01-24 02:47:51 +01:00
|
|
|
val = pic_read_irq(isa_pic);
|
2007-01-15 19:32:02 +01:00
|
|
|
break;
|
|
|
|
|
2007-06-07 19:00:37 +02:00
|
|
|
/* SDRAM and Device Address Decode */
|
|
|
|
case GT_SCS0LD:
|
|
|
|
case GT_SCS0HD:
|
|
|
|
case GT_SCS1LD:
|
|
|
|
case GT_SCS1HD:
|
|
|
|
case GT_SCS2LD:
|
|
|
|
case GT_SCS2HD:
|
|
|
|
case GT_SCS3LD:
|
|
|
|
case GT_SCS3HD:
|
|
|
|
case GT_CS0LD:
|
|
|
|
case GT_CS0HD:
|
|
|
|
case GT_CS1LD:
|
|
|
|
case GT_CS1HD:
|
|
|
|
case GT_CS2LD:
|
|
|
|
case GT_CS2HD:
|
|
|
|
case GT_CS3LD:
|
|
|
|
case GT_CS3HD:
|
|
|
|
case GT_BOOTLD:
|
|
|
|
case GT_BOOTHD:
|
|
|
|
case GT_ADERR:
|
|
|
|
val = s->regs[saddr];
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* SDRAM Configuration */
|
|
|
|
case GT_SDRAM_CFG:
|
|
|
|
case GT_SDRAM_OPMODE:
|
|
|
|
case GT_SDRAM_BM:
|
|
|
|
case GT_SDRAM_ADDRDECODE:
|
|
|
|
val = s->regs[saddr];
|
|
|
|
break;
|
|
|
|
|
2007-01-18 00:35:01 +01:00
|
|
|
/* SDRAM Parameters */
|
|
|
|
case GT_SDRAM_B0:
|
|
|
|
case GT_SDRAM_B1:
|
|
|
|
case GT_SDRAM_B2:
|
|
|
|
case GT_SDRAM_B3:
|
2019-06-25 00:28:35 +02:00
|
|
|
/*
|
|
|
|
* We don't simulate electrical parameters of the SDRAM.
|
|
|
|
* Just return the last written value.
|
|
|
|
*/
|
2007-01-18 00:35:01 +01:00
|
|
|
val = s->regs[saddr];
|
|
|
|
break;
|
|
|
|
|
2007-06-07 19:00:37 +02:00
|
|
|
/* Device Parameters */
|
|
|
|
case GT_DEV_B0:
|
|
|
|
case GT_DEV_B1:
|
|
|
|
case GT_DEV_B2:
|
|
|
|
case GT_DEV_B3:
|
|
|
|
case GT_DEV_BOOT:
|
|
|
|
val = s->regs[saddr];
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* DMA Record */
|
|
|
|
case GT_DMA0_CNT:
|
|
|
|
case GT_DMA1_CNT:
|
|
|
|
case GT_DMA2_CNT:
|
|
|
|
case GT_DMA3_CNT:
|
|
|
|
case GT_DMA0_SA:
|
|
|
|
case GT_DMA1_SA:
|
|
|
|
case GT_DMA2_SA:
|
|
|
|
case GT_DMA3_SA:
|
|
|
|
case GT_DMA0_DA:
|
|
|
|
case GT_DMA1_DA:
|
|
|
|
case GT_DMA2_DA:
|
|
|
|
case GT_DMA3_DA:
|
|
|
|
case GT_DMA0_NEXT:
|
|
|
|
case GT_DMA1_NEXT:
|
|
|
|
case GT_DMA2_NEXT:
|
|
|
|
case GT_DMA3_NEXT:
|
|
|
|
case GT_DMA0_CUR:
|
|
|
|
case GT_DMA1_CUR:
|
|
|
|
case GT_DMA2_CUR:
|
|
|
|
case GT_DMA3_CUR:
|
|
|
|
val = s->regs[saddr];
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* DMA Channel Control */
|
|
|
|
case GT_DMA0_CTRL:
|
|
|
|
case GT_DMA1_CTRL:
|
|
|
|
case GT_DMA2_CTRL:
|
|
|
|
case GT_DMA3_CTRL:
|
|
|
|
val = s->regs[saddr];
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* DMA Arbiter */
|
|
|
|
case GT_DMA_ARB:
|
|
|
|
val = s->regs[saddr];
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* Timer/Counter */
|
|
|
|
case GT_TC0:
|
|
|
|
case GT_TC1:
|
|
|
|
case GT_TC2:
|
|
|
|
case GT_TC3:
|
|
|
|
case GT_TC_CONTROL:
|
|
|
|
val = s->regs[saddr];
|
|
|
|
break;
|
|
|
|
|
2007-01-15 19:32:02 +01:00
|
|
|
/* PCI Internal */
|
|
|
|
case GT_PCI0_CFGADDR:
|
2012-08-20 19:08:09 +02:00
|
|
|
val = phb->config_reg;
|
2007-01-15 19:32:02 +01:00
|
|
|
break;
|
|
|
|
case GT_PCI0_CFGDATA:
|
2012-08-20 19:08:09 +02:00
|
|
|
if (!(phb->config_reg & (1 << 31))) {
|
2008-03-10 01:12:14 +01:00
|
|
|
val = 0xffffffff;
|
2012-08-20 19:08:09 +02:00
|
|
|
} else {
|
|
|
|
val = pci_data_read(phb->bus, phb->config_reg, 4);
|
|
|
|
}
|
|
|
|
if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
|
2008-03-10 01:12:14 +01:00
|
|
|
val = bswap32(val);
|
2012-08-20 19:08:09 +02:00
|
|
|
}
|
2007-06-07 19:00:37 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
case GT_PCI0_CMD:
|
|
|
|
case GT_PCI0_TOR:
|
|
|
|
case GT_PCI0_BS_SCS10:
|
|
|
|
case GT_PCI0_BS_SCS32:
|
|
|
|
case GT_PCI0_BS_CS20:
|
|
|
|
case GT_PCI0_BS_CS3BT:
|
|
|
|
case GT_PCI1_IACK:
|
|
|
|
case GT_PCI0_BARE:
|
|
|
|
case GT_PCI0_PREFMBR:
|
|
|
|
case GT_PCI0_SCS10_BAR:
|
|
|
|
case GT_PCI0_SCS32_BAR:
|
|
|
|
case GT_PCI0_CS20_BAR:
|
|
|
|
case GT_PCI0_CS3BT_BAR:
|
|
|
|
case GT_PCI0_SSCS10_BAR:
|
|
|
|
case GT_PCI0_SSCS32_BAR:
|
|
|
|
case GT_PCI0_SCS3BT_BAR:
|
|
|
|
case GT_PCI1_CMD:
|
|
|
|
case GT_PCI1_TOR:
|
|
|
|
case GT_PCI1_BS_SCS10:
|
|
|
|
case GT_PCI1_BS_SCS32:
|
|
|
|
case GT_PCI1_BS_CS20:
|
|
|
|
case GT_PCI1_BS_CS3BT:
|
|
|
|
case GT_PCI1_BARE:
|
|
|
|
case GT_PCI1_PREFMBR:
|
|
|
|
case GT_PCI1_SCS10_BAR:
|
|
|
|
case GT_PCI1_SCS32_BAR:
|
|
|
|
case GT_PCI1_CS20_BAR:
|
|
|
|
case GT_PCI1_CS3BT_BAR:
|
|
|
|
case GT_PCI1_SSCS10_BAR:
|
|
|
|
case GT_PCI1_SSCS32_BAR:
|
|
|
|
case GT_PCI1_SCS3BT_BAR:
|
|
|
|
case GT_PCI1_CFGADDR:
|
|
|
|
case GT_PCI1_CFGDATA:
|
|
|
|
val = s->regs[saddr];
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* Interrupts */
|
|
|
|
case GT_INTRCAUSE:
|
|
|
|
val = s->regs[saddr];
|
2021-03-03 00:10:01 +01:00
|
|
|
trace_gt64120_read_intreg("INTRCAUSE", size, val);
|
2007-06-07 19:00:37 +02:00
|
|
|
break;
|
|
|
|
case GT_INTRMASK:
|
|
|
|
val = s->regs[saddr];
|
2021-03-03 00:10:01 +01:00
|
|
|
trace_gt64120_read_intreg("INTRMASK", size, val);
|
2007-06-07 19:00:37 +02:00
|
|
|
break;
|
|
|
|
case GT_PCI0_ICMASK:
|
|
|
|
val = s->regs[saddr];
|
2021-03-03 00:10:01 +01:00
|
|
|
trace_gt64120_read_intreg("ICMASK", size, val);
|
2007-06-07 19:00:37 +02:00
|
|
|
break;
|
|
|
|
case GT_PCI0_SERR0MASK:
|
|
|
|
val = s->regs[saddr];
|
2021-03-03 00:10:01 +01:00
|
|
|
trace_gt64120_read_intreg("SERR0MASK", size, val);
|
2007-06-07 19:00:37 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
/* Reserved when only PCI_0 is configured. */
|
|
|
|
case GT_HINTRCAUSE:
|
|
|
|
case GT_CPU_INTSEL:
|
|
|
|
case GT_PCI0_INTSEL:
|
|
|
|
case GT_HINTRMASK:
|
|
|
|
case GT_PCI0_HICMASK:
|
|
|
|
case GT_PCI1_SERR1MASK:
|
|
|
|
val = s->regs[saddr];
|
2007-01-15 19:32:02 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
val = s->regs[saddr];
|
2019-06-25 00:28:39 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"gt64120: Illegal register read "
|
2021-03-03 00:20:21 +01:00
|
|
|
"reg:0x%03x size:%u value:0x%0*x\n",
|
2019-06-25 00:28:39 +02:00
|
|
|
saddr << 2, size, size << 1, val);
|
2007-01-15 19:32:02 +01:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2019-06-25 00:28:37 +02:00
|
|
|
if (!(s->regs[GT_CPU] & 0x00001000)) {
|
2007-10-20 21:47:14 +02:00
|
|
|
val = bswap32(val);
|
2019-06-25 00:28:37 +02:00
|
|
|
}
|
2021-03-04 19:02:56 +01:00
|
|
|
trace_gt64120_read(addr, val);
|
2007-10-20 21:47:14 +02:00
|
|
|
|
2007-06-07 19:00:37 +02:00
|
|
|
return val;
|
2007-01-15 19:32:02 +01:00
|
|
|
}
|
|
|
|
|
2011-08-15 16:17:21 +02:00
|
|
|
static const MemoryRegionOps isd_mem_ops = {
|
|
|
|
.read = gt64120_readl,
|
|
|
|
.write = gt64120_writel,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2021-03-04 19:25:11 +01:00
|
|
|
.impl = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
2007-01-15 19:32:02 +01:00
|
|
|
};
|
|
|
|
|
2011-01-19 23:10:40 +01:00
|
|
|
static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
|
2007-01-15 19:32:02 +01:00
|
|
|
{
|
|
|
|
int slot;
|
|
|
|
|
2020-10-11 17:04:23 +02:00
|
|
|
slot = PCI_SLOT(pci_dev->devfn);
|
2007-01-15 19:32:02 +01:00
|
|
|
|
|
|
|
switch (slot) {
|
2019-06-25 00:28:35 +02:00
|
|
|
/* PIIX4 USB */
|
|
|
|
case 10:
|
2007-01-15 19:32:02 +01:00
|
|
|
return 3;
|
2019-06-25 00:28:35 +02:00
|
|
|
/* AMD 79C973 Ethernet */
|
|
|
|
case 11:
|
2007-06-07 14:30:16 +02:00
|
|
|
return 1;
|
2019-06-25 00:28:35 +02:00
|
|
|
/* Crystal 4281 Sound */
|
|
|
|
case 12:
|
2007-06-07 14:30:16 +02:00
|
|
|
return 2;
|
2019-06-25 00:28:35 +02:00
|
|
|
/* PCI slot 1 to 4 */
|
|
|
|
case 18 ... 21:
|
2007-01-15 19:32:02 +01:00
|
|
|
return ((slot - 18) + irq_num) & 0x03;
|
2019-06-25 00:28:35 +02:00
|
|
|
/* Unknown device, don't do any translation */
|
|
|
|
default:
|
2007-01-15 19:32:02 +01:00
|
|
|
return irq_num;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pci_irq_levels[4];
|
|
|
|
|
2011-01-19 23:10:40 +01:00
|
|
|
static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
|
2007-01-15 19:32:02 +01:00
|
|
|
{
|
|
|
|
int i, pic_irq, pic_level;
|
2009-08-28 15:28:17 +02:00
|
|
|
qemu_irq *pic = opaque;
|
2007-01-15 19:32:02 +01:00
|
|
|
|
|
|
|
pci_irq_levels[irq_num] = level;
|
|
|
|
|
|
|
|
/* now we change the pic irq level according to the piix irq mappings */
|
|
|
|
/* XXX: optimize */
|
2019-10-15 14:05:42 +02:00
|
|
|
pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
|
2007-01-15 19:32:02 +01:00
|
|
|
if (pic_irq < 16) {
|
2019-06-25 00:28:35 +02:00
|
|
|
/* The pic level is the logical OR of all the PCI irqs mapped to it. */
|
2007-01-15 19:32:02 +01:00
|
|
|
pic_level = 0;
|
|
|
|
for (i = 0; i < 4; i++) {
|
2019-10-15 14:05:42 +02:00
|
|
|
if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
|
2007-01-15 19:32:02 +01:00
|
|
|
pic_level |= pci_irq_levels[i];
|
2019-06-25 00:28:37 +02:00
|
|
|
}
|
2007-01-15 19:32:02 +01:00
|
|
|
}
|
2007-04-07 20:14:41 +02:00
|
|
|
qemu_set_irq(pic[pic_irq], pic_level);
|
2007-01-15 19:32:02 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2018-10-02 23:25:16 +02:00
|
|
|
static void gt64120_reset(DeviceState *dev)
|
2007-01-15 19:32:02 +01:00
|
|
|
{
|
2018-10-02 23:25:16 +02:00
|
|
|
GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
|
2007-01-15 19:32:02 +01:00
|
|
|
|
2007-06-07 20:09:57 +02:00
|
|
|
/* FIXME: Malta specific hw assumptions ahead */
|
|
|
|
|
2007-01-15 19:32:02 +01:00
|
|
|
/* CPU Configuration */
|
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
|
|
s->regs[GT_CPU] = 0x00000000;
|
|
|
|
#else
|
2007-04-15 17:15:10 +02:00
|
|
|
s->regs[GT_CPU] = 0x00001000;
|
2007-01-15 19:32:02 +01:00
|
|
|
#endif
|
2007-06-07 20:09:57 +02:00
|
|
|
s->regs[GT_MULTI] = 0x00000003;
|
|
|
|
|
|
|
|
/* CPU Address decode */
|
|
|
|
s->regs[GT_SCS10LD] = 0x00000000;
|
|
|
|
s->regs[GT_SCS10HD] = 0x00000007;
|
|
|
|
s->regs[GT_SCS32LD] = 0x00000008;
|
|
|
|
s->regs[GT_SCS32HD] = 0x0000000f;
|
|
|
|
s->regs[GT_CS20LD] = 0x000000e0;
|
|
|
|
s->regs[GT_CS20HD] = 0x00000070;
|
|
|
|
s->regs[GT_CS3BOOTLD] = 0x000000f8;
|
|
|
|
s->regs[GT_CS3BOOTHD] = 0x0000007f;
|
2007-01-15 19:32:02 +01:00
|
|
|
|
|
|
|
s->regs[GT_PCI0IOLD] = 0x00000080;
|
|
|
|
s->regs[GT_PCI0IOHD] = 0x0000000f;
|
|
|
|
s->regs[GT_PCI0M0LD] = 0x00000090;
|
|
|
|
s->regs[GT_PCI0M0HD] = 0x0000001f;
|
2007-06-07 20:09:57 +02:00
|
|
|
s->regs[GT_ISD] = 0x000000a0;
|
2007-01-15 19:32:02 +01:00
|
|
|
s->regs[GT_PCI0M1LD] = 0x00000790;
|
|
|
|
s->regs[GT_PCI0M1HD] = 0x0000001f;
|
|
|
|
s->regs[GT_PCI1IOLD] = 0x00000100;
|
|
|
|
s->regs[GT_PCI1IOHD] = 0x0000000f;
|
|
|
|
s->regs[GT_PCI1M0LD] = 0x00000110;
|
|
|
|
s->regs[GT_PCI1M0HD] = 0x0000001f;
|
|
|
|
s->regs[GT_PCI1M1LD] = 0x00000120;
|
|
|
|
s->regs[GT_PCI1M1HD] = 0x0000002f;
|
2007-06-07 20:09:57 +02:00
|
|
|
|
|
|
|
s->regs[GT_SCS10AR] = 0x00000000;
|
|
|
|
s->regs[GT_SCS32AR] = 0x00000008;
|
|
|
|
s->regs[GT_CS20R] = 0x000000e0;
|
|
|
|
s->regs[GT_CS3BOOTR] = 0x000000f8;
|
|
|
|
|
2007-01-15 19:32:02 +01:00
|
|
|
s->regs[GT_PCI0IOREMAP] = 0x00000080;
|
|
|
|
s->regs[GT_PCI0M0REMAP] = 0x00000090;
|
|
|
|
s->regs[GT_PCI0M1REMAP] = 0x00000790;
|
|
|
|
s->regs[GT_PCI1IOREMAP] = 0x00000100;
|
|
|
|
s->regs[GT_PCI1M0REMAP] = 0x00000110;
|
|
|
|
s->regs[GT_PCI1M1REMAP] = 0x00000120;
|
|
|
|
|
|
|
|
/* CPU Error Report */
|
|
|
|
s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
|
|
|
|
s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
|
|
|
|
s->regs[GT_CPUERR_DATALO] = 0xffffffff;
|
|
|
|
s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
|
|
|
|
s->regs[GT_CPUERR_PARITY] = 0x000000ff;
|
|
|
|
|
2007-06-07 20:09:57 +02:00
|
|
|
/* CPU Sync Barrier */
|
|
|
|
s->regs[GT_PCI0SYNC] = 0x00000000;
|
|
|
|
s->regs[GT_PCI1SYNC] = 0x00000000;
|
|
|
|
|
|
|
|
/* SDRAM and Device Address Decode */
|
|
|
|
s->regs[GT_SCS0LD] = 0x00000000;
|
|
|
|
s->regs[GT_SCS0HD] = 0x00000007;
|
|
|
|
s->regs[GT_SCS1LD] = 0x00000008;
|
|
|
|
s->regs[GT_SCS1HD] = 0x0000000f;
|
|
|
|
s->regs[GT_SCS2LD] = 0x00000010;
|
|
|
|
s->regs[GT_SCS2HD] = 0x00000017;
|
|
|
|
s->regs[GT_SCS3LD] = 0x00000018;
|
|
|
|
s->regs[GT_SCS3HD] = 0x0000001f;
|
|
|
|
s->regs[GT_CS0LD] = 0x000000c0;
|
|
|
|
s->regs[GT_CS0HD] = 0x000000c7;
|
|
|
|
s->regs[GT_CS1LD] = 0x000000c8;
|
|
|
|
s->regs[GT_CS1HD] = 0x000000cf;
|
|
|
|
s->regs[GT_CS2LD] = 0x000000d0;
|
|
|
|
s->regs[GT_CS2HD] = 0x000000df;
|
|
|
|
s->regs[GT_CS3LD] = 0x000000f0;
|
|
|
|
s->regs[GT_CS3HD] = 0x000000fb;
|
|
|
|
s->regs[GT_BOOTLD] = 0x000000fc;
|
|
|
|
s->regs[GT_BOOTHD] = 0x000000ff;
|
|
|
|
s->regs[GT_ADERR] = 0xffffffff;
|
|
|
|
|
|
|
|
/* SDRAM Configuration */
|
|
|
|
s->regs[GT_SDRAM_CFG] = 0x00000200;
|
|
|
|
s->regs[GT_SDRAM_OPMODE] = 0x00000000;
|
|
|
|
s->regs[GT_SDRAM_BM] = 0x00000007;
|
|
|
|
s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
|
|
|
|
|
|
|
|
/* SDRAM Parameters */
|
|
|
|
s->regs[GT_SDRAM_B0] = 0x00000005;
|
|
|
|
s->regs[GT_SDRAM_B1] = 0x00000005;
|
|
|
|
s->regs[GT_SDRAM_B2] = 0x00000005;
|
|
|
|
s->regs[GT_SDRAM_B3] = 0x00000005;
|
|
|
|
|
2007-01-15 19:32:02 +01:00
|
|
|
/* ECC */
|
|
|
|
s->regs[GT_ECC_ERRDATALO] = 0x00000000;
|
|
|
|
s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
|
|
|
|
s->regs[GT_ECC_MEM] = 0x00000000;
|
|
|
|
s->regs[GT_ECC_CALC] = 0x00000000;
|
|
|
|
s->regs[GT_ECC_ERRADDR] = 0x00000000;
|
|
|
|
|
2007-06-07 20:09:57 +02:00
|
|
|
/* Device Parameters */
|
|
|
|
s->regs[GT_DEV_B0] = 0x386fffff;
|
|
|
|
s->regs[GT_DEV_B1] = 0x386fffff;
|
|
|
|
s->regs[GT_DEV_B2] = 0x386fffff;
|
|
|
|
s->regs[GT_DEV_B3] = 0x386fffff;
|
|
|
|
s->regs[GT_DEV_BOOT] = 0x146fffff;
|
2007-01-18 00:35:01 +01:00
|
|
|
|
2007-06-07 20:09:57 +02:00
|
|
|
/* DMA registers are all zeroed at reset */
|
|
|
|
|
|
|
|
/* Timer/Counter */
|
|
|
|
s->regs[GT_TC0] = 0xffffffff;
|
|
|
|
s->regs[GT_TC1] = 0x00ffffff;
|
|
|
|
s->regs[GT_TC2] = 0x00ffffff;
|
|
|
|
s->regs[GT_TC3] = 0x00ffffff;
|
|
|
|
s->regs[GT_TC_CONTROL] = 0x00000000;
|
|
|
|
|
|
|
|
/* PCI Internal */
|
2007-01-15 19:32:02 +01:00
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
|
|
s->regs[GT_PCI0_CMD] = 0x00000000;
|
|
|
|
#else
|
|
|
|
s->regs[GT_PCI0_CMD] = 0x00010001;
|
|
|
|
#endif
|
2007-06-07 20:09:57 +02:00
|
|
|
s->regs[GT_PCI0_TOR] = 0x0000070f;
|
|
|
|
s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
|
|
|
|
s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
|
|
|
|
s->regs[GT_PCI0_BS_CS20] = 0x01fff000;
|
|
|
|
s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
|
2007-01-15 19:32:02 +01:00
|
|
|
s->regs[GT_PCI1_IACK] = 0x00000000;
|
2007-06-07 20:09:57 +02:00
|
|
|
s->regs[GT_PCI0_IACK] = 0x00000000;
|
|
|
|
s->regs[GT_PCI0_BARE] = 0x0000000f;
|
|
|
|
s->regs[GT_PCI0_PREFMBR] = 0x00000040;
|
|
|
|
s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
|
|
|
|
s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
|
|
|
|
s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
|
|
|
|
s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
|
|
|
|
s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
|
|
|
|
s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
|
|
|
|
s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
|
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
|
|
s->regs[GT_PCI1_CMD] = 0x00000000;
|
|
|
|
#else
|
|
|
|
s->regs[GT_PCI1_CMD] = 0x00010001;
|
|
|
|
#endif
|
|
|
|
s->regs[GT_PCI1_TOR] = 0x0000070f;
|
|
|
|
s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
|
|
|
|
s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
|
|
|
|
s->regs[GT_PCI1_BS_CS20] = 0x01fff000;
|
|
|
|
s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
|
|
|
|
s->regs[GT_PCI1_BARE] = 0x0000000f;
|
|
|
|
s->regs[GT_PCI1_PREFMBR] = 0x00000040;
|
|
|
|
s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
|
|
|
|
s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
|
|
|
|
s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
|
|
|
|
s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
|
|
|
|
s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
|
|
|
|
s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
|
|
|
|
s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
|
|
|
|
s->regs[GT_PCI1_CFGADDR] = 0x00000000;
|
|
|
|
s->regs[GT_PCI1_CFGDATA] = 0x00000000;
|
|
|
|
s->regs[GT_PCI0_CFGADDR] = 0x00000000;
|
|
|
|
|
|
|
|
/* Interrupt registers are all zeroed at reset */
|
2007-01-15 19:32:02 +01:00
|
|
|
|
2007-07-11 18:44:32 +02:00
|
|
|
gt64120_isd_mapping(s);
|
2007-06-12 23:06:52 +02:00
|
|
|
gt64120_pci_mapping(s);
|
2007-01-15 19:32:02 +01:00
|
|
|
}
|
|
|
|
|
2021-03-02 23:39:06 +01:00
|
|
|
static void gt64120_realize(DeviceState *dev, Error **errp)
|
|
|
|
{
|
|
|
|
GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
|
|
|
|
|
|
|
|
memory_region_init_io(&s->ISD_mem, OBJECT(dev), &isd_mem_ops, s,
|
|
|
|
"gt64120-isd", 0x1000);
|
|
|
|
}
|
|
|
|
|
2011-01-19 23:10:40 +01:00
|
|
|
PCIBus *gt64120_register(qemu_irq *pic)
|
|
|
|
{
|
|
|
|
GT64120State *d;
|
2012-08-20 19:08:01 +02:00
|
|
|
PCIHostState *phb;
|
2011-01-19 23:10:40 +01:00
|
|
|
DeviceState *dev;
|
|
|
|
|
qdev: Convert uses of qdev_create() with Coccinelle
This is the transformation explained in the commit before previous.
Takes care of just one pattern that needs conversion. More to come in
this series.
Coccinelle script:
@ depends on !(file in "hw/arm/highbank.c")@
expression bus, type_name, dev, expr;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr;
identifier DOWN;
@@
- dev = DOWN(qdev_create(bus, type_name));
+ dev = DOWN(qdev_new(type_name));
... when != dev = expr
- qdev_init_nofail(DEVICE(dev));
+ qdev_realize_and_unref(DEVICE(dev), bus, &error_fatal);
@@
expression bus, type_name, expr;
identifier dev;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr, errp;
symbol true;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
@@
expression bus, type_name, expr, errp;
identifier dev;
symbol true;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
The first rule exempts hw/arm/highbank.c, because it matches along two
control flow paths there, with different @type_name. Covered by the
next commit's manual conversions.
Missing #include "qapi/error.h" added manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-10-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 07:31:58 +02:00
|
|
|
dev = qdev_new(TYPE_GT64120_PCI_HOST_BRIDGE);
|
2012-08-20 19:08:01 +02:00
|
|
|
d = GT64120_PCI_HOST_BRIDGE(dev);
|
2012-08-20 19:08:08 +02:00
|
|
|
phb = PCI_HOST_BRIDGE(dev);
|
2019-06-25 00:28:41 +02:00
|
|
|
memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB);
|
2015-02-01 09:12:55 +01:00
|
|
|
address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem");
|
2017-11-29 09:46:22 +01:00
|
|
|
phb->bus = pci_register_root_bus(dev, "pci",
|
|
|
|
gt64120_pci_set_irq, gt64120_pci_map_irq,
|
|
|
|
pic,
|
|
|
|
&d->pci0_mem,
|
|
|
|
get_system_io(),
|
|
|
|
PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS);
|
sysbus: Convert to sysbus_realize() etc. with Coccinelle
Convert from qdev_realize(), qdev_realize_and_unref() with null @bus
argument to sysbus_realize(), sysbus_realize_and_unref().
Coccinelle script:
@@
expression dev, errp;
@@
- qdev_realize(DEVICE(dev), NULL, errp);
+ sysbus_realize(SYS_BUS_DEVICE(dev), errp);
@@
expression sysbus_dev, dev, errp;
@@
+ sysbus_dev = SYS_BUS_DEVICE(dev);
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
- sysbus_dev = SYS_BUS_DEVICE(dev);
@@
expression sysbus_dev, dev, errp;
expression expr;
@@
sysbus_dev = SYS_BUS_DEVICE(dev);
... when != dev = expr;
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(DEVICE(dev), NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
Whitespace changes minimized manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-46-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 07:32:34 +02:00
|
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
2011-01-19 23:10:40 +01:00
|
|
|
|
2012-08-20 19:08:01 +02:00
|
|
|
pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
|
|
|
|
return phb->bus;
|
2011-01-19 23:10:40 +01:00
|
|
|
}
|
|
|
|
|
2015-12-18 12:03:51 +01:00
|
|
|
static void gt64120_pci_realize(PCIDevice *d, Error **errp)
|
2011-01-19 23:10:40 +01:00
|
|
|
{
|
2007-06-07 19:38:50 +02:00
|
|
|
/* FIXME: Malta specific hw assumptions ahead */
|
2011-01-19 23:10:40 +01:00
|
|
|
pci_set_word(d->config + PCI_COMMAND, 0);
|
|
|
|
pci_set_word(d->config + PCI_STATUS,
|
|
|
|
PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
|
|
|
|
pci_config_set_prog_interface(d->config, 0);
|
|
|
|
pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
|
|
|
|
pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
|
|
|
|
pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
|
|
|
|
pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
|
|
|
|
pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
|
|
|
|
pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
|
|
|
|
pci_set_byte(d->config + 0x3d, 0x01);
|
|
|
|
}
|
2007-07-11 18:44:32 +02:00
|
|
|
|
2011-12-04 19:22:06 +01:00
|
|
|
static void gt64120_pci_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
pci-host: Consistently set cannot_instantiate_with_device_add_yet
Many PCI host bridges consist of a sysbus device and a PCI device.
You need both for the thing to work. Arguably, these bridges should
be modelled as a single, composite devices instead of pairs of
seemingly independent devices you can only use together, but we're not
there, yet.
Since the sysbus part can't be instantiated with device_add, yet,
permitting it with the PCI part is useless. We shouldn't offer
useless options to the user, so let's set
cannot_instantiate_with_device_add_yet for them.
It's already set for Bonito, Grackle, i440FX and Raven. Document why.
Set it for the others: dec-21154, e500-host-bridge, gt64120_pci, mch,
pbm-pci, ppc4xx-host-bridge, sh_pci_host, u3-agp, uni-north-agp,
uni-north-internal-pci, uni-north-pci, and versatile_pci_host.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-28 17:26:58 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2011-12-04 19:22:06 +01:00
|
|
|
|
2015-12-18 12:03:51 +01:00
|
|
|
k->realize = gt64120_pci_realize;
|
2011-12-04 19:22:06 +01:00
|
|
|
k->vendor_id = PCI_VENDOR_ID_MARVELL;
|
|
|
|
k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X;
|
|
|
|
k->revision = 0x10;
|
|
|
|
k->class_id = PCI_CLASS_BRIDGE_HOST;
|
pci-host: Consistently set cannot_instantiate_with_device_add_yet
Many PCI host bridges consist of a sysbus device and a PCI device.
You need both for the thing to work. Arguably, these bridges should
be modelled as a single, composite devices instead of pairs of
seemingly independent devices you can only use together, but we're not
there, yet.
Since the sysbus part can't be instantiated with device_add, yet,
permitting it with the PCI part is useless. We shouldn't offer
useless options to the user, so let's set
cannot_instantiate_with_device_add_yet for them.
It's already set for Bonito, Grackle, i440FX and Raven. Document why.
Set it for the others: dec-21154, e500-host-bridge, gt64120_pci, mch,
pbm-pci, ppc4xx-host-bridge, sh_pci_host, u3-agp, uni-north-agp,
uni-north-internal-pci, uni-north-pci, and versatile_pci_host.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-28 17:26:58 +01:00
|
|
|
/*
|
|
|
|
* PCI-facing part of the host bridge, not usable without the
|
|
|
|
* host-facing part, which can't be device_add'ed, yet.
|
|
|
|
*/
|
2017-05-03 22:35:44 +02:00
|
|
|
dc->user_creatable = false;
|
2011-12-04 19:22:06 +01:00
|
|
|
}
|
|
|
|
|
2012-08-20 19:07:56 +02:00
|
|
|
static const TypeInfo gt64120_pci_info = {
|
2011-12-08 04:34:16 +01:00
|
|
|
.name = "gt64120_pci",
|
|
|
|
.parent = TYPE_PCI_DEVICE,
|
|
|
|
.instance_size = sizeof(PCIDevice),
|
|
|
|
.class_init = gt64120_pci_class_init,
|
2017-09-27 21:56:34 +02:00
|
|
|
.interfaces = (InterfaceInfo[]) {
|
|
|
|
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
|
|
|
|
{ },
|
|
|
|
},
|
2011-01-19 23:10:40 +01:00
|
|
|
};
|
2007-06-07 19:31:35 +02:00
|
|
|
|
2012-01-24 20:12:29 +01:00
|
|
|
static void gt64120_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2014-06-20 15:59:58 +02:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-24 20:12:29 +01:00
|
|
|
|
2018-10-02 23:25:17 +02:00
|
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
2021-03-02 23:39:06 +01:00
|
|
|
dc->realize = gt64120_realize;
|
2018-10-02 23:25:16 +02:00
|
|
|
dc->reset = gt64120_reset;
|
2014-06-20 15:59:58 +02:00
|
|
|
dc->vmsd = &vmstate_gt64120;
|
2012-01-24 20:12:29 +01:00
|
|
|
}
|
|
|
|
|
2012-08-20 19:07:56 +02:00
|
|
|
static const TypeInfo gt64120_info = {
|
2012-08-20 19:08:01 +02:00
|
|
|
.name = TYPE_GT64120_PCI_HOST_BRIDGE,
|
2012-08-20 19:08:08 +02:00
|
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
2011-12-08 04:34:16 +01:00
|
|
|
.instance_size = sizeof(GT64120State),
|
|
|
|
.class_init = gt64120_class_init,
|
2012-01-24 20:12:29 +01:00
|
|
|
};
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
static void gt64120_pci_register_types(void)
|
2011-01-19 23:10:40 +01:00
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
type_register_static(>64120_info);
|
|
|
|
type_register_static(>64120_pci_info);
|
2007-01-15 19:32:02 +01:00
|
|
|
}
|
2011-01-19 23:10:40 +01:00
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
type_init(gt64120_pci_register_types)
|