2007-09-29 21:40:09 +02:00
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/*
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* SuperH Timer modules.
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*
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* Copyright (c) 2007 Magnus Damm
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* Based on arm_timer.c by Paul Brook
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* Copyright (c) 2005-2006 CodeSourcery.
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*
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2011-06-26 04:21:35 +02:00
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* This code is licensed under the GPL.
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2007-09-29 21:40:09 +02:00
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*/
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2016-01-26 19:17:18 +01:00
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#include "qemu/osdep.h"
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2020-05-04 10:16:52 +02:00
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#include "exec/memory.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/hw.h"
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2019-08-12 07:23:42 +02:00
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#include "hw/irq.h"
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2013-02-05 17:06:20 +01:00
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#include "hw/sh4/sh.h"
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2020-05-04 10:16:52 +02:00
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#include "hw/timer/tmu012.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/ptimer.h"
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2021-10-29 23:02:09 +02:00
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#include "trace.h"
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2007-09-29 21:40:09 +02:00
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#define TIMER_TCR_TPSC (7 << 0)
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#define TIMER_TCR_CKEG (3 << 3)
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#define TIMER_TCR_UNIE (1 << 5)
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#define TIMER_TCR_ICPE (3 << 6)
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#define TIMER_TCR_UNF (1 << 8)
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#define TIMER_TCR_ICPF (1 << 9)
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#define TIMER_TCR_RESERVED (0x3f << 10)
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#define TIMER_FEAT_CAPT (1 << 0)
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#define TIMER_FEAT_EXTCLK (1 << 1)
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2009-02-07 16:18:47 +01:00
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#define OFFSET_TCOR 0
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#define OFFSET_TCNT 1
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#define OFFSET_TCR 2
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#define OFFSET_TCPR 3
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2007-09-29 21:40:09 +02:00
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typedef struct {
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ptimer_state *timer;
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uint32_t tcnt;
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uint32_t tcor;
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uint32_t tcr;
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uint32_t tcpr;
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int freq;
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int int_level;
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2007-12-12 02:11:42 +01:00
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int old_level;
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2007-09-29 21:40:09 +02:00
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int feat;
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int enabled;
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2008-11-21 22:06:42 +01:00
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qemu_irq irq;
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2021-10-29 23:02:09 +02:00
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} SHTimerState;
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2007-09-29 21:40:09 +02:00
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/* Check all active timers, and schedule the next timer interrupt. */
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2021-10-29 23:02:09 +02:00
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static void sh_timer_update(SHTimerState *s)
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2007-09-29 21:40:09 +02:00
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{
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2007-12-12 02:11:42 +01:00
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int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);
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2021-10-29 23:02:09 +02:00
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if (new_level != s->old_level) {
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2021-10-29 23:02:09 +02:00
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qemu_set_irq(s->irq, new_level);
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2021-10-29 23:02:09 +02:00
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}
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2007-12-12 02:11:42 +01:00
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s->old_level = s->int_level;
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s->int_level = new_level;
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2007-09-29 21:40:09 +02:00
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}
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2012-10-23 12:30:10 +02:00
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static uint32_t sh_timer_read(void *opaque, hwaddr offset)
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2007-09-29 21:40:09 +02:00
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{
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2021-10-29 23:02:09 +02:00
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SHTimerState *s = opaque;
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2007-09-29 21:40:09 +02:00
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switch (offset >> 2) {
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2009-02-07 16:18:47 +01:00
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case OFFSET_TCOR:
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2007-09-29 21:40:09 +02:00
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return s->tcor;
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2009-02-07 16:18:47 +01:00
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case OFFSET_TCNT:
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2007-09-29 21:40:09 +02:00
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return ptimer_get_count(s->timer);
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2009-02-07 16:18:47 +01:00
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case OFFSET_TCR:
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2007-09-29 21:40:09 +02:00
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return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0);
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2009-02-07 16:18:47 +01:00
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case OFFSET_TCPR:
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2021-10-29 23:02:09 +02:00
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if (s->feat & TIMER_FEAT_CAPT) {
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2007-09-29 21:40:09 +02:00
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return s->tcpr;
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2021-10-29 23:02:09 +02:00
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}
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2018-08-01 17:14:09 +02:00
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/* fall through */
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2007-09-29 21:40:09 +02:00
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default:
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2009-05-08 03:35:15 +02:00
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hw_error("sh_timer_read: Bad offset %x\n", (int)offset);
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2007-09-29 21:40:09 +02:00
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return 0;
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}
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}
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2012-10-23 12:30:10 +02:00
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static void sh_timer_write(void *opaque, hwaddr offset,
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2007-09-29 21:40:09 +02:00
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uint32_t value)
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{
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2021-10-29 23:02:09 +02:00
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SHTimerState *s = opaque;
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2007-09-29 21:40:09 +02:00
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int freq;
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switch (offset >> 2) {
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2009-02-07 16:18:47 +01:00
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case OFFSET_TCOR:
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2007-09-29 21:40:09 +02:00
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s->tcor = value;
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2019-10-22 17:50:36 +02:00
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ptimer_transaction_begin(s->timer);
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2007-09-29 21:40:09 +02:00
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ptimer_set_limit(s->timer, s->tcor, 0);
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2019-10-22 17:50:36 +02:00
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ptimer_transaction_commit(s->timer);
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2007-09-29 21:40:09 +02:00
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break;
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2009-02-07 16:18:47 +01:00
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case OFFSET_TCNT:
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2007-09-29 21:40:09 +02:00
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s->tcnt = value;
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2019-10-22 17:50:36 +02:00
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ptimer_transaction_begin(s->timer);
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2007-09-29 21:40:09 +02:00
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ptimer_set_count(s->timer, s->tcnt);
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2019-10-22 17:50:36 +02:00
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ptimer_transaction_commit(s->timer);
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2007-09-29 21:40:09 +02:00
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break;
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2009-02-07 16:18:47 +01:00
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case OFFSET_TCR:
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2019-10-22 17:50:36 +02:00
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ptimer_transaction_begin(s->timer);
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2007-09-29 21:40:09 +02:00
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if (s->enabled) {
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2021-10-29 23:02:09 +02:00
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/*
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* Pause the timer if it is running. This may cause some inaccuracy
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2021-10-29 23:02:09 +02:00
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* due to rounding, but avoids a whole lot of other messiness
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2021-10-29 23:02:09 +02:00
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*/
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2007-09-29 21:40:09 +02:00
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ptimer_stop(s->timer);
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}
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freq = s->freq;
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/* ??? Need to recalculate expiry time after changing divisor. */
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switch (value & TIMER_TCR_TPSC) {
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2021-10-29 23:02:09 +02:00
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case 0:
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freq >>= 2;
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break;
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case 1:
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freq >>= 4;
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break;
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case 2:
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freq >>= 6;
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break;
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case 3:
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freq >>= 8;
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break;
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case 4:
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freq >>= 10;
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break;
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2020-10-20 17:39:33 +02:00
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case 6:
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case 7:
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if (s->feat & TIMER_FEAT_EXTCLK) {
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break;
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}
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2020-10-20 17:39:34 +02:00
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/* fallthrough */
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2020-10-20 17:39:33 +02:00
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default:
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hw_error("sh_timer_write: Reserved TPSC value\n");
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2007-09-29 21:40:09 +02:00
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}
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switch ((value & TIMER_TCR_CKEG) >> 3) {
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2020-10-20 17:39:33 +02:00
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case 0:
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break;
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2007-09-29 21:40:09 +02:00
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case 1:
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case 2:
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2020-10-20 17:39:33 +02:00
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case 3:
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if (s->feat & TIMER_FEAT_EXTCLK) {
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break;
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}
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2020-10-20 17:39:34 +02:00
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/* fallthrough */
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2020-10-20 17:39:33 +02:00
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default:
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hw_error("sh_timer_write: Reserved CKEG value\n");
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2007-09-29 21:40:09 +02:00
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}
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switch ((value & TIMER_TCR_ICPE) >> 6) {
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2020-10-20 17:39:33 +02:00
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case 0:
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break;
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2007-09-29 21:40:09 +02:00
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case 2:
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2020-10-20 17:39:33 +02:00
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case 3:
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if (s->feat & TIMER_FEAT_CAPT) {
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break;
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}
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2020-10-20 17:39:34 +02:00
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/* fallthrough */
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2020-10-20 17:39:33 +02:00
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default:
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hw_error("sh_timer_write: Reserved ICPE value\n");
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2007-09-29 21:40:09 +02:00
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}
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2020-10-20 17:39:33 +02:00
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if ((value & TIMER_TCR_UNF) == 0) {
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2007-09-29 21:40:09 +02:00
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s->int_level = 0;
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2020-10-20 17:39:33 +02:00
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}
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2007-09-29 21:40:09 +02:00
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2020-10-20 17:39:33 +02:00
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value &= ~TIMER_TCR_UNF;
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2007-09-29 21:40:09 +02:00
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2020-10-20 17:39:33 +02:00
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if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT))) {
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2009-05-08 03:35:15 +02:00
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hw_error("sh_timer_write: Reserved ICPF value\n");
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2020-10-20 17:39:33 +02:00
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}
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2007-09-29 21:40:09 +02:00
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2020-10-20 17:39:33 +02:00
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value &= ~TIMER_TCR_ICPF; /* capture not supported */
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2007-09-29 21:40:09 +02:00
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2020-10-20 17:39:33 +02:00
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if (value & TIMER_TCR_RESERVED) {
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2009-05-08 03:35:15 +02:00
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hw_error("sh_timer_write: Reserved TCR bits set\n");
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2020-10-20 17:39:33 +02:00
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}
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2007-09-29 21:40:09 +02:00
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s->tcr = value;
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ptimer_set_limit(s->timer, s->tcor, 0);
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ptimer_set_freq(s->timer, freq);
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if (s->enabled) {
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/* Restart the timer if still enabled. */
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ptimer_run(s->timer, 0);
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}
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2019-10-22 17:50:36 +02:00
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ptimer_transaction_commit(s->timer);
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2007-09-29 21:40:09 +02:00
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break;
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2009-02-07 16:18:47 +01:00
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case OFFSET_TCPR:
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2007-09-29 21:40:09 +02:00
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if (s->feat & TIMER_FEAT_CAPT) {
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s->tcpr = value;
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2020-10-20 17:39:33 +02:00
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break;
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}
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2020-10-20 17:39:34 +02:00
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/* fallthrough */
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2007-09-29 21:40:09 +02:00
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default:
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2009-05-08 03:35:15 +02:00
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hw_error("sh_timer_write: Bad offset %x\n", (int)offset);
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2007-09-29 21:40:09 +02:00
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}
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sh_timer_update(s);
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}
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static void sh_timer_start_stop(void *opaque, int enable)
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{
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2021-10-29 23:02:09 +02:00
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SHTimerState *s = opaque;
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2007-09-29 21:40:09 +02:00
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2021-10-29 23:02:09 +02:00
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trace_sh_timer_start_stop(enable, s->enabled);
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2019-10-22 17:50:36 +02:00
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ptimer_transaction_begin(s->timer);
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2007-09-29 21:40:09 +02:00
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if (s->enabled && !enable) {
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ptimer_stop(s->timer);
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}
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if (!s->enabled && enable) {
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ptimer_run(s->timer, 0);
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}
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2019-10-22 17:50:36 +02:00
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ptimer_transaction_commit(s->timer);
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2007-09-29 21:40:09 +02:00
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s->enabled = !!enable;
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}
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static void sh_timer_tick(void *opaque)
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{
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2021-10-29 23:02:09 +02:00
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SHTimerState *s = opaque;
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2007-09-29 21:40:09 +02:00
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s->int_level = s->enabled;
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sh_timer_update(s);
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}
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2008-11-21 22:06:42 +01:00
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static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
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2007-09-29 21:40:09 +02:00
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{
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2021-10-29 23:02:09 +02:00
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SHTimerState *s;
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2007-09-29 21:40:09 +02:00
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2021-10-29 23:02:09 +02:00
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s = g_malloc0(sizeof(*s));
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2007-09-29 21:40:09 +02:00
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s->freq = freq;
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s->feat = feat;
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s->tcor = 0xffffffff;
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s->tcnt = 0xffffffff;
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s->tcpr = 0xdeadbeef;
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2009-02-07 16:18:47 +01:00
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s->tcr = 0;
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2007-09-29 21:40:09 +02:00
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s->enabled = 0;
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2007-12-12 02:11:42 +01:00
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s->irq = irq;
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2007-09-29 21:40:09 +02:00
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2019-10-22 17:50:36 +02:00
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s->timer = ptimer_init(sh_timer_tick, s, PTIMER_POLICY_DEFAULT);
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2009-02-07 16:18:47 +01:00
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sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor);
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sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt);
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sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr);
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sh_timer_write(s, OFFSET_TCR >> 2, s->tcpr);
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2007-09-29 21:40:09 +02:00
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/* ??? Save/restore. */
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return s;
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}
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typedef struct {
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2011-11-17 14:23:00 +01:00
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MemoryRegion iomem;
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MemoryRegion iomem_p4;
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MemoryRegion iomem_a7;
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2007-09-29 21:40:09 +02:00
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void *timer[3];
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int level[3];
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uint32_t tocr;
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uint32_t tstr;
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int feat;
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} tmu012_state;
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2012-10-23 12:30:10 +02:00
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static uint64_t tmu012_read(void *opaque, hwaddr offset,
|
2011-11-17 14:23:00 +01:00
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unsigned size)
|
2007-09-29 21:40:09 +02:00
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{
|
2021-10-29 23:02:09 +02:00
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tmu012_state *s = opaque;
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2007-09-29 21:40:09 +02:00
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2021-10-29 23:02:09 +02:00
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trace_sh_timer_read(offset);
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2007-09-29 21:40:09 +02:00
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if (offset >= 0x20) {
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2020-10-20 17:39:33 +02:00
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if (!(s->feat & TMU012_FEAT_3CHAN)) {
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hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
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}
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2007-09-29 21:40:09 +02:00
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return sh_timer_read(s->timer[2], offset - 0x20);
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}
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2021-10-29 23:02:09 +02:00
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if (offset >= 0x14) {
|
2007-09-29 21:40:09 +02:00
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return sh_timer_read(s->timer[1], offset - 0x14);
|
2021-10-29 23:02:09 +02:00
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}
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|
|
if (offset >= 0x08) {
|
2007-09-29 21:40:09 +02:00
|
|
|
return sh_timer_read(s->timer[0], offset - 0x08);
|
2021-10-29 23:02:09 +02:00
|
|
|
}
|
|
|
|
if (offset == 4) {
|
2007-09-29 21:40:09 +02:00
|
|
|
return s->tstr;
|
2021-10-29 23:02:09 +02:00
|
|
|
}
|
|
|
|
if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) {
|
2007-09-29 21:40:09 +02:00
|
|
|
return s->tocr;
|
2021-10-29 23:02:09 +02:00
|
|
|
}
|
2007-09-29 21:40:09 +02:00
|
|
|
|
2009-05-08 03:35:15 +02:00
|
|
|
hw_error("tmu012_write: Bad offset %x\n", (int)offset);
|
2007-09-29 21:40:09 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void tmu012_write(void *opaque, hwaddr offset,
|
2011-11-17 14:23:00 +01:00
|
|
|
uint64_t value, unsigned size)
|
2007-09-29 21:40:09 +02:00
|
|
|
{
|
2021-10-29 23:02:09 +02:00
|
|
|
tmu012_state *s = opaque;
|
2007-09-29 21:40:09 +02:00
|
|
|
|
2021-10-29 23:02:09 +02:00
|
|
|
trace_sh_timer_write(offset, value);
|
2007-09-29 21:40:09 +02:00
|
|
|
if (offset >= 0x20) {
|
2020-10-20 17:39:33 +02:00
|
|
|
if (!(s->feat & TMU012_FEAT_3CHAN)) {
|
|
|
|
hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
|
|
|
|
}
|
2007-09-29 21:40:09 +02:00
|
|
|
sh_timer_write(s->timer[2], offset - 0x20, value);
|
2020-10-20 17:39:33 +02:00
|
|
|
return;
|
2007-09-29 21:40:09 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
if (offset >= 0x14) {
|
|
|
|
sh_timer_write(s->timer[1], offset - 0x14, value);
|
2020-10-20 17:39:33 +02:00
|
|
|
return;
|
2007-09-29 21:40:09 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
if (offset >= 0x08) {
|
|
|
|
sh_timer_write(s->timer[0], offset - 0x08, value);
|
2020-10-20 17:39:33 +02:00
|
|
|
return;
|
2007-09-29 21:40:09 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
if (offset == 4) {
|
|
|
|
sh_timer_start_stop(s->timer[0], value & (1 << 0));
|
|
|
|
sh_timer_start_stop(s->timer[1], value & (1 << 1));
|
2020-10-20 17:39:33 +02:00
|
|
|
if (s->feat & TMU012_FEAT_3CHAN) {
|
2007-09-29 21:40:09 +02:00
|
|
|
sh_timer_start_stop(s->timer[2], value & (1 << 2));
|
2020-10-20 17:39:33 +02:00
|
|
|
} else {
|
|
|
|
if (value & (1 << 2)) {
|
2009-05-08 03:35:15 +02:00
|
|
|
hw_error("tmu012_write: Bad channel\n");
|
2020-10-20 17:39:33 +02:00
|
|
|
}
|
|
|
|
}
|
2007-09-29 21:40:09 +02:00
|
|
|
|
2020-10-20 17:39:33 +02:00
|
|
|
s->tstr = value;
|
|
|
|
return;
|
2007-09-29 21:40:09 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) {
|
|
|
|
s->tocr = value & (1 << 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-11-17 14:23:00 +01:00
|
|
|
static const MemoryRegionOps tmu012_ops = {
|
|
|
|
.read = tmu012_read,
|
|
|
|
.write = tmu012_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2007-09-29 21:40:09 +02:00
|
|
|
};
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
void tmu012_init(MemoryRegion *sysmem, hwaddr base,
|
2011-11-17 14:23:00 +01:00
|
|
|
int feat, uint32_t freq,
|
2020-10-20 17:39:33 +02:00
|
|
|
qemu_irq ch0_irq, qemu_irq ch1_irq,
|
|
|
|
qemu_irq ch2_irq0, qemu_irq ch2_irq1)
|
2007-09-29 21:40:09 +02:00
|
|
|
{
|
|
|
|
tmu012_state *s;
|
|
|
|
int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
|
|
|
|
|
2021-10-29 23:02:09 +02:00
|
|
|
s = g_malloc0(sizeof(*s));
|
2007-09-29 21:40:09 +02:00
|
|
|
s->feat = feat;
|
2007-12-12 02:11:42 +01:00
|
|
|
s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
|
|
|
|
s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
|
2020-10-20 17:39:33 +02:00
|
|
|
if (feat & TMU012_FEAT_3CHAN) {
|
2007-12-12 02:11:42 +01:00
|
|
|
s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
|
2020-10-20 17:39:33 +02:00
|
|
|
ch2_irq0); /* ch2_irq1 not supported */
|
|
|
|
}
|
2011-11-17 14:23:00 +01:00
|
|
|
|
2013-06-06 11:41:28 +02:00
|
|
|
memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s,
|
2011-11-17 14:23:00 +01:00
|
|
|
"timer", 0x100000000ULL);
|
|
|
|
|
2013-06-06 11:41:28 +02:00
|
|
|
memory_region_init_alias(&s->iomem_p4, NULL, "timer-p4",
|
2011-11-17 14:23:00 +01:00
|
|
|
&s->iomem, 0, 0x1000);
|
|
|
|
memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
|
|
|
|
|
2013-06-06 11:41:28 +02:00
|
|
|
memory_region_init_alias(&s->iomem_a7, NULL, "timer-a7",
|
2011-11-17 14:23:00 +01:00
|
|
|
&s->iomem, 0, 0x1000);
|
|
|
|
memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
|
2007-09-29 21:40:09 +02:00
|
|
|
/* ??? Save/restore. */
|
|
|
|
}
|