2007-11-11 01:04:49 +01:00
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/*
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* ARMV7M System emulation.
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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2011-06-23 02:59:26 +02:00
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* This code is licensed under the GPL.
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2007-11-11 01:04:49 +01:00
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*/
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2015-12-07 17:23:45 +01:00
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#include "qemu/osdep.h"
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2017-02-20 16:35:57 +01:00
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#include "hw/arm/armv7m.h"
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include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 09:01:28 +01:00
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#include "qapi/error.h"
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2016-01-19 21:51:44 +01:00
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#include "qemu-common.h"
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#include "cpu.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/sysbus.h"
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2013-04-09 16:26:55 +02:00
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#include "hw/arm/arm.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/loader.h"
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2009-09-20 16:58:02 +02:00
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#include "elf.h"
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2013-07-29 18:36:59 +02:00
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#include "sysemu/qtest.h"
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#include "qemu/error-report.h"
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2017-02-20 16:35:59 +01:00
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#include "exec/address-spaces.h"
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2007-11-11 01:04:49 +01:00
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/* Bitbanded IO. Each word corresponds to a single bit. */
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2011-06-23 02:59:26 +02:00
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/* Get the byte address of the real memory for a bitband access. */
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2008-12-01 19:59:50 +01:00
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static inline uint32_t bitband_addr(void * opaque, uint32_t addr)
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2007-11-11 01:04:49 +01:00
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{
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uint32_t res;
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2008-12-01 19:59:50 +01:00
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res = *(uint32_t *)opaque;
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2007-11-11 01:04:49 +01:00
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res |= (addr & 0x1ffffff) >> 5;
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return res;
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}
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2012-10-23 12:30:10 +02:00
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static uint32_t bitband_readb(void *opaque, hwaddr offset)
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2007-11-11 01:04:49 +01:00
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{
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uint8_t v;
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2008-12-01 19:59:50 +01:00
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cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
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2007-11-11 01:04:49 +01:00
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return (v & (1 << ((offset >> 2) & 7))) != 0;
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}
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2012-10-23 12:30:10 +02:00
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static void bitband_writeb(void *opaque, hwaddr offset,
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2007-11-11 01:04:49 +01:00
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uint32_t value)
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{
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uint32_t addr;
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uint8_t mask;
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uint8_t v;
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2008-12-01 19:59:50 +01:00
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addr = bitband_addr(opaque, offset);
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2007-11-11 01:04:49 +01:00
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mask = (1 << ((offset >> 2) & 7));
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cpu_physical_memory_read(addr, &v, 1);
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if (value & 1)
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v |= mask;
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else
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v &= ~mask;
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cpu_physical_memory_write(addr, &v, 1);
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}
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2012-10-23 12:30:10 +02:00
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static uint32_t bitband_readw(void *opaque, hwaddr offset)
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2007-11-11 01:04:49 +01:00
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{
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uint32_t addr;
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uint16_t mask;
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uint16_t v;
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2008-12-01 19:59:50 +01:00
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addr = bitband_addr(opaque, offset) & ~1;
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2007-11-11 01:04:49 +01:00
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mask = (1 << ((offset >> 2) & 15));
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mask = tswap16(mask);
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2013-04-12 20:53:58 +02:00
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cpu_physical_memory_read(addr, &v, 2);
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2007-11-11 01:04:49 +01:00
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return (v & mask) != 0;
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}
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2012-10-23 12:30:10 +02:00
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static void bitband_writew(void *opaque, hwaddr offset,
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2007-11-11 01:04:49 +01:00
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uint32_t value)
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{
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uint32_t addr;
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uint16_t mask;
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uint16_t v;
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2008-12-01 19:59:50 +01:00
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addr = bitband_addr(opaque, offset) & ~1;
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2007-11-11 01:04:49 +01:00
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mask = (1 << ((offset >> 2) & 15));
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mask = tswap16(mask);
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2013-04-12 20:53:58 +02:00
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cpu_physical_memory_read(addr, &v, 2);
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2007-11-11 01:04:49 +01:00
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if (value & 1)
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v |= mask;
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else
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v &= ~mask;
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2013-04-12 20:53:58 +02:00
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cpu_physical_memory_write(addr, &v, 2);
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2007-11-11 01:04:49 +01:00
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}
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2012-10-23 12:30:10 +02:00
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static uint32_t bitband_readl(void *opaque, hwaddr offset)
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2007-11-11 01:04:49 +01:00
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{
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uint32_t addr;
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uint32_t mask;
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uint32_t v;
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2008-12-01 19:59:50 +01:00
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addr = bitband_addr(opaque, offset) & ~3;
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2007-11-11 01:04:49 +01:00
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mask = (1 << ((offset >> 2) & 31));
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mask = tswap32(mask);
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2013-04-12 20:53:58 +02:00
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cpu_physical_memory_read(addr, &v, 4);
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2007-11-11 01:04:49 +01:00
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return (v & mask) != 0;
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}
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2012-10-23 12:30:10 +02:00
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static void bitband_writel(void *opaque, hwaddr offset,
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2007-11-11 01:04:49 +01:00
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uint32_t value)
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{
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uint32_t addr;
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uint32_t mask;
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uint32_t v;
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2008-12-01 19:59:50 +01:00
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addr = bitband_addr(opaque, offset) & ~3;
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2007-11-11 01:04:49 +01:00
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mask = (1 << ((offset >> 2) & 31));
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mask = tswap32(mask);
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2013-04-12 20:53:58 +02:00
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cpu_physical_memory_read(addr, &v, 4);
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2007-11-11 01:04:49 +01:00
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if (value & 1)
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v |= mask;
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else
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v &= ~mask;
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2013-04-12 20:53:58 +02:00
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cpu_physical_memory_write(addr, &v, 4);
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2007-11-11 01:04:49 +01:00
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}
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2011-08-15 16:17:20 +02:00
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static const MemoryRegionOps bitband_ops = {
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.old_mmio = {
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.read = { bitband_readb, bitband_readw, bitband_readl, },
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.write = { bitband_writeb, bitband_writew, bitband_writel, },
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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2007-11-11 01:04:49 +01:00
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};
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2016-03-07 08:05:42 +01:00
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static void bitband_init(Object *obj)
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2007-11-11 01:04:49 +01:00
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{
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2016-03-07 08:05:42 +01:00
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BitBandState *s = BITBAND(obj);
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SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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2007-11-11 01:04:49 +01:00
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2016-03-07 08:05:42 +01:00
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memory_region_init_io(&s->iomem, obj, &bitband_ops, &s->base,
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2013-06-07 03:25:08 +02:00
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"bitband", 0x02000000);
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2011-11-27 10:38:10 +01:00
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sysbus_init_mmio(dev, &s->iomem);
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2009-06-03 16:16:49 +02:00
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}
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2007-11-11 01:04:49 +01:00
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/* Board init. */
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2010-04-05 20:34:51 +02:00
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2017-02-20 16:35:57 +01:00
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static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
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0x20000000, 0x40000000
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};
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static const hwaddr bitband_output_addr[ARMV7M_NUM_BITBANDS] = {
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0x22000000, 0x42000000
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};
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static void armv7m_instance_init(Object *obj)
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{
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ARMv7MState *s = ARMV7M(obj);
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int i;
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/* Can't init the cpu here, we don't yet know which model to use */
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2017-02-20 16:35:59 +01:00
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object_property_add_link(obj, "memory",
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TYPE_MEMORY_REGION,
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(Object **)&s->board_memory,
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qdev_prop_allow_set_link_before_realize,
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OBJ_PROP_LINK_UNREF_ON_RELEASE,
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&error_abort);
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memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);
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2017-02-20 16:35:57 +01:00
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object_initialize(&s->nvic, sizeof(s->nvic), "armv7m_nvic");
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qdev_set_parent_bus(DEVICE(&s->nvic), sysbus_get_default());
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object_property_add_alias(obj, "num-irq",
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OBJECT(&s->nvic), "num-irq", &error_abort);
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for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
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object_initialize(&s->bitband[i], sizeof(s->bitband[i]), TYPE_BITBAND);
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qdev_set_parent_bus(DEVICE(&s->bitband[i]), sysbus_get_default());
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}
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}
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static void armv7m_realize(DeviceState *dev, Error **errp)
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{
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ARMv7MState *s = ARMV7M(dev);
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Error *err = NULL;
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int i;
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char **cpustr;
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ObjectClass *oc;
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const char *typename;
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CPUClass *cc;
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2017-02-20 16:35:59 +01:00
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if (!s->board_memory) {
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error_setg(errp, "memory property was not set");
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return;
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}
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memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
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2017-02-20 16:35:57 +01:00
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cpustr = g_strsplit(s->cpu_model, ",", 2);
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oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
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if (!oc) {
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error_setg(errp, "Unknown CPU model %s", cpustr[0]);
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g_strfreev(cpustr);
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return;
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}
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cc = CPU_CLASS(oc);
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typename = object_class_get_name(oc);
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cc->parse_features(typename, cpustr[1], &err);
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g_strfreev(cpustr);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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s->cpu = ARM_CPU(object_new(typename));
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if (!s->cpu) {
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error_setg(errp, "Unknown CPU model %s", s->cpu_model);
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return;
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}
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2017-02-20 16:35:59 +01:00
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object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory",
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&error_abort);
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2017-02-20 16:35:57 +01:00
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object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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/* Note that we must realize the NVIC after the CPU */
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object_property_set_bool(OBJECT(&s->nvic), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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/* Alias the NVIC's input and output GPIOs as our own so the board
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* code can wire them up. (We do this in realize because the
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* NVIC doesn't create the input GPIO array until realize.)
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*/
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qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL);
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qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
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/* Wire the NVIC up to the CPU */
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->nvic), 0,
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qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
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s->cpu->env.nvic = &s->nvic;
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for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
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Object *obj = OBJECT(&s->bitband[i]);
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SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
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object_property_set_int(obj, bitband_input_addr[i], "base", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_bool(obj, true, "realized", &err);
|
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|
|
if (err != NULL) {
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|
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error_propagate(errp, err);
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return;
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}
|
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|
2017-02-20 16:35:59 +01:00
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memory_region_add_subregion(&s->container, bitband_output_addr[i],
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|
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sysbus_mmio_get_region(sbd, 0));
|
2017-02-20 16:35:57 +01:00
|
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}
|
|
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}
|
|
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static Property armv7m_properties[] = {
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|
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DEFINE_PROP_STRING("cpu-model", ARMv7MState, cpu_model),
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|
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DEFINE_PROP_END_OF_LIST(),
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};
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|
|
static void armv7m_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = armv7m_realize;
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dc->props = armv7m_properties;
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}
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|
static const TypeInfo armv7m_info = {
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|
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.name = TYPE_ARMV7M,
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|
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(ARMv7MState),
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|
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.instance_init = armv7m_instance_init,
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|
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.class_init = armv7m_class_init,
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|
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};
|
|
|
|
|
2010-04-05 20:34:51 +02:00
|
|
|
static void armv7m_reset(void *opaque)
|
|
|
|
{
|
2012-05-04 16:11:34 +02:00
|
|
|
ARMCPU *cpu = opaque;
|
|
|
|
|
|
|
|
cpu_reset(CPU(cpu));
|
2010-04-05 20:34:51 +02:00
|
|
|
}
|
|
|
|
|
2007-11-11 01:04:49 +01:00
|
|
|
/* Init CPU and memory for a v7-M based board.
|
2015-02-05 14:37:21 +01:00
|
|
|
mem_size is in bytes.
|
2017-02-20 16:35:58 +01:00
|
|
|
Returns the ARMv7M device. */
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2007-11-11 01:04:49 +01:00
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2015-11-03 14:49:41 +01:00
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DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
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2007-11-11 01:04:49 +01:00
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const char *kernel_filename, const char *cpu_model)
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{
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2017-02-20 16:35:58 +01:00
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DeviceState *armv7m;
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2007-11-11 01:04:49 +01:00
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2012-05-04 16:09:50 +02:00
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if (cpu_model == NULL) {
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2017-02-20 16:35:58 +01:00
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cpu_model = "cortex-m3";
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2012-05-04 16:09:50 +02:00
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}
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2017-02-20 16:35:58 +01:00
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armv7m = qdev_create(NULL, "armv7m");
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qdev_prop_set_uint32(armv7m, "num-irq", num_irq);
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qdev_prop_set_string(armv7m, "cpu-model", cpu_model);
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2017-02-20 16:35:59 +01:00
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object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),
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"memory", &error_abort);
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2017-02-20 16:35:58 +01:00
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/* This will exit with an error if the user passed us a bad cpu_model */
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qdev_init_nofail(armv7m);
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armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size);
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return armv7m;
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2017-02-20 16:35:55 +01:00
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}
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void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
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{
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int image_size;
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uint64_t entry;
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uint64_t lowaddr;
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int big_endian;
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2007-11-11 01:04:49 +01:00
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2009-09-20 16:58:02 +02:00
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#ifdef TARGET_WORDS_BIGENDIAN
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big_endian = 1;
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#else
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big_endian = 0;
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#endif
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2013-07-29 18:36:59 +02:00
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if (!kernel_filename && !qtest_enabled()) {
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2012-08-13 12:04:05 +02:00
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fprintf(stderr, "Guest image must be specified (using -kernel)\n");
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exit(1);
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}
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2013-07-29 18:36:59 +02:00
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if (kernel_filename) {
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image_size = load_elf(kernel_filename, NULL, NULL, &entry, &lowaddr,
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2016-03-04 12:30:21 +01:00
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NULL, big_endian, EM_ARM, 1, 0);
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2013-07-29 18:36:59 +02:00
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if (image_size < 0) {
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2015-02-05 14:37:21 +01:00
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image_size = load_image_targphys(kernel_filename, 0, mem_size);
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2013-07-29 18:36:59 +02:00
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lowaddr = 0;
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}
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if (image_size < 0) {
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error_report("Could not load kernel '%s'", kernel_filename);
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exit(1);
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}
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2007-11-11 01:04:49 +01:00
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}
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2017-02-20 16:35:55 +01:00
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/* CPU objects (unlike devices) are not automatically reset on system
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* reset, so we must always register a handler to do so. Unlike
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* A-profile CPUs, we don't need to do anything special in the
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* handler to arrange that it starts correctly.
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* This is arguably the wrong place to do this, but it matches the
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* way A-profile does it. Note that this means that every M profile
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* board must call this function!
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*/
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2012-05-04 16:11:34 +02:00
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qemu_register_reset(armv7m_reset, cpu);
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2007-11-11 01:04:49 +01:00
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}
|
2009-06-03 16:16:49 +02:00
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2012-01-24 20:12:29 +01:00
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static Property bitband_properties[] = {
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DEFINE_PROP_UINT32("base", BitBandState, base, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void bitband_class_init(ObjectClass *klass, void *data)
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{
|
2011-12-08 04:34:16 +01:00
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DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-24 20:12:29 +01:00
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|
2011-12-08 04:34:16 +01:00
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dc->props = bitband_properties;
|
2012-01-24 20:12:29 +01:00
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}
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|
2013-01-10 16:19:07 +01:00
|
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static const TypeInfo bitband_info = {
|
2013-07-24 00:46:43 +02:00
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.name = TYPE_BITBAND,
|
2011-12-08 04:34:16 +01:00
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.parent = TYPE_SYS_BUS_DEVICE,
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|
.instance_size = sizeof(BitBandState),
|
2016-03-07 08:05:42 +01:00
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|
.instance_init = bitband_init,
|
2011-12-08 04:34:16 +01:00
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|
.class_init = bitband_class_init,
|
2009-07-15 13:43:31 +02:00
|
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|
};
|
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|
2012-02-09 15:20:55 +01:00
|
|
|
static void armv7m_register_types(void)
|
2009-06-03 16:16:49 +02:00
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
type_register_static(&bitband_info);
|
2017-02-20 16:35:57 +01:00
|
|
|
type_register_static(&armv7m_info);
|
2009-06-03 16:16:49 +02:00
|
|
|
}
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
type_init(armv7m_register_types)
|