2011-03-07 23:32:34 +01:00
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/*
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* QEMU model of the Milkymist SD Card Controller.
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*
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* Copyright (c) 2010 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*
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* Specification available at:
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2016-06-20 18:08:41 +02:00
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* http://milkymist.walle.cc/socdoc/memcard.pdf
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2011-03-07 23:32:34 +01:00
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*/
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2016-01-26 19:16:57 +01:00
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#include "qemu/osdep.h"
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2018-02-22 16:12:51 +01:00
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#include "qemu/log.h"
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2019-05-23 16:35:07 +02:00
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#include "qemu/module.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/sysbus.h"
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2019-08-12 07:23:45 +02:00
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#include "migration/vmstate.h"
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2011-03-07 23:32:34 +01:00
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#include "trace.h"
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2018-05-03 21:50:46 +02:00
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#include "qapi/error.h"
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2014-10-07 13:59:13 +02:00
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#include "sysemu/block-backend.h"
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2012-12-17 18:20:04 +01:00
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#include "sysemu/blockdev.h"
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2019-08-12 07:23:51 +02:00
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#include "hw/qdev-properties.h"
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2015-10-08 15:21:01 +02:00
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#include "hw/sd/sd.h"
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2011-03-07 23:32:34 +01:00
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enum {
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ENABLE_CMD_TX = (1<<0),
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ENABLE_CMD_RX = (1<<1),
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ENABLE_DAT_TX = (1<<2),
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ENABLE_DAT_RX = (1<<3),
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};
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enum {
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PENDING_CMD_TX = (1<<0),
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PENDING_CMD_RX = (1<<1),
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PENDING_DAT_TX = (1<<2),
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PENDING_DAT_RX = (1<<3),
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};
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enum {
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START_CMD_TX = (1<<0),
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START_DAT_RX = (1<<1),
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};
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enum {
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R_CLK2XDIV = 0,
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R_ENABLE,
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R_PENDING,
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R_START,
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R_CMD,
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R_DAT,
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R_MAX
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};
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2013-07-27 13:18:50 +02:00
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#define TYPE_MILKYMIST_MEMCARD "milkymist-memcard"
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#define MILKYMIST_MEMCARD(obj) \
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OBJECT_CHECK(MilkymistMemcardState, (obj), TYPE_MILKYMIST_MEMCARD)
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2020-07-05 23:03:34 +02:00
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#define TYPE_MILKYMIST_SDBUS "milkymist-sdbus"
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2011-03-07 23:32:34 +01:00
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struct MilkymistMemcardState {
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2013-07-27 13:18:50 +02:00
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SysBusDevice parent_obj;
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2011-08-31 16:48:41 +02:00
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MemoryRegion regs_region;
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2018-02-22 16:12:52 +01:00
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SDBus sdbus;
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2011-03-07 23:32:34 +01:00
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int command_write_ptr;
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int response_read_ptr;
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int response_len;
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int ignore_next_cmd;
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int enabled;
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uint8_t command[6];
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uint8_t response[17];
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uint32_t regs[R_MAX];
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};
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typedef struct MilkymistMemcardState MilkymistMemcardState;
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static void update_pending_bits(MilkymistMemcardState *s)
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{
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/* transmits are instantaneous, thus tx pending bits are never set */
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s->regs[R_PENDING] = 0;
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/* if rx is enabled the corresponding pending bits are always set */
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if (s->regs[R_ENABLE] & ENABLE_CMD_RX) {
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s->regs[R_PENDING] |= PENDING_CMD_RX;
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}
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if (s->regs[R_ENABLE] & ENABLE_DAT_RX) {
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s->regs[R_PENDING] |= PENDING_DAT_RX;
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}
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}
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static void memcard_sd_command(MilkymistMemcardState *s)
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{
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SDRequest req;
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req.cmd = s->command[0] & 0x3f;
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2018-06-29 16:11:20 +02:00
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req.arg = ldl_be_p(s->command + 1);
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2011-03-07 23:32:34 +01:00
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req.crc = s->command[5];
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s->response[0] = req.cmd;
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2018-02-22 16:12:52 +01:00
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s->response_len = sdbus_do_command(&s->sdbus, &req, s->response + 1);
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2011-03-07 23:32:34 +01:00
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s->response_read_ptr = 0;
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if (s->response_len == 16) {
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/* R2 response */
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s->response[0] = 0x3f;
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s->response_len += 1;
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} else if (s->response_len == 4) {
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/* no crc calculation, insert dummy byte */
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s->response[5] = 0;
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s->response_len += 2;
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}
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if (req.cmd == 0) {
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/* next write is a dummy byte to clock the initialization of the sd
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* card */
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s->ignore_next_cmd = 1;
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}
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}
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2012-10-23 12:30:10 +02:00
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static uint64_t memcard_read(void *opaque, hwaddr addr,
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2011-08-31 16:48:41 +02:00
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unsigned size)
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2011-03-07 23:32:34 +01:00
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{
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MilkymistMemcardState *s = opaque;
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uint32_t r = 0;
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addr >>= 2;
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switch (addr) {
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case R_CMD:
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if (!s->enabled) {
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r = 0xff;
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} else {
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r = s->response[s->response_read_ptr++];
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if (s->response_read_ptr > s->response_len) {
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2018-02-22 16:12:51 +01:00
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qemu_log_mask(LOG_GUEST_ERROR, "milkymist_memcard: "
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2018-06-08 14:15:33 +02:00
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"read more cmd bytes than available: clipping\n");
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2011-03-07 23:32:34 +01:00
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s->response_read_ptr = 0;
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}
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}
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break;
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case R_DAT:
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if (!s->enabled) {
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r = 0xffffffff;
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} else {
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r = 0;
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2020-08-14 11:23:42 +02:00
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r |= sdbus_read_byte(&s->sdbus) << 24;
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r |= sdbus_read_byte(&s->sdbus) << 16;
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r |= sdbus_read_byte(&s->sdbus) << 8;
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r |= sdbus_read_byte(&s->sdbus);
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2011-03-07 23:32:34 +01:00
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}
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break;
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case R_CLK2XDIV:
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case R_ENABLE:
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case R_PENDING:
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case R_START:
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r = s->regs[addr];
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break;
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default:
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2018-02-22 16:12:51 +01:00
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qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
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"read access to unknown register 0x%" HWADDR_PRIx "\n",
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addr << 2);
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2011-03-07 23:32:34 +01:00
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break;
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}
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trace_milkymist_memcard_memory_read(addr << 2, r);
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return r;
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}
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2012-10-23 12:30:10 +02:00
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static void memcard_write(void *opaque, hwaddr addr, uint64_t value,
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2011-08-31 16:48:41 +02:00
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unsigned size)
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2011-03-07 23:32:34 +01:00
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{
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MilkymistMemcardState *s = opaque;
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2020-08-14 11:23:44 +02:00
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uint32_t val32;
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2011-03-07 23:32:34 +01:00
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trace_milkymist_memcard_memory_write(addr, value);
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addr >>= 2;
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switch (addr) {
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case R_PENDING:
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/* clear rx pending bits */
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s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX | PENDING_DAT_RX));
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update_pending_bits(s);
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break;
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case R_CMD:
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if (!s->enabled) {
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break;
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}
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if (s->ignore_next_cmd) {
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s->ignore_next_cmd = 0;
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break;
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}
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s->command[s->command_write_ptr] = value & 0xff;
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s->command_write_ptr = (s->command_write_ptr + 1) % 6;
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if (s->command_write_ptr == 0) {
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memcard_sd_command(s);
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}
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break;
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case R_DAT:
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if (!s->enabled) {
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break;
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}
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2020-08-14 11:23:44 +02:00
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val32 = cpu_to_be32(value);
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sdbus_write_data(&s->sdbus, &val32, sizeof(val32));
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2011-03-07 23:32:34 +01:00
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break;
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case R_ENABLE:
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s->regs[addr] = value;
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update_pending_bits(s);
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break;
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case R_CLK2XDIV:
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case R_START:
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s->regs[addr] = value;
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break;
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default:
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2018-02-22 16:12:51 +01:00
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qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
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"write access to unknown register 0x%" HWADDR_PRIx " "
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"(value 0x%" PRIx64 ")\n", addr << 2, value);
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2011-03-07 23:32:34 +01:00
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break;
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}
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}
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2011-08-31 16:48:41 +02:00
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static const MemoryRegionOps memcard_mmio_ops = {
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.read = memcard_read,
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.write = memcard_write,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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2011-03-07 23:32:34 +01:00
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};
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static void milkymist_memcard_reset(DeviceState *d)
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{
|
2013-07-27 13:18:50 +02:00
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MilkymistMemcardState *s = MILKYMIST_MEMCARD(d);
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2011-03-07 23:32:34 +01:00
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int i;
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s->command_write_ptr = 0;
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s->response_read_ptr = 0;
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s->response_len = 0;
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for (i = 0; i < R_MAX; i++) {
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s->regs[i] = 0;
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}
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}
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2020-07-05 23:03:34 +02:00
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static void milkymist_memcard_set_readonly(DeviceState *dev, bool level)
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{
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qemu_log_mask(LOG_UNIMP,
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"milkymist_memcard: read-only mode not supported\n");
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}
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static void milkymist_memcard_set_inserted(DeviceState *dev, bool level)
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{
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MilkymistMemcardState *s = MILKYMIST_MEMCARD(dev);
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s->enabled = !!level;
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}
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2018-02-22 16:12:51 +01:00
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static void milkymist_memcard_init(Object *obj)
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{
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MilkymistMemcardState *s = MILKYMIST_MEMCARD(obj);
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SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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memory_region_init_io(&s->regs_region, OBJECT(s), &memcard_mmio_ops, s,
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"milkymist-memcard", R_MAX * 4);
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sysbus_init_mmio(dev, &s->regs_region);
|
2020-07-05 22:56:07 +02:00
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qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS,
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DEVICE(obj), "sd-bus");
|
2018-02-22 16:12:51 +01:00
|
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}
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|
2011-03-07 23:32:34 +01:00
|
|
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static const VMStateDescription vmstate_milkymist_memcard = {
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|
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.name = "milkymist-memcard",
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|
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.version_id = 1,
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|
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.minimum_version_id = 1,
|
2014-04-16 16:01:33 +02:00
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|
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.fields = (VMStateField[]) {
|
2011-03-07 23:32:34 +01:00
|
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VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
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VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
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VMSTATE_INT32(response_len, MilkymistMemcardState),
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VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
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|
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VMSTATE_INT32(enabled, MilkymistMemcardState),
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VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
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VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
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|
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VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
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|
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VMSTATE_END_OF_LIST()
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}
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};
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|
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|
|
2012-01-24 20:12:29 +01:00
|
|
|
static void milkymist_memcard_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-24 20:12:29 +01:00
|
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|
2011-12-08 04:34:16 +01:00
|
|
|
dc->reset = milkymist_memcard_reset;
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|
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dc->vmsd = &vmstate_milkymist_memcard;
|
2020-07-05 23:03:34 +02:00
|
|
|
/* Reason: output IRQs should be wired up */
|
2017-05-03 22:35:44 +02:00
|
|
|
dc->user_creatable = false;
|
2012-01-24 20:12:29 +01:00
|
|
|
}
|
|
|
|
|
2013-01-10 16:19:07 +01:00
|
|
|
static const TypeInfo milkymist_memcard_info = {
|
2013-07-27 13:18:50 +02:00
|
|
|
.name = TYPE_MILKYMIST_MEMCARD,
|
2011-12-08 04:34:16 +01:00
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
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|
|
|
.instance_size = sizeof(MilkymistMemcardState),
|
2018-02-22 16:12:51 +01:00
|
|
|
.instance_init = milkymist_memcard_init,
|
2011-12-08 04:34:16 +01:00
|
|
|
.class_init = milkymist_memcard_class_init,
|
2011-03-07 23:32:34 +01:00
|
|
|
};
|
|
|
|
|
2020-07-05 23:03:34 +02:00
|
|
|
static void milkymist_sdbus_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
SDBusClass *sbc = SD_BUS_CLASS(klass);
|
|
|
|
|
|
|
|
sbc->set_inserted = milkymist_memcard_set_inserted;
|
|
|
|
sbc->set_readonly = milkymist_memcard_set_readonly;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo milkymist_sdbus_info = {
|
|
|
|
.name = TYPE_MILKYMIST_SDBUS,
|
|
|
|
.parent = TYPE_SD_BUS,
|
|
|
|
.instance_size = sizeof(SDBus),
|
|
|
|
.class_init = milkymist_sdbus_class_init,
|
|
|
|
};
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
static void milkymist_memcard_register_types(void)
|
2011-03-07 23:32:34 +01:00
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
type_register_static(&milkymist_memcard_info);
|
2020-07-05 23:03:34 +02:00
|
|
|
type_register_static(&milkymist_sdbus_info);
|
2011-03-07 23:32:34 +01:00
|
|
|
}
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
type_init(milkymist_memcard_register_types)
|