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qemu-patch-raspberry4/default-configs/arm-softmmu.mak

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Add new config-devices.mak for each target We generate config-devices.h from there automatically. We need to do it in main Makefile, because we are going to need a main Makefile for them. Patchworks-ID: 35196 Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-07 02:41:02 +02:00
# Default configuration for arm-softmmu
Generate gdbstub-xml.c only when needed First user of new config-devices.mak Patchworks-ID: 35198 Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-07 02:41:04 +02:00
hw/arm: Express dependencies of the exynos machines with Kconfig Add Kconfig dependencies for the Exynos-related boards (nuri and smdkc210). This patch is slightly based on earlier work by Ákos Kovács (i.e. his "hw/arm/Kconfig: Add ARM Kconfig" patch). Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-02-07 10:28:01 +01:00
# TODO: ARM_V7M is currently always required - make this more flexible!
CONFIG_ARM_V7M=y
hw/arm: Express dependencies of realview, versatile and vexpress with Kconfig This patch is slightly based on earlier work by Ákos Kovács (i.e. his "hw/arm/Kconfig: Add ARM Kconfig" patch). Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-02-07 20:05:05 +01:00
# CONFIG_PCI_DEVICES=n
# CONFIG_TEST_DEVICES=n
hw/arm: Express dependencies of the exynos machines with Kconfig Add Kconfig dependencies for the Exynos-related boards (nuri and smdkc210). This patch is slightly based on earlier work by Ákos Kovács (i.e. his "hw/arm/Kconfig: Add ARM Kconfig" patch). Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-02-07 10:28:01 +01:00
CONFIG_EXYNOS4=y
hw/arm: Express dependencies of the highbank machines with Kconfig Add Kconfig dependencies for the highbank machine (and the midway machine). This patch is slightly based on earlier work by Ákos Kovács (i.e. his "hw/arm/Kconfig: Add ARM Kconfig" patch). Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-02-07 10:35:22 +01:00
CONFIG_HIGHBANK=y
hw/arm: Express dependencies of integratorcp with Kconfig This patch is slightly based on earlier work by Ákos Kovács (i.e. his "hw/arm/Kconfig: Add ARM Kconfig" patch). Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-02-07 15:21:27 +01:00
CONFIG_INTEGRATOR=y
hw/arm: Express dependencies of the fsl-imx31 machine with Kconfig Add Kconfig dependencies for the fsl-imx31 / kzm machine. This patch is slightly based on earlier work by Ákos Kovács (i.e. his "hw/arm/Kconfig: Add ARM Kconfig" patch). Reviewed-by: Peter Chubb <peter.chubb@data61.csiro.au> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-02-07 16:51:56 +01:00
CONFIG_FSL_IMX31=y
hw/arm: Express dependencies of musicpal with Kconfig This patch is slightly based on earlier work by Ákos Kovács (i.e. his "hw/arm/Kconfig: Add ARM Kconfig" patch). Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-02-07 17:05:38 +01:00
CONFIG_MUSICPAL=y
hw/arm: Express dependencies of the OMAP machines with Kconfig Add Kconfig dependencies for the OMAP machines (cheetah, n800, n810, sx1 and sx1-v1). This patch is slightly based on earlier work by Ákos Kovács (i.e. his "hw/arm/Kconfig: Add ARM Kconfig" patch). Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-02-07 17:12:14 +01:00
CONFIG_MUSCA=y
CONFIG_CHEETAH=y
CONFIG_SX1=y
CONFIG_NSERIES=y
hw/arm: Express dependencies of stellaris with Kconfig This patch is slightly based on earlier work by Ákos Kovács (i.e. his "hw/arm/Kconfig: Add ARM Kconfig" patch). Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-02-07 17:33:50 +01:00
CONFIG_STELLARIS=y
hw/arm: Express dependencies of realview, versatile and vexpress with Kconfig This patch is slightly based on earlier work by Ákos Kovács (i.e. his "hw/arm/Kconfig: Add ARM Kconfig" patch). Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-02-07 20:05:05 +01:00
CONFIG_REALVIEW=y
CONFIG_VERSATILE=y
CONFIG_VEXPRESS=y
hw/arm: Express dependencies of xilinx-zynq with Kconfig Add Kconfig dependencies for the xilinx-zynq-a9 board. This patch is based on earlier work by Ákos Kovács (i.e. his "hw/arm/Kconfig: Add ARM Kconfig" patch). Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-02-07 20:26:34 +01:00
CONFIG_ZYNQ=y
hw/arm: Express dependencies of the PXA2xx machines with Kconfig Add Kconfig dependencies for the PXA2xx machines (akita, borzoi, connex and verdex gumstix, tosa, mainstone, spitz, terrier and z2). This patch is based on earlier work by Ákos Kovács (i.e. his "hw/arm/Kconfig: Add ARM Kconfig" patch). Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-02-08 12:35:26 +01:00
CONFIG_MAINSTONE=y
CONFIG_GUMSTIX=y
CONFIG_SPITZ=y
CONFIG_TOSA=y
CONFIG_Z2=y
hw/arm: Express dependencies of collie with Kconfig Add Kconfig dependencies for the Strongarm collie machine. This patch is based on earlier work by Ákos Kovács (i.e. his "hw/arm/Kconfig: Add ARM Kconfig" patch). Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-02-08 06:39:48 +01:00
CONFIG_COLLIE=y
hw/arm: Express dependencies of the aspeed boards with Kconfig Dependencies have been determined by looking at hw/arm/aspeed.c Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-02-08 06:53:04 +01:00
CONFIG_ASPEED_SOC=y
hw/arm: Express dependencies of the exynos machines with Kconfig Add Kconfig dependencies for the Exynos-related boards (nuri and smdkc210). This patch is slightly based on earlier work by Ákos Kovács (i.e. his "hw/arm/Kconfig: Add ARM Kconfig" patch). Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-02-07 10:28:01 +01:00
vga: make Cirrus ISA device optional Reviewed-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01 18:33:43 +02:00
CONFIG_VGA=y
m25p80: Initial implementation of SPI flash device Added device model for m25p80 style SPI flash family. Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
2012-03-26 14:10:59 +02:00
CONFIG_SSI_M25P80=y
hw/net: add support for Allwinner EMAC Fast Ethernet controller This patch adds support for the Fast Ethernet MAC found on Allwinner SoCs, together with a basic emulation of Realtek RTL8201CP PHY. Since there is no public documentation of the Allwinner controller, the implementation is based on Linux kernel driver. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-30 23:02:06 +01:00
CONFIG_ALLWINNER_EMAC=y
i.MX: Add FEC Ethernet Emulator This is based on mcf_fec.c FEC implementation for Coldfire * A generic PHY was added (borrowwed from LAN9118) * The buffer management is also modified as buffers are slightly different between Coldfire and i.MX Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: fb314f8a120aa49f8f6ad886f312c649b484fb5a.1441057361.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 11:39:30 +02:00
CONFIG_IMX_FEC=y
Create specific config option for "platform-bus" Currently the "platform-bus" device is included for all softmmu builds. This bridge is intended for use on any platforms that require dynamic creation of sysbus devices. However, at present it is used only for the PPC E500 target, with plans for the ARM "virt" target in the immediate future. To avoid a not-very-useful entry appearing in "qemu -device ?" output on other targets, this patch makes a specific config option for platform-bus and enables it (for now) only on ppc configurations which include E500 and on ARM (which always includes the "virt" target). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <1425017077-18487-3-git-send-email-david@gibson.dropbear.id.au> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-02-27 07:04:36 +01:00
CONFIG_PLATFORM_BUS=y
hw: make virtio devices configurable via default-configs/ This is only half of the work, because the proxy devices (virtio-*-pci, virtio-*-ccw, etc.) are still included unconditionally. It is still a move in the right direction. Based-on: <20180522194943.24871-1-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-05-22 21:48:22 +02:00
CONFIG_VIRTIO_MMIO=y
arm: Move some ARM devices into libhw Avoids some unnecessary dependencies on cpu.h and prepares for a future armeb-softmmu where most machines would not be built. Defer touching the SoC devices since most have implicit or explicit dependencies on the CPU. Signed-off-by: Andreas Färber <andreas.faerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-08-13 04:11:12 +02:00
hw/arm: Use more CONFIG switches for the object files A lot of ARM object files are linked into the executable unconditionally, even though we have corresponding CONFIG switches like CONFIG_PXA2XX or CONFIG_OMAP. We should make sure to use these switches in the Makefile so that the users can disable certain unwanted boards and devices more easily. While we're at it, also add some new switches for the boards that do not have a CONFIG option yet. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 1520266949-29817-1-git-send-email-thuth@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-09 18:09:44 +01:00
CONFIG_NETDUINO2=y
armv7m: Don't put core v7M devices under CONFIG_STELLARIS The NVIC is a core v7M device that exists for all v7M CPUs; put it under a CONFIG_ARM_V7M rather than hiding it under CONFIG_STELLARIS. (We'll use CONFIG_ARM_V7M for the SysTick device too when we split it out of the NVIC.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-9-git-send-email-peter.maydell@linaro.org
2017-02-20 16:36:02 +01:00
hw: move display devices to hw/display/, configure via default-configs/ Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-02-05 12:59:04 +01:00
CONFIG_FRAMEBUFFER=y
hw: move timer devices to hw/timer/, configure with default-configs/ Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-02-05 14:38:25 +01:00
hw/arm: add very initial support for Canon DIGIC SoC DIGIC is Canon Inc.'s name for a family of SoC for digital cameras and camcorders. There is no publicly available specification for DIGIC chips. All information about DIGIC chip internals is based on reverse engineering efforts made by CHDK (http://chdk.wikia.com) and Magic Lantern (http://www.magiclantern.fm) projects contributors. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387188908-754-2-git-send-email-antonynpavlov@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17 20:42:36 +01:00
CONFIG_DIGIC=y
hw/arm/mps2: Implement skeleton mps2-an385 and mps2-an511 board models Model the ARM MPS2/MPS2+ FPGA based development board. The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger FPGA but is otherwise the same as the 2). Since the CPU itself and most of the devices are in the FPGA, the details of the board as seen by the guest depend significantly on the FPGA image. We model the following FPGA images: "mps2_an385" -- Cortex-M3 as documented in ARM Application Note AN385 "mps2_an511" -- Cortex-M3 'DesignStart' as documented in AN511 They are fairly similar but differ in the details for some peripherals. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1500029487-14822-2-git-send-email-peter.maydell@linaro.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-07-17 14:36:08 +02:00
CONFIG_MPS2=y
bcm2835_mbox: add BCM2835 mailboxes This adds the system mailboxes which are used to communicate with a number of GPU peripherals on Pi/Pi2. Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-29 23:50:37 +01:00
CONFIG_RASPI=y
stm32f2xx_timer: Add the stm32f2xx Timer This patch adds the stm32f2xx timers: TIM2, TIM3, TIM4 and TIM5 to QEMU. Signed-off-by: Alistair Francis <alistair@alistair23.me> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 155091a323390f8da3cca496e4c611c493e62a77.1424175342.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-11 14:21:05 +01:00
CONFIG_STM32F2XX_TIMER=y
stm32f2xx_USART: Add the stm32f2xx USART Controller This patch adds the stm32f2xx USART controller (UART also uses the same controller). Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 762c6c0d2a41d574932bc4445ec9bfffe6da8798.1424175342.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-11 14:21:05 +01:00
CONFIG_STM32F2XX_USART=y
stm32f2xx_SYSCFG: Add the stm32f2xx SYSCFG This patch adds the stm32f2xx System Configuration Controller. This is used to configure what memory is mapped at address 0 (although that is not supported) as well as configure how the EXTI interrupts work (also not supported at the moment). This device is not required for basic examples, but more complex systems will require it (as well as the EXTI device) Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 5d499d7b60b61d5d6dcb310b2e55411b1f53794e.1424175342.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-11 14:21:05 +01:00
CONFIG_STM32F2XX_SYSCFG=y
STM32F2xx: Add the ADC device Add the STM32F2xx ADC device. This device randomly generates values on each read. This also includes creating a hw/adc directory. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 3240e660adaf537f55a63ce06096e844aece8cda.1474742262.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04 14:28:07 +02:00
CONFIG_STM32F2XX_ADC=y
STM32F2xx: Add the SPI device Add the STM32F2xx SPI device. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 8197811d5c94f814fa67c6a33ca2f7fd0aa97432.1474742262.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04 14:28:07 +02:00
CONFIG_STM32F2XX_SPI=y
stm32f205: Add the stm32f205 SoC This patch adds the stm32f205 SoC. This will be used by the Netduino 2 to create a machine. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 48d509747a1ea0d8a7d5480560495e679990f9d2.1424175342.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-11 14:21:06 +01:00
CONFIG_STM32F205_SOC=y
arm: Add Nordic Semiconductor nRF51 SoC The nRF51 is a Cortex-M0 microcontroller with an on-board radio module, plus other common ARM SoC peripherals. http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf This defines a basic model of the CPU and memory, with no peripherals implemented at this stage. Signed-off-by: Joel Stanley <joel@jms.id.au> Message-id: 20180831220920.27113-3-joel@jms.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: wrapped a few long lines] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25 15:02:31 +02:00
CONFIG_NRF51_SOC=y
arm: Move some ARM devices into libhw Avoids some unnecessary dependencies on cpu.h and prepares for a future armeb-softmmu where most machines would not be built. Defer touching the SoC devices since most have implicit or explicit dependencies on the CPU. Signed-off-by: Andreas Färber <andreas.faerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-08-13 04:11:12 +02:00
hw/char/cmsdk-apb-timer: Implement CMSDK APB timer device Implement a model of the simple timer device found in the CMSDK. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1500029487-14822-5-git-send-email-peter.maydell@linaro.org
2017-07-17 14:36:08 +02:00
CONFIG_CMSDK_APB_TIMER=y
hw/timer/cmsdk-apb-dualtimer: Implement CMSDK dual timer module The Arm Cortex-M System Design Kit includes a "dual-input timer module" which combines two programmable down-counters. Implement a model of this device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180820141116.9118-4-peter.maydell@linaro.org
2018-08-24 14:17:41 +02:00
CONFIG_CMSDK_APB_DUALTIMER=y
hw/char/cmsdk-apb-uart.c: Implement CMSDK APB UART Implement a model of the simple "APB UART" provided in the Cortex-M System Design Kit (CMSDK). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1500029487-14822-3-git-send-email-peter.maydell@linaro.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-07-17 14:36:08 +02:00
CONFIG_CMSDK_APB_UART=y
hw/watchdog/cmsdk_apb_watchdog: Implement CMSDK APB watchdog module The Arm Cortex-M System Design Kit includes a simple watchdog module based on a 32-bit down-counter. Implement this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-20 12:24:33 +02:00
CONFIG_CMSDK_APB_WATCHDOG=y
hw/char/cmsdk-apb-uart.c: Implement CMSDK APB UART Implement a model of the simple "APB UART" provided in the Cortex-M System Design Kit (CMSDK). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1500029487-14822-3-git-send-email-peter.maydell@linaro.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-07-17 14:36:08 +02:00
hw/misc/mps2-fpgaio: FPGA control block for MPS2 AN505 The MPS2 AN505 FPGA image includes a "FPGA control block" which is a small set of registers handling LEDs, buttons and some counters. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-14-peter.maydell@linaro.org
2018-03-02 11:45:39 +01:00
CONFIG_MPS2_FPGAIO=y
hw/misc/mps2_scc: Implement MPS2 Serial Communication Controller Implement a model of the Serial Communication Controller (SCC) found in MPS2 FPGA images. The primary purpose of this device is to communicate with the Motherboard Configuration Controller (MCC) which is located on the MPS board itself, outside the FPGA image. This is used for programming the MPS clock generators. The SCC also has some basic ID registers and an output for the board LEDs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1500029487-14822-7-git-send-email-peter.maydell@linaro.org
2017-07-17 14:36:08 +02:00
CONFIG_MPS2_SCC=y
hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller Implement the Arm TrustZone Memory Protection Controller, which sits in front of RAM and allows secure software to configure it to either pass through or reject transactions. We implement the MPC as a QEMU IOMMU, which will direct transactions either through to the devices and memory behind it or to a special "never works" AddressSpace if they are blocked. This initial commit implements the skeleton of the device: * it always permits accesses * it doesn't implement most of the registers * it doesn't implement the interrupt or other behaviour for blocked transactions Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20180620132032.28865-2-peter.maydell@linaro.org
2018-06-22 14:28:39 +02:00
CONFIG_TZ_MPC=y
hw/misc/tz-msc: Model TrustZone Master Security Controller Implement a model of the TrustZone Master Securtiy Controller, as documented in the Arm CoreLink SIE-200 System IP for Embedded TRM (DDI0571G): https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g The MSC is intended to sit in front of a device which can be a bus master (eg a DMA controller) and programmably gate its transactions. This allows a bus-mastering device to be controlled by non-secure code but still restricted from making accesses to addresses which are secure-only. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180820141116.9118-12-peter.maydell@linaro.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-08-24 14:17:43 +02:00
CONFIG_TZ_MSC=y
hw/misc/tz-ppc: Model TrustZone peripheral protection controller Add a model of the TrustZone peripheral protection controller (PPC), which is used to gate transactions to non-TZ-aware peripherals so that secure software can configure them to not be accessible to non-secure software. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-15-peter.maydell@linaro.org
2018-03-02 11:45:39 +01:00
CONFIG_TZ_PPC=y
hw/arm/iotkit: Rename files to hw/arm/armsse.[ch] Rename the files that used to be iotkit.[ch] to armsse.[ch] to reflect the fact they new cover multiple Arm subsystems for embedded. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-8-peter.maydell@linaro.org
2019-02-01 15:55:42 +01:00
CONFIG_ARMSSE=y
hw/misc/iotkit-secctl: Arm IoT Kit security controller initial skeleton The Arm IoT Kit includes a "security controller" which is largely a collection of registers for controlling the PPCs and other bits of glue in the system. This commit provides the initial skeleton of the device, implementing just the ID registers, and a couple of read-only read-as-zero registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-16-peter.maydell@linaro.org
2018-03-02 11:45:39 +01:00
CONFIG_IOTKIT_SECCTL=y
hw/misc/iotkit-sysctl: Implement IoTKit system control element The Arm IoTKit includes a system control element which provides a block of read-only ID registers and a block of read-write control registers. Implement a minimal version of this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180820141116.9118-9-peter.maydell@linaro.org
2018-08-24 14:17:42 +02:00
CONFIG_IOTKIT_SYSCTL=y
hw/misc/iotkit-sysinfo: Implement IoTKit system information block Implement the IoTKit system control element's system information block; this is just a pair of read-only version/config registers, plus the usual PID/CID ID registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180820141116.9118-10-peter.maydell@linaro.org
2018-08-24 14:17:43 +02:00
CONFIG_IOTKIT_SYSINFO=y
hw/misc/armsse-cpuid: Implement SSE-200 CPU_IDENTITY register block The SSE-200 has a CPU_IDENTITY register block, which is a set of read-only registers. As well as the usual PID/CID registers, there is a single CPUID register which indicates whether the CPU is CPU 0 or CPU 1. Implement a model of this register block. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-20-peter.maydell@linaro.org
2019-02-01 15:55:43 +01:00
CONFIG_ARMSSE_CPUID=y
hw/misc/armsse-mhu.c: Model the SSE-200 Message Handling Unit Implement a model of the Message Handling Unit (MHU) found in the Arm SSE-200. This is a simple device which just contains some registers which allow the two cores of the SSE-200 to raise interrupts on each other. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190219125808.25174-2-peter.maydell@linaro.org
2019-02-28 11:55:15 +01:00
CONFIG_ARMSSE_MHU=y
hw/misc/tz-ppc: Model TrustZone peripheral protection controller Add a model of the TrustZone peripheral protection controller (PPC), which is used to gate transactions to non-TZ-aware peripherals so that secure software can configure them to not be accessible to non-secure software. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-15-peter.maydell@linaro.org
2018-03-02 11:45:39 +01:00
hw/pci/Makefile.objs: make pcie configurable Make pcie splited from pci and make it configurable. Signed-off-by: Yang Zhong <yang.zhong@intel.com> Cc: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20190123065618.3520-30-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-01-23 07:56:03 +01:00
CONFIG_PCI_EXPRESS=y
hw/pci-host/Makefile.objs: make CONFIGS clear for PCI EXPRESS Change the CONFIGs for PCI EXPRESS and make module name more clear for code files. Signed-off-by: Yang Zhong <yang.zhong@intel.com> Cc: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20190202072456.6468-5-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-02-02 08:24:33 +01:00
CONFIG_PCI_EXPRESS_GENERIC_BRIDGE=y
arm: Add PCIe host bridge in virt machine Now that we have a working "generic" PCIe host bridge driver, we can plug it into ARM's virt machine to always have PCIe available to normal ARM VMs. I've successfully managed to expose a Bochs VGA device, XHCI and an e1000 into an AArch64 VM with this and they all lived happily ever after. Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: Claudio Fontana <claudio.fontana@huawei.com> [PMM: Squashed in fix for off-by-one error in bus-range DT property from Laszlo Ersek <lersek@redhat.com>] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-02-13 06:46:08 +01:00
hw/timer: add allwinner a10 timer Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387159292-10436-3-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17 20:42:37 +01:00
CONFIG_ALLWINNER_A10_PIT=y
hw/intc: add allwinner A10 interrupt controller Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1387159292-10436-4-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17 20:42:38 +01:00
CONFIG_ALLWINNER_A10_PIC=y
hw/arm: add allwinner a10 SoC support Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387159292-10436-5-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17 20:42:38 +01:00
CONFIG_ALLWINNER_A10=y
Add specific config options for PCI-E bridges The i82801b11, ioh3420 and xio3130 PCI Express devices are currently included in the build unconditionally. While they could theoretically appear on any target platform with PCI-E, they're pretty unlikely to appear on platforms that aren't Intel derived. Therefore, to avoid presenting unlikely-to-be-relevant devices to the user, add config options to enable these components, and enable them by default only on x86 and arm platforms. (Note that this patch does include these for aarch64, via its inclusion of arm-softmmu.mak). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-Id: <1425017077-18487-2-git-send-email-david@gibson.dropbear.id.au> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-02-27 07:04:35 +01:00
i.MX: Add i.MX6 SOC implementation. For now we only support the following devices: * up to 4 Cortex A9 cores * A9 MPCORE (SCU, GIC, TWD) * 5 i.MX UARTs * 2 EPIT timers * 1 GPT timer * 3 I2C controllers * 7 GPIO controllers * 6 SDHC controllers * 5 SPI controllers * 1 CCM device * 1 SRC device * various ROM/RAM areas. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-05-12 14:22:29 +02:00
CONFIG_FSL_IMX6=y
i.MX: Add SOC support for i.MX25 For now we support the following devices: * CPU: ARM926 * Interrupt Controller: AVIC * CCM * UART x 5 * EPIT x 2 * GPT x 4 * FEC * I2C x 3 Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 62218bfa90f9101f79098e768c3d58bd92dcb7f3.1441057361.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 11:39:30 +02:00
CONFIG_FSL_IMX25=y
i.MX: Add i.MX7 SOC implementation. The following interfaces are partially or fully emulated: * up to 2 Cortex A9 cores (SMP works with PSCI) * A7 MPCORE (identical to A15 MPCORE) * 4 GPTs modules * 7 GPIO controllers * 2 IOMUXC controllers * 1 CCM module * 1 SVNS module * 1 SRC module * 1 GPCv2 controller * 4 eCSPI controllers * 4 I2C controllers * 7 i.MX UART controllers * 2 FlexCAN controllers * 2 Ethernet controllers (FEC) * 3 SD controllers (USDHC) * 4 WDT modules * 1 SDMA module * 1 GPR module * 2 USBMISC modules * 2 ADC modules * 1 PCIe controller Tested to boot and work with upstream Linux (4.13+) guest. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> [PMM: folded a couple of long lines] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-09 18:09:43 +01:00
CONFIG_FSL_IMX7=y
i.MX6UL: Add i.MX6UL SOC Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 3853ec555d68e7e25d726170833b775796151a07.1532984236.git.jcd@tribudubois.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16 15:05:28 +02:00
CONFIG_FSL_IMX6UL=y
i.MX: Add SOC support for i.MX31 For now we support the following devices: * CPU: ARM1136 * Interrupt Controller: AVIC * CCM * UART x 2 * EPIT x 2 * GPT Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: f146d819594e41568daec42a1d0f440cdfe3df76.1441057361.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 11:39:30 +02:00
i.MX: Add I2C controller emulator The slave mode is not implemented. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 508dbf2ebe26ec383d3a12a1db5a7890ac8acf20.1441057361.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 11:39:30 +02:00
CONFIG_IMX_I2C=y
hw/pcie: Introduce a base class for PCI Express Root Ports The 'base' PCI Express Root Port includes the common code to be re-used for all Root Ports implementations. Most of the code was taken from the current implementation of Intel's IOH 3420 Root Port. Signed-off-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-01-23 20:20:18 +01:00
CONFIG_PCIE_PORT=y
Add specific config options for PCI-E bridges The i82801b11, ioh3420 and xio3130 PCI Express devices are currently included in the build unconditionally. While they could theoretically appear on any target platform with PCI-E, they're pretty unlikely to appear on platforms that aren't Intel derived. Therefore, to avoid presenting unlikely-to-be-relevant devices to the user, add config options to enable these components, and enable them by default only on x86 and arm platforms. (Note that this patch does include these for aarch64, via its inclusion of arm-softmmu.mak). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-Id: <1425017077-18487-2-git-send-email-david@gibson.dropbear.id.au> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-02-27 07:04:35 +01:00
CONFIG_XIO3130=y
CONFIG_IOH3420=y
CONFIG_I82801B11=y
ACPI: split CONFIG_ACPI into 4 pieces As core.c, piix4.c, ich9.c and pcihp.c are for x86, add CONFIG_ACPI_X86 to make it only for x86. ARM doesn't support cpu and memory hotplug, add CONFIG_ACPI_CPU_HOTPLUG and CONFIG_ACPI_MEMORY_HOTPLUG to exclude them for target-arm. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-24-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29 12:28:59 +02:00
CONFIG_ACPI=y
hw/arm/Makefile.objs: CONFIG_ARM_VIRT created for virt board Make ARM virt code configurable and the new CONFIG_ARM_VIRT definitions added to the default-configs/arm-softmmu.mak. Signed-off-by: Yang Zhong <yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20190202072456.6468-8-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-02-02 08:24:36 +01:00
CONFIG_ARM_VIRT=y
smbios: implement smbios support for mach-virt This patch generates smbios tables for ARM mach-virt. Also add CONFIG_SMBIOS=y for ARM default config. Acked-by: Gabriel Somlo <somlo@cmu.edu> Tested-by: Gabriel Somlo <somlo@cmu.edu> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Wei Huang <wei@redhat.com> Message-id: 1440615870-9518-3-git-send-email-wei@redhat.com [PMM: Added missing braces around an if().] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07 11:39:29 +02:00
CONFIG_SMBIOS=y
hw/gpio: Add the emulation of gpio_key This will be used by ARM virt machine as a power button. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1458221140-15232-2-git-send-email-zhaoshenglong@huawei.com [PMM: Use hyphen rather than underscore in type names; add a comment briefly describing what the device does] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-30 18:27:22 +02:00
CONFIG_GPIO_KEY=y
msf2: Add Smartfusion2 SoC Smartfusion2 SoC has hardened Microcontroller subsystem and flash based FPGA fabric. This patch adds support for Microcontroller subsystem in the SoC. Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170920201737.25723-5-f4bug@amsat.org [PMD: drop cpu_model to directly use cpu type, check m3clk non null] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-20 22:17:36 +02:00
CONFIG_MSF2=y
build-sys: restrict vmcoreinfo to fw_cfg+dma capable targets vmcoreinfo is built for all targets. However, it requires fw_cfg with DMA operations support (write operation). Restrict vmcoreinfo exposure to architectures that are supporting FW_CFG_DMA, that is arm-virt and x86 only atm. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com> Tested-by: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-11-06 12:53:47 +01:00
CONFIG_FW_CFG_DMA=y
hw/pci-host/Makefile.objs: make CONFIGS clear for PCI EXPRESS Change the CONFIGs for PCI EXPRESS and make module name more clear for code files. Signed-off-by: Yang Zhong <yang.zhong@intel.com> Cc: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20190202072456.6468-5-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-02-02 08:24:33 +01:00
CONFIG_PCI_EXPRESS_DESIGNWARE=y
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