2015-05-15 04:22:58 +02:00
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/*
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* Xilinx Zynq MPSoC emulation
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*
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* Copyright (C) 2015 Xilinx Inc
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* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "hw/arm/xlnx-zynqmp.h"
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2015-05-15 04:23:01 +02:00
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#include "exec/address-spaces.h"
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#define GIC_NUM_SPI_INTR 160
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#define GIC_BASE_ADDR 0xf9000000
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#define GIC_DIST_ADDR 0xf9010000
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#define GIC_CPU_ADDR 0xf9020000
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typedef struct XlnxZynqMPGICRegion {
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int region_index;
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uint32_t address;
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} XlnxZynqMPGICRegion;
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static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
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{ .region_index = 0, .address = GIC_DIST_ADDR, },
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{ .region_index = 1, .address = GIC_CPU_ADDR, },
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};
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2015-05-15 04:22:58 +02:00
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static void xlnx_zynqmp_init(Object *obj)
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{
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XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
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int i;
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for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
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object_initialize(&s->cpu[i], sizeof(s->cpu[i]),
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"cortex-a53-" TYPE_ARM_CPU);
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object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
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&error_abort);
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}
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2015-05-15 04:23:01 +02:00
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object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
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qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
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2015-05-15 04:22:58 +02:00
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}
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static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
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{
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XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
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2015-05-15 04:23:01 +02:00
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MemoryRegion *system_memory = get_system_memory();
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2015-05-15 04:22:58 +02:00
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uint8_t i;
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Error *err = NULL;
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2015-05-15 04:23:01 +02:00
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qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
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qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
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qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_CPUS);
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object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
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if (err) {
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error_propagate((errp), (err));
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return;
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}
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assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
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for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
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SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
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const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
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MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
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uint32_t addr = r->address;
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int j;
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sysbus_mmio_map(gic, r->region_index, addr);
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for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
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MemoryRegion *alias = &s->gic_mr[i][j];
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addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
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memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
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0, XLNX_ZYNQMP_GIC_REGION_SIZE);
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memory_region_add_subregion(system_memory, addr, alias);
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}
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}
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2015-05-15 04:22:58 +02:00
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for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
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object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC,
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"psci-conduit", &error_abort);
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if (i > 0) {
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/* Secondary CPUs start in PSCI powered-down state */
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object_property_set_bool(OBJECT(&s->cpu[i]), true,
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"start-powered-off", &error_abort);
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}
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2015-05-15 04:23:01 +02:00
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object_property_set_int(OBJECT(&s->cpu[i]), GIC_BASE_ADDR,
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"reset-cbar", &err);
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if (err) {
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error_propagate((errp), (err));
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return;
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}
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2015-05-15 04:22:58 +02:00
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object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
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if (err) {
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error_propagate((errp), (err));
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return;
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}
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2015-05-15 04:23:01 +02:00
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
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qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
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2015-05-15 04:22:58 +02:00
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}
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}
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static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = xlnx_zynqmp_realize;
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}
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static const TypeInfo xlnx_zynqmp_type_info = {
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.name = TYPE_XLNX_ZYNQMP,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(XlnxZynqMPState),
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.instance_init = xlnx_zynqmp_init,
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.class_init = xlnx_zynqmp_class_init,
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};
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static void xlnx_zynqmp_register_types(void)
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{
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type_register_static(&xlnx_zynqmp_type_info);
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}
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type_init(xlnx_zynqmp_register_types)
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