2005-07-02 16:58:51 +02:00
|
|
|
#include "vl.h"
|
|
|
|
|
|
|
|
#define BIOS_FILENAME "mips_bios.bin"
|
|
|
|
//#define BIOS_FILENAME "system.bin"
|
|
|
|
#define KERNEL_LOAD_ADDR 0x80010000
|
|
|
|
#define INITRD_LOAD_ADDR 0x80800000
|
|
|
|
|
2006-04-27 00:06:55 +02:00
|
|
|
#define VIRT_TO_PHYS_ADDEND (-0x80000000LL)
|
|
|
|
|
2006-10-29 16:38:28 +01:00
|
|
|
static const int ide_iobase[2] = { 0x1f0, 0x170 };
|
|
|
|
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
|
|
|
|
static const int ide_irq[2] = { 14, 15 };
|
|
|
|
|
2005-07-02 16:58:51 +02:00
|
|
|
extern FILE *logfile;
|
|
|
|
|
2005-08-21 11:41:56 +02:00
|
|
|
static PITState *pit;
|
|
|
|
|
2005-07-02 20:11:03 +02:00
|
|
|
static void pic_irq_request(void *opaque, int level)
|
2005-07-02 16:58:51 +02:00
|
|
|
{
|
2005-11-22 00:33:12 +01:00
|
|
|
CPUState *env = first_cpu;
|
2005-07-02 20:11:03 +02:00
|
|
|
if (level) {
|
2005-11-22 00:33:12 +01:00
|
|
|
env->CP0_Cause |= 0x00000400;
|
|
|
|
cpu_interrupt(env, CPU_INTERRUPT_HARD);
|
2005-07-02 16:58:51 +02:00
|
|
|
} else {
|
2005-11-22 00:33:12 +01:00
|
|
|
env->CP0_Cause &= ~0x00000400;
|
|
|
|
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
|
2005-07-02 16:58:51 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_mips_irqctrl_init (void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2006-05-03 00:18:28 +02:00
|
|
|
/* XXX: do not use a global */
|
2005-07-02 16:58:51 +02:00
|
|
|
uint32_t cpu_mips_get_random (CPUState *env)
|
|
|
|
{
|
2006-05-03 00:18:28 +02:00
|
|
|
static uint32_t seed = 0;
|
|
|
|
uint32_t idx;
|
|
|
|
seed = seed * 314159 + 1;
|
|
|
|
idx = (seed >> 16) % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired;
|
|
|
|
return idx;
|
2005-07-02 16:58:51 +02:00
|
|
|
}
|
|
|
|
|
2005-07-02 17:13:42 +02:00
|
|
|
/* MIPS R4K timer */
|
2005-07-02 16:58:51 +02:00
|
|
|
uint32_t cpu_mips_get_count (CPUState *env)
|
|
|
|
{
|
|
|
|
return env->CP0_Count +
|
|
|
|
(uint32_t)muldiv64(qemu_get_clock(vm_clock),
|
|
|
|
100 * 1000 * 1000, ticks_per_sec);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void cpu_mips_update_count (CPUState *env, uint32_t count,
|
|
|
|
uint32_t compare)
|
|
|
|
{
|
|
|
|
uint64_t now, next;
|
|
|
|
uint32_t tmp;
|
|
|
|
|
|
|
|
tmp = count;
|
|
|
|
if (count == compare)
|
|
|
|
tmp++;
|
|
|
|
now = qemu_get_clock(vm_clock);
|
|
|
|
next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000);
|
|
|
|
if (next == now)
|
|
|
|
next++;
|
2005-12-05 20:56:38 +01:00
|
|
|
#if 0
|
2005-07-02 16:58:51 +02:00
|
|
|
if (logfile) {
|
2006-06-25 20:15:32 +02:00
|
|
|
fprintf(logfile, "%s: 0x%08" PRIx64 " %08x %08x => 0x%08" PRIx64 "\n",
|
2005-07-02 16:58:51 +02:00
|
|
|
__func__, now, count, compare, next - now);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
/* Store new count and compare registers */
|
|
|
|
env->CP0_Compare = compare;
|
|
|
|
env->CP0_Count =
|
|
|
|
count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec);
|
|
|
|
/* Adjust timer */
|
|
|
|
qemu_mod_timer(env->timer, next);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_mips_store_count (CPUState *env, uint32_t value)
|
|
|
|
{
|
|
|
|
cpu_mips_update_count(env, value, env->CP0_Compare);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_mips_store_compare (CPUState *env, uint32_t value)
|
|
|
|
{
|
|
|
|
cpu_mips_update_count(env, cpu_mips_get_count(env), value);
|
2005-11-22 00:33:12 +01:00
|
|
|
env->CP0_Cause &= ~0x00008000;
|
|
|
|
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
|
2005-07-02 16:58:51 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void mips_timer_cb (void *opaque)
|
|
|
|
{
|
|
|
|
CPUState *env;
|
|
|
|
|
|
|
|
env = opaque;
|
2005-12-05 20:56:38 +01:00
|
|
|
#if 0
|
2005-07-02 16:58:51 +02:00
|
|
|
if (logfile) {
|
|
|
|
fprintf(logfile, "%s\n", __func__);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
|
2005-11-22 00:33:12 +01:00
|
|
|
env->CP0_Cause |= 0x00008000;
|
|
|
|
cpu_interrupt(env, CPU_INTERRUPT_HARD);
|
2005-07-02 16:58:51 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_mips_clock_init (CPUState *env)
|
|
|
|
{
|
|
|
|
env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env);
|
|
|
|
env->CP0_Compare = 0;
|
|
|
|
cpu_mips_update_count(env, 1, 0);
|
|
|
|
}
|
|
|
|
|
2006-12-06 18:48:52 +01:00
|
|
|
static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
|
|
|
|
uint32_t val)
|
|
|
|
{
|
|
|
|
if ((addr & 0xffff) == 0 && val == 42)
|
|
|
|
qemu_system_reset_request ();
|
|
|
|
else if ((addr & 0xffff) == 4 && val == 42)
|
|
|
|
qemu_system_shutdown_request ();
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static CPUWriteMemoryFunc *mips_qemu_write[] = {
|
|
|
|
&mips_qemu_writel,
|
|
|
|
&mips_qemu_writel,
|
|
|
|
&mips_qemu_writel,
|
|
|
|
};
|
|
|
|
|
|
|
|
static CPUReadMemoryFunc *mips_qemu_read[] = {
|
|
|
|
&mips_qemu_readl,
|
|
|
|
&mips_qemu_readl,
|
|
|
|
&mips_qemu_readl,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int mips_qemu_iomemtype = 0;
|
|
|
|
|
|
|
|
void load_kernel (CPUState *env, int ram_size, const char *kernel_filename,
|
|
|
|
const char *kernel_cmdline,
|
|
|
|
const char *initrd_filename)
|
|
|
|
{
|
|
|
|
int64_t entry = 0;
|
|
|
|
long kernel_size, initrd_size;
|
|
|
|
|
|
|
|
kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry);
|
|
|
|
if (kernel_size >= 0)
|
|
|
|
env->PC = entry;
|
|
|
|
else {
|
|
|
|
kernel_size = load_image(kernel_filename,
|
|
|
|
phys_ram_base + KERNEL_LOAD_ADDR + VIRT_TO_PHYS_ADDEND);
|
|
|
|
if (kernel_size < 0) {
|
|
|
|
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
|
|
|
kernel_filename);
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
env->PC = KERNEL_LOAD_ADDR;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* load initrd */
|
|
|
|
initrd_size = 0;
|
|
|
|
if (initrd_filename) {
|
|
|
|
initrd_size = load_image(initrd_filename,
|
|
|
|
phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND);
|
|
|
|
if (initrd_size == (target_ulong) -1) {
|
|
|
|
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
|
|
|
initrd_filename);
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Store command line. */
|
|
|
|
if (initrd_size > 0) {
|
|
|
|
int ret;
|
|
|
|
ret = sprintf(phys_ram_base + (16 << 20) - 256,
|
|
|
|
"rd_start=0x%08x rd_size=%li ",
|
|
|
|
INITRD_LOAD_ADDR,
|
|
|
|
initrd_size);
|
|
|
|
strcpy (phys_ram_base + (16 << 20) - 256 + ret, kernel_cmdline);
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline);
|
|
|
|
}
|
|
|
|
|
|
|
|
*(int *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678);
|
|
|
|
*(int *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void main_cpu_reset(void *opaque)
|
|
|
|
{
|
|
|
|
CPUState *env = opaque;
|
|
|
|
cpu_reset(env);
|
|
|
|
|
|
|
|
if (env->kernel_filename)
|
|
|
|
load_kernel (env, env->ram_size, env->kernel_filename,
|
|
|
|
env->kernel_cmdline, env->initrd_filename);
|
|
|
|
}
|
2006-04-27 00:06:55 +02:00
|
|
|
|
2005-07-02 16:58:51 +02:00
|
|
|
void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
|
|
|
|
DisplayState *ds, const char **fd_filename, int snapshot,
|
|
|
|
const char *kernel_filename, const char *kernel_cmdline,
|
|
|
|
const char *initrd_filename)
|
|
|
|
{
|
|
|
|
char buf[1024];
|
|
|
|
unsigned long bios_offset;
|
|
|
|
int ret;
|
2005-11-22 00:33:12 +01:00
|
|
|
CPUState *env;
|
2006-10-29 16:38:28 +01:00
|
|
|
int i;
|
2005-11-22 00:33:12 +01:00
|
|
|
|
|
|
|
env = cpu_init();
|
|
|
|
register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
|
2006-12-06 18:48:52 +01:00
|
|
|
qemu_register_reset(main_cpu_reset, env);
|
2005-11-22 00:33:12 +01:00
|
|
|
|
2005-07-02 16:58:51 +02:00
|
|
|
/* allocate RAM */
|
|
|
|
cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
|
2006-04-27 00:06:55 +02:00
|
|
|
|
2006-12-06 18:48:52 +01:00
|
|
|
if (!mips_qemu_iomemtype) {
|
|
|
|
mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read,
|
|
|
|
mips_qemu_write, NULL);
|
|
|
|
}
|
|
|
|
cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);
|
|
|
|
|
2006-04-27 00:06:55 +02:00
|
|
|
/* Try to load a BIOS image. If this fails, we continue regardless,
|
|
|
|
but initialize the hardware ourselves. When a kernel gets
|
|
|
|
preloaded we also initialize the hardware, since the BIOS wasn't
|
|
|
|
run. */
|
2005-07-02 16:58:51 +02:00
|
|
|
bios_offset = ram_size + vga_ram_size;
|
|
|
|
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
|
|
|
|
ret = load_image(buf, phys_ram_base + bios_offset);
|
2006-04-27 00:06:55 +02:00
|
|
|
if (ret == BIOS_SIZE) {
|
|
|
|
cpu_register_physical_memory((uint32_t)(0x1fc00000),
|
|
|
|
BIOS_SIZE, bios_offset | IO_MEM_ROM);
|
|
|
|
} else {
|
|
|
|
/* not fatal */
|
|
|
|
fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
|
|
|
|
buf);
|
2005-07-02 16:58:51 +02:00
|
|
|
}
|
2006-04-27 00:06:55 +02:00
|
|
|
|
|
|
|
if (kernel_filename) {
|
2006-12-06 18:48:52 +01:00
|
|
|
load_kernel (env, ram_size, kernel_filename, kernel_cmdline,
|
|
|
|
initrd_filename);
|
|
|
|
env->ram_size = ram_size;
|
|
|
|
env->kernel_filename = kernel_filename;
|
|
|
|
env->kernel_cmdline = kernel_cmdline;
|
|
|
|
env->initrd_filename = initrd_filename;
|
2005-07-02 16:58:51 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Init internal devices */
|
2005-11-22 00:33:12 +01:00
|
|
|
cpu_mips_clock_init(env);
|
2005-07-02 16:58:51 +02:00
|
|
|
cpu_mips_irqctrl_init();
|
|
|
|
|
2005-07-02 17:20:29 +02:00
|
|
|
/* Register 64 KB of ISA IO space at 0x14000000 */
|
2006-09-18 03:15:29 +02:00
|
|
|
isa_mmio_init(0x14000000, 0x00010000);
|
2005-07-02 17:20:29 +02:00
|
|
|
isa_mem_base = 0x10000000;
|
|
|
|
|
2005-11-22 00:33:12 +01:00
|
|
|
isa_pic = pic_init(pic_irq_request, env);
|
2005-08-21 11:41:56 +02:00
|
|
|
pit = pit_init(0x40, 0);
|
2005-11-23 22:11:49 +01:00
|
|
|
serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]);
|
2006-08-17 12:45:20 +02:00
|
|
|
isa_vga_init(ds, phys_ram_base + ram_size, ram_size,
|
|
|
|
vga_ram_size);
|
2005-07-02 17:26:04 +02:00
|
|
|
|
2006-02-05 05:14:41 +01:00
|
|
|
if (nd_table[0].vlan) {
|
|
|
|
if (nd_table[0].model == NULL
|
|
|
|
|| strcmp(nd_table[0].model, "ne2k_isa") == 0) {
|
|
|
|
isa_ne2000_init(0x300, 9, &nd_table[0]);
|
|
|
|
} else {
|
|
|
|
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
|
|
|
|
exit (1);
|
|
|
|
}
|
|
|
|
}
|
2006-10-29 16:38:28 +01:00
|
|
|
|
|
|
|
for(i = 0; i < 2; i++)
|
|
|
|
isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
|
|
|
|
bs_table[2 * i], bs_table[2 * i + 1]);
|
2005-07-02 16:58:51 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
QEMUMachine mips_machine = {
|
|
|
|
"mips",
|
|
|
|
"mips r4k platform",
|
|
|
|
mips_r4k_init,
|
|
|
|
};
|