2016-10-22 11:46:39 +02:00
|
|
|
/*
|
|
|
|
* QEMU PowerPC PowerNV CPU Core model
|
|
|
|
*
|
|
|
|
* Copyright (c) 2016, IBM Corporation.
|
|
|
|
*
|
|
|
|
* This library is free software; you can redistribute it and/or
|
|
|
|
* modify it under the terms of the GNU Lesser General Public License
|
|
|
|
* as published by the Free Software Foundation; either version 2 of
|
|
|
|
* the License, or (at your option) any later version.
|
|
|
|
*
|
|
|
|
* This library is distributed in the hope that it will be useful, but
|
|
|
|
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
|
|
* Lesser General Public License for more details.
|
|
|
|
*
|
|
|
|
* You should have received a copy of the GNU Lesser General Public
|
|
|
|
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
|
|
|
*/
|
2019-05-23 16:35:07 +02:00
|
|
|
|
2016-10-22 11:46:39 +02:00
|
|
|
#include "qemu/osdep.h"
|
2019-08-12 07:23:38 +02:00
|
|
|
#include "sysemu/reset.h"
|
2016-10-22 11:46:39 +02:00
|
|
|
#include "qapi/error.h"
|
2016-10-22 11:46:41 +02:00
|
|
|
#include "qemu/log.h"
|
2019-05-23 16:35:07 +02:00
|
|
|
#include "qemu/module.h"
|
2016-10-11 08:56:52 +02:00
|
|
|
#include "target/ppc/cpu.h"
|
2016-10-22 11:46:39 +02:00
|
|
|
#include "hw/ppc/ppc.h"
|
|
|
|
#include "hw/ppc/pnv.h"
|
|
|
|
#include "hw/ppc/pnv_core.h"
|
2016-11-07 19:03:02 +01:00
|
|
|
#include "hw/ppc/pnv_xscom.h"
|
2017-04-03 09:46:03 +02:00
|
|
|
#include "hw/ppc/xics.h"
|
2019-08-12 07:23:51 +02:00
|
|
|
#include "hw/qdev-properties.h"
|
2016-10-22 11:46:39 +02:00
|
|
|
|
2017-10-09 21:51:08 +02:00
|
|
|
static const char *pnv_core_cpu_typename(PnvCore *pc)
|
|
|
|
{
|
|
|
|
const char *core_type = object_class_get_name(object_get_class(OBJECT(pc)));
|
|
|
|
int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX);
|
|
|
|
char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type);
|
|
|
|
const char *cpu_type = object_class_get_name(object_class_by_name(s));
|
|
|
|
g_free(s);
|
|
|
|
return cpu_type;
|
|
|
|
}
|
|
|
|
|
2020-01-27 15:41:53 +01:00
|
|
|
static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu)
|
2016-10-22 11:46:39 +02:00
|
|
|
{
|
|
|
|
CPUState *cs = CPU(cpu);
|
|
|
|
CPUPPCState *env = &cpu->env;
|
2020-01-27 15:41:53 +01:00
|
|
|
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip);
|
2016-10-22 11:46:39 +02:00
|
|
|
|
|
|
|
cpu_reset(cs);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* the skiboot firmware elects a primary thread to initialize the
|
|
|
|
* system and it can be any.
|
|
|
|
*/
|
|
|
|
env->gpr[3] = PNV_FDT_ADDR;
|
|
|
|
env->nip = 0x10;
|
|
|
|
env->msr |= MSR_HVB; /* Hypervisor mode */
|
2019-10-22 18:38:10 +02:00
|
|
|
|
2020-01-27 15:41:54 +01:00
|
|
|
env->spr[SPR_HRMOR] = pc->hrmor;
|
|
|
|
|
2020-01-27 15:41:53 +01:00
|
|
|
pcc->intc_reset(pc->chip, cpu);
|
2016-10-22 11:46:39 +02:00
|
|
|
}
|
|
|
|
|
2016-10-22 11:46:41 +02:00
|
|
|
/*
|
|
|
|
* These values are read by the PowerNV HW monitors under Linux
|
|
|
|
*/
|
|
|
|
#define PNV_XSCOM_EX_DTS_RESULT0 0x50000
|
|
|
|
#define PNV_XSCOM_EX_DTS_RESULT1 0x50001
|
|
|
|
|
2019-03-07 23:35:43 +01:00
|
|
|
static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr,
|
|
|
|
unsigned int width)
|
2016-10-22 11:46:41 +02:00
|
|
|
{
|
|
|
|
uint32_t offset = addr >> 3;
|
|
|
|
uint64_t val = 0;
|
|
|
|
|
|
|
|
/* The result should be 38 C */
|
|
|
|
switch (offset) {
|
|
|
|
case PNV_XSCOM_EX_DTS_RESULT0:
|
|
|
|
val = 0x26f024f023f0000ull;
|
|
|
|
break;
|
|
|
|
case PNV_XSCOM_EX_DTS_RESULT1:
|
|
|
|
val = 0x24f000000000000ull;
|
|
|
|
break;
|
|
|
|
default:
|
2018-06-08 14:15:33 +02:00
|
|
|
qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
|
2016-10-22 11:46:41 +02:00
|
|
|
addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2019-03-07 23:35:43 +01:00
|
|
|
static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val,
|
|
|
|
unsigned int width)
|
2016-10-22 11:46:41 +02:00
|
|
|
{
|
2018-06-08 14:15:33 +02:00
|
|
|
qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
|
2016-10-22 11:46:41 +02:00
|
|
|
addr);
|
|
|
|
}
|
|
|
|
|
2019-03-07 23:35:43 +01:00
|
|
|
static const MemoryRegionOps pnv_core_power8_xscom_ops = {
|
|
|
|
.read = pnv_core_power8_xscom_read,
|
|
|
|
.write = pnv_core_power8_xscom_write,
|
|
|
|
.valid.min_access_size = 8,
|
|
|
|
.valid.max_access_size = 8,
|
|
|
|
.impl.min_access_size = 8,
|
|
|
|
.impl.max_access_size = 8,
|
|
|
|
.endianness = DEVICE_BIG_ENDIAN,
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* POWER9 core controls
|
|
|
|
*/
|
|
|
|
#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d
|
|
|
|
#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a
|
|
|
|
|
|
|
|
static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
|
|
|
|
unsigned int width)
|
|
|
|
{
|
|
|
|
uint32_t offset = addr >> 3;
|
|
|
|
uint64_t val = 0;
|
|
|
|
|
|
|
|
/* The result should be 38 C */
|
|
|
|
switch (offset) {
|
|
|
|
case PNV_XSCOM_EX_DTS_RESULT0:
|
|
|
|
val = 0x26f024f023f0000ull;
|
|
|
|
break;
|
|
|
|
case PNV_XSCOM_EX_DTS_RESULT1:
|
|
|
|
val = 0x24f000000000000ull;
|
|
|
|
break;
|
|
|
|
case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
|
|
|
|
case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
|
|
|
|
val = 0x0;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
|
|
|
|
addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val,
|
|
|
|
unsigned int width)
|
|
|
|
{
|
|
|
|
uint32_t offset = addr >> 3;
|
|
|
|
|
|
|
|
switch (offset) {
|
|
|
|
case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
|
|
|
|
case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
|
|
|
|
addr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps pnv_core_power9_xscom_ops = {
|
|
|
|
.read = pnv_core_power9_xscom_read,
|
|
|
|
.write = pnv_core_power9_xscom_write,
|
2016-10-22 11:46:41 +02:00
|
|
|
.valid.min_access_size = 8,
|
|
|
|
.valid.max_access_size = 8,
|
|
|
|
.impl.min_access_size = 8,
|
|
|
|
.impl.max_access_size = 8,
|
|
|
|
.endianness = DEVICE_BIG_ENDIAN,
|
|
|
|
};
|
|
|
|
|
2020-01-27 15:41:53 +01:00
|
|
|
static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp)
|
2016-10-22 11:46:39 +02:00
|
|
|
{
|
2018-06-13 05:34:36 +02:00
|
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
int core_pir;
|
|
|
|
int thread_index = 0; /* TODO: TCG supports only one thread */
|
|
|
|
ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
|
2016-10-22 11:46:39 +02:00
|
|
|
Error *local_err = NULL;
|
2020-01-27 15:41:53 +01:00
|
|
|
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip);
|
2017-04-03 09:46:03 +02:00
|
|
|
|
2018-06-13 05:34:36 +02:00
|
|
|
object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
|
2017-04-03 09:46:03 +02:00
|
|
|
if (local_err) {
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
return;
|
|
|
|
}
|
2016-10-22 11:46:39 +02:00
|
|
|
|
2020-01-27 15:41:53 +01:00
|
|
|
pcc->intc_create(pc->chip, cpu, &local_err);
|
2016-10-22 11:46:39 +02:00
|
|
|
if (local_err) {
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2020-01-27 15:41:53 +01:00
|
|
|
core_pir = object_property_get_uint(OBJECT(pc), "pir", &error_abort);
|
2018-06-13 05:34:36 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* The PIR of a thread is the core PIR + the thread index. We will
|
|
|
|
* need to find a way to get the thread index when TCG supports
|
|
|
|
* more than 1. We could use the object name ?
|
|
|
|
*/
|
|
|
|
pir->default_value = core_pir + thread_index;
|
|
|
|
|
|
|
|
/* Set time-base frequency to 512 MHz */
|
|
|
|
cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
|
2019-10-22 18:38:08 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void pnv_core_reset(void *dev)
|
|
|
|
{
|
|
|
|
CPUCore *cc = CPU_CORE(dev);
|
|
|
|
PnvCore *pc = PNV_CORE(dev);
|
|
|
|
int i;
|
2018-06-13 05:34:36 +02:00
|
|
|
|
2019-10-22 18:38:08 +02:00
|
|
|
for (i = 0; i < cc->nr_threads; i++) {
|
2020-01-27 15:41:53 +01:00
|
|
|
pnv_core_cpu_reset(pc, pc->threads[i]);
|
2019-10-22 18:38:08 +02:00
|
|
|
}
|
2016-10-22 11:46:39 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void pnv_core_realize(DeviceState *dev, Error **errp)
|
|
|
|
{
|
|
|
|
PnvCore *pc = PNV_CORE(OBJECT(dev));
|
2019-03-07 23:35:43 +01:00
|
|
|
PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc);
|
2016-10-22 11:46:39 +02:00
|
|
|
CPUCore *cc = CPU_CORE(OBJECT(dev));
|
2017-10-09 21:51:08 +02:00
|
|
|
const char *typename = pnv_core_cpu_typename(pc);
|
2016-10-22 11:46:39 +02:00
|
|
|
Error *local_err = NULL;
|
|
|
|
void *obj;
|
|
|
|
int i, j;
|
|
|
|
char name[32];
|
2017-04-03 09:46:03 +02:00
|
|
|
|
2019-11-15 16:56:00 +01:00
|
|
|
assert(pc->chip);
|
2016-10-22 11:46:39 +02:00
|
|
|
|
2018-06-13 03:57:37 +02:00
|
|
|
pc->threads = g_new(PowerPCCPU *, cc->nr_threads);
|
2016-10-22 11:46:39 +02:00
|
|
|
for (i = 0; i < cc->nr_threads; i++) {
|
2019-01-17 08:53:25 +01:00
|
|
|
PowerPCCPU *cpu;
|
|
|
|
|
2018-06-13 03:57:37 +02:00
|
|
|
obj = object_new(typename);
|
2019-01-17 08:53:25 +01:00
|
|
|
cpu = POWERPC_CPU(obj);
|
2016-10-22 11:46:39 +02:00
|
|
|
|
2018-06-13 03:57:37 +02:00
|
|
|
pc->threads[i] = POWERPC_CPU(obj);
|
2016-10-22 11:46:39 +02:00
|
|
|
|
|
|
|
snprintf(name, sizeof(name), "thread[%d]", i);
|
qom: Drop parameter @errp of object_property_add() & friends
The only way object_property_add() can fail is when a property with
the same name already exists. Since our property names are all
hardcoded, failure is a programming error, and the appropriate way to
handle it is passing &error_abort.
Same for its variants, except for object_property_add_child(), which
additionally fails when the child already has a parent. Parentage is
also under program control, so this is a programming error, too.
We have a bit over 500 callers. Almost half of them pass
&error_abort, slightly fewer ignore errors, one test case handles
errors, and the remaining few callers pass them to their own callers.
The previous few commits demonstrated once again that ignoring
programming errors is a bad idea.
Of the few ones that pass on errors, several violate the Error API.
The Error ** argument must be NULL, &error_abort, &error_fatal, or a
pointer to a variable containing NULL. Passing an argument of the
latter kind twice without clearing it in between is wrong: if the
first call sets an error, it no longer points to NULL for the second
call. ich9_pm_add_properties(), sparc32_ledma_realize(),
sparc32_dma_realize(), xilinx_axidma_realize(), xilinx_enet_realize()
are wrong that way.
When the one appropriate choice of argument is &error_abort, letting
users pick the argument is a bad idea.
Drop parameter @errp and assert the preconditions instead.
There's one exception to "duplicate property name is a programming
error": the way object_property_add() implements the magic (and
undocumented) "automatic arrayification". Don't drop @errp there.
Instead, rename object_property_add() to object_property_try_add(),
and add the obvious wrapper object_property_add().
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200505152926.18877-15-armbru@redhat.com>
[Two semantic rebase conflicts resolved]
2020-05-05 17:29:22 +02:00
|
|
|
object_property_add_child(OBJECT(pc), name, obj);
|
2019-01-17 08:53:25 +01:00
|
|
|
|
|
|
|
cpu->machine_data = g_new0(PnvCPUState, 1);
|
|
|
|
|
2016-10-22 11:46:39 +02:00
|
|
|
object_unref(obj);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (j = 0; j < cc->nr_threads; j++) {
|
2020-01-27 15:41:53 +01:00
|
|
|
pnv_core_cpu_realize(pc, pc->threads[j], &local_err);
|
2016-10-22 11:46:39 +02:00
|
|
|
if (local_err) {
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
}
|
2016-10-22 11:46:41 +02:00
|
|
|
|
|
|
|
snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
|
2019-12-05 19:44:51 +01:00
|
|
|
/* TODO: check PNV_XSCOM_EX_SIZE for p10 */
|
2019-03-07 23:35:43 +01:00
|
|
|
pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops,
|
2018-01-15 19:04:04 +01:00
|
|
|
pc, name, PNV_XSCOM_EX_SIZE);
|
2019-10-22 18:38:08 +02:00
|
|
|
|
|
|
|
qemu_register_reset(pnv_core_reset, pc);
|
2016-10-22 11:46:39 +02:00
|
|
|
return;
|
|
|
|
|
|
|
|
err:
|
|
|
|
while (--i >= 0) {
|
2018-06-13 03:57:37 +02:00
|
|
|
obj = OBJECT(pc->threads[i]);
|
2016-10-22 11:46:39 +02:00
|
|
|
object_unparent(obj);
|
|
|
|
}
|
|
|
|
g_free(pc->threads);
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
}
|
|
|
|
|
2020-01-27 15:41:53 +01:00
|
|
|
static void pnv_core_cpu_unrealize(PnvCore *pc, PowerPCCPU *cpu)
|
2018-06-13 04:08:42 +02:00
|
|
|
{
|
2019-01-17 08:53:25 +01:00
|
|
|
PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
|
2020-01-27 15:41:53 +01:00
|
|
|
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip);
|
2019-01-17 08:53:25 +01:00
|
|
|
|
2020-01-27 15:41:53 +01:00
|
|
|
pcc->intc_destroy(pc->chip, cpu);
|
2018-06-13 04:08:42 +02:00
|
|
|
cpu_remove_sync(CPU(cpu));
|
2019-01-17 08:53:25 +01:00
|
|
|
cpu->machine_data = NULL;
|
|
|
|
g_free(pnv_cpu);
|
2018-06-13 04:08:42 +02:00
|
|
|
object_unparent(OBJECT(cpu));
|
|
|
|
}
|
|
|
|
|
qdev: Unrealize must not fail
Devices may have component devices and buses.
Device realization may fail. Realization is recursive: a device's
realize() method realizes its components, and device_set_realized()
realizes its buses (which should in turn realize the devices on that
bus, except bus_set_realized() doesn't implement that, yet).
When realization of a component or bus fails, we need to roll back:
unrealize everything we realized so far. If any of these unrealizes
failed, the device would be left in an inconsistent state. Must not
happen.
device_set_realized() lets it happen: it ignores errors in the roll
back code starting at label child_realize_fail.
Since realization is recursive, unrealization must be recursive, too.
But how could a partly failed unrealize be rolled back? We'd have to
re-realize, which can fail. This design is fundamentally broken.
device_set_realized() does not roll back at all. Instead, it keeps
unrealizing, ignoring further errors.
It can screw up even for a device with no buses: if the lone
dc->unrealize() fails, it still unregisters vmstate, and calls
listeners' unrealize() callback.
bus_set_realized() does not roll back either. Instead, it stops
unrealizing.
Fortunately, no unrealize method can fail, as we'll see below.
To fix the design error, drop parameter @errp from all the unrealize
methods.
Any unrealize method that uses @errp now needs an update. This leads
us to unrealize() methods that can fail. Merely passing it to another
unrealize method cannot cause failure, though. Here are the ones that
do other things with @errp:
* virtio_serial_device_unrealize()
Fails when qbus_set_hotplug_handler() fails, but still does all the
other work. On failure, the device would stay realized with its
resources completely gone. Oops. Can't happen, because
qbus_set_hotplug_handler() can't actually fail here. Pass
&error_abort to qbus_set_hotplug_handler() instead.
* hw/ppc/spapr_drc.c's unrealize()
Fails when object_property_del() fails, but all the other work is
already done. On failure, the device would stay realized with its
vmstate registration gone. Oops. Can't happen, because
object_property_del() can't actually fail here. Pass &error_abort
to object_property_del() instead.
* spapr_phb_unrealize()
Fails and bails out when remove_drcs() fails, but other work is
already done. On failure, the device would stay realized with some
of its resources gone. Oops. remove_drcs() fails only when
chassis_from_bus()'s object_property_get_uint() fails, and it can't
here. Pass &error_abort to remove_drcs() instead.
Therefore, no unrealize method can fail before this patch.
device_set_realized()'s recursive unrealization via bus uses
object_property_set_bool(). Can't drop @errp there, so pass
&error_abort.
We similarly unrealize with object_property_set_bool() elsewhere,
always ignoring errors. Pass &error_abort instead.
Several unrealize methods no longer handle errors from other unrealize
methods: virtio_9p_device_unrealize(),
virtio_input_device_unrealize(), scsi_qdev_unrealize(), ...
Much of the deleted error handling looks wrong anyway.
One unrealize methods no longer ignore such errors:
usb_ehci_pci_exit().
Several realize methods no longer ignore errors when rolling back:
v9fs_device_realize_common(), pci_qdev_unrealize(),
spapr_phb_realize(), usb_qdev_realize(), vfio_ccw_realize(),
virtio_device_realize().
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200505152926.18877-17-armbru@redhat.com>
2020-05-05 17:29:24 +02:00
|
|
|
static void pnv_core_unrealize(DeviceState *dev)
|
2018-06-13 04:08:42 +02:00
|
|
|
{
|
|
|
|
PnvCore *pc = PNV_CORE(dev);
|
|
|
|
CPUCore *cc = CPU_CORE(dev);
|
|
|
|
int i;
|
|
|
|
|
2019-10-22 18:38:08 +02:00
|
|
|
qemu_unregister_reset(pnv_core_reset, pc);
|
|
|
|
|
2018-06-13 04:08:42 +02:00
|
|
|
for (i = 0; i < cc->nr_threads; i++) {
|
2020-01-27 15:41:53 +01:00
|
|
|
pnv_core_cpu_unrealize(pc, pc->threads[i]);
|
2018-06-13 04:08:42 +02:00
|
|
|
}
|
|
|
|
g_free(pc->threads);
|
|
|
|
}
|
|
|
|
|
2016-10-22 11:46:39 +02:00
|
|
|
static Property pnv_core_properties[] = {
|
|
|
|
DEFINE_PROP_UINT32("pir", PnvCore, pir, 0),
|
2020-01-27 15:41:54 +01:00
|
|
|
DEFINE_PROP_UINT64("hrmor", PnvCore, hrmor, 0),
|
2019-11-15 16:56:00 +01:00
|
|
|
DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *),
|
2016-10-22 11:46:39 +02:00
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
2019-03-07 23:35:43 +01:00
|
|
|
static void pnv_core_power8_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
|
|
|
|
|
|
|
|
pcc->xscom_ops = &pnv_core_power8_xscom_ops;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pnv_core_power9_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
|
|
|
|
|
|
|
|
pcc->xscom_ops = &pnv_core_power9_xscom_ops;
|
|
|
|
}
|
|
|
|
|
2019-12-05 19:44:51 +01:00
|
|
|
static void pnv_core_power10_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
|
|
|
|
|
|
|
|
/* TODO: Use the P9 XSCOMs for now on P10 */
|
|
|
|
pcc->xscom_ops = &pnv_core_power9_xscom_ops;
|
|
|
|
}
|
|
|
|
|
2016-10-22 11:46:39 +02:00
|
|
|
static void pnv_core_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
|
|
|
|
dc->realize = pnv_core_realize;
|
2018-06-13 04:08:42 +02:00
|
|
|
dc->unrealize = pnv_core_unrealize;
|
2020-01-10 16:30:32 +01:00
|
|
|
device_class_set_props(dc, pnv_core_properties);
|
2020-01-29 12:37:20 +01:00
|
|
|
dc->user_creatable = false;
|
2016-10-22 11:46:39 +02:00
|
|
|
}
|
|
|
|
|
2019-03-07 23:35:43 +01:00
|
|
|
#define DEFINE_PNV_CORE_TYPE(family, cpu_model) \
|
2017-10-09 21:51:09 +02:00
|
|
|
{ \
|
|
|
|
.parent = TYPE_PNV_CORE, \
|
|
|
|
.name = PNV_CORE_TYPE_NAME(cpu_model), \
|
2019-03-07 23:35:43 +01:00
|
|
|
.class_init = pnv_core_##family##_class_init, \
|
2016-10-22 11:46:39 +02:00
|
|
|
}
|
|
|
|
|
2017-10-09 21:51:09 +02:00
|
|
|
static const TypeInfo pnv_core_infos[] = {
|
|
|
|
{
|
|
|
|
.name = TYPE_PNV_CORE,
|
|
|
|
.parent = TYPE_CPU_CORE,
|
|
|
|
.instance_size = sizeof(PnvCore),
|
|
|
|
.class_size = sizeof(PnvCoreClass),
|
|
|
|
.class_init = pnv_core_class_init,
|
|
|
|
.abstract = true,
|
|
|
|
},
|
2019-03-07 23:35:43 +01:00
|
|
|
DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"),
|
|
|
|
DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"),
|
|
|
|
DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
|
|
|
|
DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"),
|
2019-12-05 19:44:51 +01:00
|
|
|
DEFINE_PNV_CORE_TYPE(power10, "power10_v1.0"),
|
2017-10-09 21:51:09 +02:00
|
|
|
};
|
2016-10-22 11:46:39 +02:00
|
|
|
|
2017-10-09 21:51:09 +02:00
|
|
|
DEFINE_TYPES(pnv_core_infos)
|
2019-03-07 23:35:44 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* POWER9 Quads
|
|
|
|
*/
|
|
|
|
|
|
|
|
#define P9X_EX_NCU_SPEC_BAR 0x11010
|
|
|
|
|
|
|
|
static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
|
|
|
|
unsigned int width)
|
|
|
|
{
|
|
|
|
uint32_t offset = addr >> 3;
|
|
|
|
uint64_t val = -1;
|
|
|
|
|
|
|
|
switch (offset) {
|
|
|
|
case P9X_EX_NCU_SPEC_BAR:
|
|
|
|
case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
|
|
|
|
val = 0;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
|
|
|
|
offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
|
|
|
|
unsigned int width)
|
|
|
|
{
|
|
|
|
uint32_t offset = addr >> 3;
|
|
|
|
|
|
|
|
switch (offset) {
|
|
|
|
case P9X_EX_NCU_SPEC_BAR:
|
|
|
|
case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
|
|
|
|
offset);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps pnv_quad_xscom_ops = {
|
|
|
|
.read = pnv_quad_xscom_read,
|
|
|
|
.write = pnv_quad_xscom_write,
|
|
|
|
.valid.min_access_size = 8,
|
|
|
|
.valid.max_access_size = 8,
|
|
|
|
.impl.min_access_size = 8,
|
|
|
|
.impl.max_access_size = 8,
|
|
|
|
.endianness = DEVICE_BIG_ENDIAN,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void pnv_quad_realize(DeviceState *dev, Error **errp)
|
|
|
|
{
|
|
|
|
PnvQuad *eq = PNV_QUAD(dev);
|
|
|
|
char name[32];
|
|
|
|
|
|
|
|
snprintf(name, sizeof(name), "xscom-quad.%d", eq->id);
|
|
|
|
pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops,
|
|
|
|
eq, name, PNV9_XSCOM_EQ_SIZE);
|
|
|
|
}
|
|
|
|
|
|
|
|
static Property pnv_quad_properties[] = {
|
|
|
|
DEFINE_PROP_UINT32("id", PnvQuad, id, 0),
|
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
|
|
|
static void pnv_quad_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
|
|
|
|
dc->realize = pnv_quad_realize;
|
2020-01-10 16:30:32 +01:00
|
|
|
device_class_set_props(dc, pnv_quad_properties);
|
2020-01-29 12:37:20 +01:00
|
|
|
dc->user_creatable = false;
|
2019-03-07 23:35:44 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo pnv_quad_info = {
|
|
|
|
.name = TYPE_PNV_QUAD,
|
|
|
|
.parent = TYPE_DEVICE,
|
|
|
|
.instance_size = sizeof(PnvQuad),
|
|
|
|
.class_init = pnv_quad_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void pnv_core_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&pnv_quad_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(pnv_core_register_types)
|