2018-03-02 13:31:10 +01:00
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/*
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* QEMU RISC-V CPU
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef RISCV_CPU_H
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#define RISCV_CPU_H
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2019-07-09 17:20:52 +02:00
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#include "hw/core/cpu.h"
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2020-07-01 17:24:52 +02:00
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#include "hw/registerfields.h"
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2018-03-02 13:31:10 +01:00
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#include "exec/cpu-defs.h"
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2019-08-08 18:29:41 +02:00
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#include "fpu/softfloat-types.h"
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2020-09-03 22:43:22 +02:00
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#include "qom/object.h"
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2018-03-02 13:31:10 +01:00
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2019-03-22 19:51:19 +01:00
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#define TCG_GUEST_DEFAULT_MO 0
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2018-03-02 13:31:10 +01:00
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#define TYPE_RISCV_CPU "riscv-cpu"
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#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
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#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
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2018-02-07 11:40:25 +01:00
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#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
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2018-03-02 13:31:10 +01:00
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#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
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2019-04-20 04:24:09 +02:00
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#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
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#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
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2020-04-23 19:50:09 +02:00
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#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
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2021-04-01 20:14:54 +02:00
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#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
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2018-03-02 13:31:10 +01:00
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#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
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2020-03-13 20:34:29 +01:00
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#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
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2018-03-02 13:31:10 +01:00
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#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
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#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
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#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
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2020-12-16 19:22:29 +01:00
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#if defined(TARGET_RISCV32)
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# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
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#elif defined(TARGET_RISCV64)
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# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
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#endif
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2018-03-02 13:31:10 +01:00
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#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
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#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
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#define RV(x) ((target_ulong)1 << (x - 'A'))
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#define RVI RV('I')
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2018-03-05 01:28:00 +01:00
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#define RVE RV('E') /* E and I are mutually exclusive */
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2018-03-02 13:31:10 +01:00
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#define RVM RV('M')
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#define RVA RV('A')
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#define RVF RV('F')
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#define RVD RV('D')
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2020-07-01 17:24:49 +02:00
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#define RVV RV('V')
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2018-03-02 13:31:10 +01:00
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#define RVC RV('C')
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#define RVS RV('S')
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#define RVU RV('U')
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2020-02-01 02:01:41 +01:00
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#define RVH RV('H')
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2021-05-05 18:06:03 +02:00
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#define RVB RV('B')
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2018-03-02 13:31:10 +01:00
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/* S extension denotes that Supervisor mode exists, however it is possible
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to have a core that support S mode but does not have an MMU and there
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is currently no bit in misa to indicate whether an MMU exists or not
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2019-01-05 00:24:14 +01:00
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so a cpu features bitfield is required, likewise for optional PMP support */
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2018-03-02 13:31:10 +01:00
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enum {
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2019-01-05 00:24:14 +01:00
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RISCV_FEATURE_MMU,
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2019-01-15 00:59:00 +01:00
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RISCV_FEATURE_PMP,
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2021-04-19 08:16:44 +02:00
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RISCV_FEATURE_EPMP,
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2019-01-15 00:59:00 +01:00
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RISCV_FEATURE_MISA
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2018-03-02 13:31:10 +01:00
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};
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#define PRIV_VERSION_1_10_0 0x00011000
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2019-06-18 03:31:05 +02:00
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#define PRIV_VERSION_1_11_0 0x00011100
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2018-03-02 13:31:10 +01:00
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2021-05-05 18:06:18 +02:00
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#define BEXT_VERSION_0_93_0 0x00009300
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2020-07-01 17:24:50 +02:00
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#define VEXT_VERSION_0_07_1 0x00000701
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2020-10-14 12:17:28 +02:00
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enum {
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TRANSLATE_SUCCESS,
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TRANSLATE_FAIL,
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TRANSLATE_PMP_FAIL,
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TRANSLATE_G_STAGE_FAIL
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};
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2018-03-02 13:31:10 +01:00
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#define MMU_USER_IDX 3
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#define MAX_RISCV_PMPS (16)
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typedef struct CPURISCVState CPURISCVState;
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2021-05-16 22:53:33 +02:00
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#if !defined(CONFIG_USER_ONLY)
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2018-03-02 13:31:10 +01:00
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#include "pmp.h"
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2021-05-16 22:53:33 +02:00
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#endif
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2018-03-02 13:31:10 +01:00
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2020-07-01 17:25:49 +02:00
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#define RV_VLEN_MAX 256
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2020-07-01 17:24:49 +02:00
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2020-07-01 17:24:52 +02:00
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FIELD(VTYPE, VLMUL, 0, 2)
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FIELD(VTYPE, VSEW, 2, 3)
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FIELD(VTYPE, VEDIV, 5, 2)
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FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
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2020-07-10 12:48:18 +02:00
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FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
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2020-07-01 17:24:52 +02:00
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2018-03-02 13:31:10 +01:00
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struct CPURISCVState {
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target_ulong gpr[32];
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uint64_t fpr[32]; /* assume both F and D extensions */
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2020-07-01 17:24:49 +02:00
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/* vector coprocessor state. */
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uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
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target_ulong vxrm;
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target_ulong vxsat;
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target_ulong vl;
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target_ulong vstart;
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target_ulong vtype;
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2018-03-02 13:31:10 +01:00
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target_ulong pc;
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target_ulong load_res;
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target_ulong load_val;
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target_ulong frm;
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target_ulong badaddr;
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2020-02-01 02:02:56 +01:00
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target_ulong guest_phys_fault_addr;
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2018-03-02 13:31:10 +01:00
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target_ulong priv_ver;
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2021-05-05 18:06:18 +02:00
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target_ulong bext_ver;
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2020-07-01 17:24:50 +02:00
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target_ulong vext_ver;
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2018-03-02 13:31:10 +01:00
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target_ulong misa;
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2019-01-15 00:59:00 +01:00
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target_ulong misa_mask;
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2018-03-02 13:31:10 +01:00
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uint32_t features;
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2019-03-16 02:20:46 +01:00
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#ifdef CONFIG_USER_ONLY
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uint32_t elf_flags;
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#endif
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2018-03-02 13:31:10 +01:00
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#ifndef CONFIG_USER_ONLY
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target_ulong priv;
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2020-02-01 02:01:51 +01:00
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/* This contains QEMU specific information about the virt state. */
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target_ulong virt;
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2018-03-02 13:31:10 +01:00
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target_ulong resetvec;
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target_ulong mhartid;
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2020-10-26 12:55:25 +01:00
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/*
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* For RV32 this is 32-bit mstatus and 32-bit mstatush.
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* For RV64 this is a 64-bit mstatus.
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*/
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uint64_t mstatus;
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2018-04-08 23:25:25 +02:00
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2020-02-01 02:01:38 +01:00
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target_ulong mip;
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2020-02-01 02:02:12 +01:00
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2019-03-16 02:20:20 +01:00
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uint32_t miclaim;
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2018-04-08 23:25:25 +02:00
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2018-03-02 13:31:10 +01:00
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target_ulong mie;
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target_ulong mideleg;
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target_ulong satp; /* since: priv-1.10.0 */
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2021-03-19 20:45:29 +01:00
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target_ulong stval;
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2018-03-02 13:31:10 +01:00
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target_ulong medeleg;
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target_ulong stvec;
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target_ulong sepc;
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target_ulong scause;
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target_ulong mtvec;
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target_ulong mepc;
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target_ulong mcause;
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target_ulong mtval; /* since: priv-1.10.0 */
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2020-02-01 02:01:43 +01:00
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/* Hypervisor CSRs */
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target_ulong hstatus;
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target_ulong hedeleg;
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target_ulong hideleg;
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target_ulong hcounteren;
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target_ulong htval;
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target_ulong htinst;
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target_ulong hgatp;
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2020-02-02 14:42:16 +01:00
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uint64_t htimedelta;
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2020-02-01 02:01:43 +01:00
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/* Virtual CSRs */
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2020-10-26 12:55:25 +01:00
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/*
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* For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
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* For RV64 this is a 64-bit vsstatus.
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*/
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uint64_t vsstatus;
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2020-02-01 02:01:43 +01:00
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target_ulong vstvec;
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target_ulong vsscratch;
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target_ulong vsepc;
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target_ulong vscause;
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target_ulong vstval;
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target_ulong vsatp;
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target_ulong mtval2;
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target_ulong mtinst;
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2020-02-01 02:02:12 +01:00
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/* HS Backup CSRs */
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target_ulong stvec_hs;
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target_ulong sscratch_hs;
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target_ulong sepc_hs;
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target_ulong scause_hs;
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target_ulong stval_hs;
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target_ulong satp_hs;
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2020-10-26 12:55:25 +01:00
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uint64_t mstatus_hs;
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2020-02-01 02:02:12 +01:00
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2021-03-19 15:14:59 +01:00
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/* Signals whether the current exception occurred with two-stage address
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translation active. */
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bool two_stage_lookup;
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2018-04-09 01:33:05 +02:00
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target_ulong scounteren;
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target_ulong mcounteren;
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2018-03-02 13:31:10 +01:00
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target_ulong sscratch;
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target_ulong mscratch;
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/* temporary htif regs */
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uint64_t mfromhost;
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uint64_t mtohost;
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uint64_t timecmp;
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/* physical memory protection */
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pmp_table_t pmp_state;
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2021-04-19 08:16:53 +02:00
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target_ulong mseccfg;
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2019-03-15 11:26:58 +01:00
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2020-02-02 14:42:16 +01:00
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/* machine specific rdtime callback */
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2020-09-01 03:39:10 +02:00
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uint64_t (*rdtime_fn)(uint32_t);
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uint32_t rdtime_fn_arg;
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2020-02-02 14:42:16 +01:00
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2019-03-15 11:26:58 +01:00
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/* True if in debugger mode. */
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bool debugger;
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2018-03-02 13:31:10 +01:00
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#endif
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float_status fp_status;
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/* Fields from here on are preserved across CPU reset. */
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QEMUTimer *timer; /* Internal timer */
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};
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2020-08-31 23:07:37 +02:00
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OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
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qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros
One of the goals of having less boilerplate on QOM declarations
is to avoid human error. Requiring an extra argument that is
never used is an opportunity for mistakes.
Remove the unused argument from OBJECT_DECLARE_TYPE and
OBJECT_DECLARE_SIMPLE_TYPE.
Coccinelle patch used to convert all users of the macros:
@@
declarer name OBJECT_DECLARE_TYPE;
identifier InstanceType, ClassType, lowercase, UPPERCASE;
@@
OBJECT_DECLARE_TYPE(InstanceType, ClassType,
- lowercase,
UPPERCASE);
@@
declarer name OBJECT_DECLARE_SIMPLE_TYPE;
identifier InstanceType, lowercase, UPPERCASE;
@@
OBJECT_DECLARE_SIMPLE_TYPE(InstanceType,
- lowercase,
UPPERCASE);
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Paul Durrant <paul@xen.org>
Acked-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20200916182519.415636-4-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-16 20:25:17 +02:00
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RISCV_CPU)
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2018-03-02 13:31:10 +01:00
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/**
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* RISCVCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_reset: The parent class' reset handler.
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*
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* A RISCV CPU model.
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*/
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2020-09-03 22:43:22 +02:00
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struct RISCVCPUClass {
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2018-03-02 13:31:10 +01:00
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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cpu: Use DeviceClass reset instead of a special CPUClass reset
The CPUClass has a 'reset' method. This is a legacy from when
TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any
more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()'
function is kept as the API which most places use to reset a CPU; it
is now a wrapper which calls device_cold_reset() and then the
tracepoint function.
This change should not cause CPU objects to be reset more often
than they are at the moment, because:
* nobody is directly calling device_cold_reset() or
qdev_reset_all() on CPU objects
* no CPU object is on a qbus, so they will not be reset either
by somebody calling qbus_reset_all()/bus_cold_reset(), or
by the main "reset sysbus and everything in the qbus tree"
reset that most devices are reset by
Note that this does not change the need for each machine or whatever
to use qemu_register_reset() to arrange to call cpu_reset() -- that
is necessary because CPU objects are not on any qbus, so they don't
get reset when the qbus tree rooted at the sysbus bus is reset, and
this isn't being changed here.
All the changes to the files under target/ were made using the
included Coccinelle script, except:
(1) the deletion of the now-inaccurate and not terribly useful
"CPUClass::reset" comments was done with a perl one-liner afterwards:
perl -n -i -e '/ CPUClass::reset/ or print' target/*/*.c
(2) this bit of the s390 change was done by hand, because the
Coccinelle script is not sophisticated enough to handle the
parent_reset call being inside another function:
| @@ -96,8 +96,9 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type)
| S390CPU *cpu = S390_CPU(s);
| S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
| CPUS390XState *env = &cpu->env;
|+ DeviceState *dev = DEVICE(s);
|
|- scc->parent_reset(s);
|+ scc->parent_reset(dev);
| cpu->env.sigp_order = 0;
| s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu);
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20200303100511.5498-1-peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-03-03 11:05:11 +01:00
|
|
|
DeviceReset parent_reset;
|
2020-09-03 22:43:22 +02:00
|
|
|
};
|
2018-03-02 13:31:10 +01:00
|
|
|
|
|
|
|
/**
|
|
|
|
* RISCVCPU:
|
|
|
|
* @env: #CPURISCVState
|
|
|
|
*
|
|
|
|
* A RISCV CPU.
|
|
|
|
*/
|
2020-09-03 22:43:22 +02:00
|
|
|
struct RISCVCPU {
|
2018-03-02 13:31:10 +01:00
|
|
|
/*< private >*/
|
|
|
|
CPUState parent_obj;
|
|
|
|
/*< public >*/
|
2019-03-23 01:16:06 +01:00
|
|
|
CPUNegativeOffsetState neg;
|
2018-03-02 13:31:10 +01:00
|
|
|
CPURISCVState env;
|
2019-04-20 04:24:01 +02:00
|
|
|
|
2021-01-16 06:41:22 +01:00
|
|
|
char *dyn_csr_xml;
|
|
|
|
|
2019-04-20 04:24:01 +02:00
|
|
|
/* Configuration Settings */
|
|
|
|
struct {
|
2019-05-07 00:49:53 +02:00
|
|
|
bool ext_i;
|
|
|
|
bool ext_e;
|
|
|
|
bool ext_g;
|
|
|
|
bool ext_m;
|
|
|
|
bool ext_a;
|
|
|
|
bool ext_f;
|
|
|
|
bool ext_d;
|
|
|
|
bool ext_c;
|
2021-05-05 18:06:17 +02:00
|
|
|
bool ext_b;
|
2019-05-07 00:49:53 +02:00
|
|
|
bool ext_s;
|
|
|
|
bool ext_u;
|
2020-02-01 02:03:11 +01:00
|
|
|
bool ext_h;
|
2020-07-01 17:25:49 +02:00
|
|
|
bool ext_v;
|
2021-09-11 16:00:04 +02:00
|
|
|
bool ext_zba;
|
|
|
|
bool ext_zbb;
|
|
|
|
bool ext_zbc;
|
|
|
|
bool ext_zbs;
|
2019-06-18 03:31:22 +02:00
|
|
|
bool ext_counters;
|
2019-06-24 10:59:05 +02:00
|
|
|
bool ext_ifencei;
|
2019-06-24 10:59:51 +02:00
|
|
|
bool ext_icsr;
|
2019-05-07 00:49:53 +02:00
|
|
|
|
2019-04-20 04:24:01 +02:00
|
|
|
char *priv_spec;
|
|
|
|
char *user_spec;
|
2021-05-05 18:06:18 +02:00
|
|
|
char *bext_spec;
|
2020-07-01 17:25:49 +02:00
|
|
|
char *vext_spec;
|
2020-07-01 17:24:50 +02:00
|
|
|
uint16_t vlen;
|
|
|
|
uint16_t elen;
|
2019-04-20 04:24:01 +02:00
|
|
|
bool mmu;
|
|
|
|
bool pmp;
|
2021-04-19 08:17:25 +02:00
|
|
|
bool epmp;
|
2020-09-01 03:38:56 +02:00
|
|
|
uint64_t resetvec;
|
2019-04-20 04:24:01 +02:00
|
|
|
} cfg;
|
2020-09-03 22:43:22 +02:00
|
|
|
};
|
2018-03-02 13:31:10 +01:00
|
|
|
|
|
|
|
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
|
|
|
|
{
|
|
|
|
return (env->misa & ext) != 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool riscv_feature(CPURISCVState *env, int feature)
|
|
|
|
{
|
|
|
|
return env->features & (1ULL << feature);
|
|
|
|
}
|
|
|
|
|
|
|
|
#include "cpu_user.h"
|
|
|
|
#include "cpu_bits.h"
|
|
|
|
|
|
|
|
extern const char * const riscv_int_regnames[];
|
|
|
|
extern const char * const riscv_fpr_regnames[];
|
|
|
|
|
2020-08-14 05:58:19 +02:00
|
|
|
const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
|
2018-03-02 13:31:10 +01:00
|
|
|
void riscv_cpu_do_interrupt(CPUState *cpu);
|
2021-02-01 13:44:58 +01:00
|
|
|
int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
|
|
|
|
int cpuid, void *opaque);
|
|
|
|
int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
|
|
|
|
int cpuid, void *opaque);
|
2020-03-16 18:21:41 +01:00
|
|
|
int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
|
2018-03-02 13:31:10 +01:00
|
|
|
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
|
2019-07-31 01:35:24 +02:00
|
|
|
bool riscv_cpu_fp_enabled(CPURISCVState *env);
|
2020-02-01 02:01:51 +01:00
|
|
|
bool riscv_cpu_virt_enabled(CPURISCVState *env);
|
|
|
|
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
|
2020-02-01 02:01:54 +01:00
|
|
|
bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
|
|
|
|
void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);
|
2020-11-04 05:43:29 +01:00
|
|
|
bool riscv_cpu_two_stage_lookup(int mmu_idx);
|
2018-03-02 13:31:10 +01:00
|
|
|
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
|
|
|
|
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
|
|
|
|
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
|
|
|
|
MMUAccessType access_type, int mmu_idx,
|
2021-07-29 22:45:10 +02:00
|
|
|
uintptr_t retaddr) QEMU_NORETURN;
|
2019-04-02 12:12:38 +02:00
|
|
|
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
|
|
|
|
MMUAccessType access_type, int mmu_idx,
|
|
|
|
bool probe, uintptr_t retaddr);
|
2019-10-08 22:51:52 +02:00
|
|
|
void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
|
|
|
|
vaddr addr, unsigned size,
|
|
|
|
MMUAccessType access_type,
|
|
|
|
int mmu_idx, MemTxAttrs attrs,
|
|
|
|
MemTxResult response, uintptr_t retaddr);
|
2018-03-02 13:31:10 +01:00
|
|
|
char *riscv_isa_string(RISCVCPU *cpu);
|
2019-04-17 21:17:57 +02:00
|
|
|
void riscv_cpu_list(void);
|
2018-03-02 13:31:10 +01:00
|
|
|
|
|
|
|
#define cpu_list riscv_cpu_list
|
|
|
|
#define cpu_mmu_index riscv_cpu_mmu_index
|
|
|
|
|
2018-04-08 23:25:25 +02:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
2021-09-11 18:54:28 +02:00
|
|
|
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
|
2020-02-01 02:02:12 +01:00
|
|
|
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
|
2019-03-16 02:20:20 +01:00
|
|
|
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
|
2018-04-08 23:25:25 +02:00
|
|
|
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
|
|
|
|
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
|
2020-09-01 03:39:10 +02:00
|
|
|
void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
|
|
|
|
uint32_t arg);
|
2018-04-08 23:25:25 +02:00
|
|
|
#endif
|
2019-01-15 00:58:23 +01:00
|
|
|
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
|
2018-03-02 13:31:10 +01:00
|
|
|
|
|
|
|
void riscv_translate_init(void);
|
2019-01-15 00:58:23 +01:00
|
|
|
void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
|
|
|
|
uint32_t exception, uintptr_t pc);
|
2018-03-02 13:31:10 +01:00
|
|
|
|
2019-01-15 00:58:23 +01:00
|
|
|
target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
|
|
|
|
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
|
2018-03-02 13:31:10 +01:00
|
|
|
|
2020-11-04 05:43:23 +01:00
|
|
|
#define TB_FLAGS_MMU_MASK 7
|
|
|
|
#define TB_FLAGS_PRIV_MMU_MASK 3
|
|
|
|
#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
|
2019-01-15 00:57:50 +01:00
|
|
|
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
|
2018-03-02 13:31:10 +01:00
|
|
|
|
2020-07-01 17:24:52 +02:00
|
|
|
typedef CPURISCVState CPUArchState;
|
|
|
|
typedef RISCVCPU ArchCPU;
|
|
|
|
#include "exec/cpu-all.h"
|
|
|
|
|
|
|
|
FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
|
|
|
|
FIELD(TB_FLAGS, LMUL, 3, 2)
|
|
|
|
FIELD(TB_FLAGS, SEW, 5, 3)
|
|
|
|
FIELD(TB_FLAGS, VILL, 8, 1)
|
2020-11-04 05:43:31 +01:00
|
|
|
/* Is a Hypervisor instruction load/store allowed? */
|
|
|
|
FIELD(TB_FLAGS, HLSX, 9, 1)
|
2020-07-01 17:24:52 +02:00
|
|
|
|
2020-12-16 19:22:51 +01:00
|
|
|
bool riscv_cpu_is_32bit(CPURISCVState *env);
|
|
|
|
|
2020-07-01 17:24:52 +02:00
|
|
|
/*
|
|
|
|
* A simplification for VLMAX
|
|
|
|
* = (1 << LMUL) * VLEN / (8 * (1 << SEW))
|
|
|
|
* = (VLEN << LMUL) / (8 << SEW)
|
|
|
|
* = (VLEN << LMUL) >> (SEW + 3)
|
|
|
|
* = VLEN >> (SEW + 3 - LMUL)
|
|
|
|
*/
|
|
|
|
static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
|
|
|
|
{
|
|
|
|
uint8_t sew, lmul;
|
|
|
|
|
|
|
|
sew = FIELD_EX64(vtype, VTYPE, VSEW);
|
|
|
|
lmul = FIELD_EX64(vtype, VTYPE, VLMUL);
|
|
|
|
return cpu->cfg.vlen >> (sew + 3 - lmul);
|
|
|
|
}
|
|
|
|
|
2018-03-02 13:31:10 +01:00
|
|
|
static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
|
2020-07-01 17:24:52 +02:00
|
|
|
target_ulong *cs_base, uint32_t *pflags)
|
2018-03-02 13:31:10 +01:00
|
|
|
{
|
2020-07-01 17:24:52 +02:00
|
|
|
uint32_t flags = 0;
|
|
|
|
|
2018-03-02 13:31:10 +01:00
|
|
|
*pc = env->pc;
|
|
|
|
*cs_base = 0;
|
2020-07-01 17:24:52 +02:00
|
|
|
|
|
|
|
if (riscv_has_ext(env, RVV)) {
|
|
|
|
uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
|
|
|
|
bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
|
|
|
|
flags = FIELD_DP32(flags, TB_FLAGS, VILL,
|
|
|
|
FIELD_EX64(env->vtype, VTYPE, VILL));
|
|
|
|
flags = FIELD_DP32(flags, TB_FLAGS, SEW,
|
|
|
|
FIELD_EX64(env->vtype, VTYPE, VSEW));
|
|
|
|
flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
|
|
|
|
FIELD_EX64(env->vtype, VTYPE, VLMUL));
|
|
|
|
flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
|
|
|
|
} else {
|
|
|
|
flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
|
|
|
|
}
|
|
|
|
|
2018-03-02 13:31:10 +01:00
|
|
|
#ifdef CONFIG_USER_ONLY
|
2020-07-01 17:24:52 +02:00
|
|
|
flags |= TB_FLAGS_MSTATUS_FS;
|
2018-03-02 13:31:10 +01:00
|
|
|
#else
|
2020-07-01 17:24:52 +02:00
|
|
|
flags |= cpu_mmu_index(env, 0);
|
2020-02-01 02:02:41 +01:00
|
|
|
if (riscv_cpu_fp_enabled(env)) {
|
2020-07-01 17:24:52 +02:00
|
|
|
flags |= env->mstatus & MSTATUS_FS;
|
2020-02-01 02:02:41 +01:00
|
|
|
}
|
2020-11-04 05:43:31 +01:00
|
|
|
|
|
|
|
if (riscv_has_ext(env, RVH)) {
|
|
|
|
if (env->priv == PRV_M ||
|
|
|
|
(env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
|
|
|
|
(env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
|
|
|
|
get_field(env->hstatus, HSTATUS_HU))) {
|
|
|
|
flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
|
|
|
|
}
|
|
|
|
}
|
2018-03-02 13:31:10 +01:00
|
|
|
#endif
|
2020-11-04 05:43:31 +01:00
|
|
|
|
2020-07-01 17:24:52 +02:00
|
|
|
*pflags = flags;
|
2018-03-02 13:31:10 +01:00
|
|
|
}
|
|
|
|
|
2021-04-01 17:18:07 +02:00
|
|
|
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
|
|
|
|
target_ulong *ret_value,
|
|
|
|
target_ulong new_value, target_ulong write_mask);
|
|
|
|
RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
|
|
|
|
target_ulong *ret_value,
|
|
|
|
target_ulong new_value,
|
|
|
|
target_ulong write_mask);
|
2019-01-05 00:23:55 +01:00
|
|
|
|
2019-01-15 00:58:23 +01:00
|
|
|
static inline void riscv_csr_write(CPURISCVState *env, int csrno,
|
|
|
|
target_ulong val)
|
2019-01-05 00:23:55 +01:00
|
|
|
{
|
|
|
|
riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
|
|
|
|
}
|
|
|
|
|
2019-01-15 00:58:23 +01:00
|
|
|
static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
|
2019-01-05 00:23:55 +01:00
|
|
|
{
|
|
|
|
target_ulong val = 0;
|
|
|
|
riscv_csrrw(env, csrno, &val, 0, 0);
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2021-04-01 17:17:39 +02:00
|
|
|
typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
|
|
|
|
int csrno);
|
2021-04-01 17:17:57 +02:00
|
|
|
typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
|
|
|
|
target_ulong *ret_value);
|
|
|
|
typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
|
|
|
|
target_ulong new_value);
|
|
|
|
typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
|
|
|
|
target_ulong *ret_value,
|
|
|
|
target_ulong new_value,
|
|
|
|
target_ulong write_mask);
|
2019-01-05 00:23:55 +01:00
|
|
|
|
|
|
|
typedef struct {
|
2021-01-12 05:52:02 +01:00
|
|
|
const char *name;
|
2019-01-05 00:24:14 +01:00
|
|
|
riscv_csr_predicate_fn predicate;
|
2019-01-05 00:23:55 +01:00
|
|
|
riscv_csr_read_fn read;
|
|
|
|
riscv_csr_write_fn write;
|
|
|
|
riscv_csr_op_fn op;
|
|
|
|
} riscv_csr_operations;
|
|
|
|
|
2021-01-12 05:52:01 +01:00
|
|
|
/* CSR function table constants */
|
|
|
|
enum {
|
|
|
|
CSR_TABLE_SIZE = 0x1000
|
|
|
|
};
|
|
|
|
|
|
|
|
/* CSR function table */
|
2021-01-19 03:52:03 +01:00
|
|
|
extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
|
2021-01-12 05:52:01 +01:00
|
|
|
|
2019-01-05 00:23:55 +01:00
|
|
|
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
|
|
|
|
void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
|
2018-03-02 13:31:10 +01:00
|
|
|
|
2019-03-15 11:26:59 +01:00
|
|
|
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
|
|
|
|
|
2018-03-02 13:31:10 +01:00
|
|
|
#endif /* RISCV_CPU_H */
|