2007-06-30 19:32:17 +02:00
|
|
|
/*
|
|
|
|
* ARM AMBA PrimeCell PL031 RTC
|
|
|
|
*
|
|
|
|
* Copyright (c) 2007 CodeSourcery
|
|
|
|
*
|
|
|
|
* This file is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
|
|
* published by the Free Software Foundation.
|
|
|
|
*
|
2012-01-13 17:44:23 +01:00
|
|
|
* Contributions after 2012-01-13 are licensed under the terms of the
|
|
|
|
* GNU GPL, version 2 or (at your option) any later version.
|
2007-06-30 19:32:17 +02:00
|
|
|
*/
|
|
|
|
|
2016-01-26 19:17:05 +01:00
|
|
|
#include "qemu/osdep.h"
|
2019-05-23 16:35:08 +02:00
|
|
|
#include "qemu-common.h"
|
2019-02-21 19:17:46 +01:00
|
|
|
#include "hw/timer/pl031.h"
|
2019-08-12 07:23:42 +02:00
|
|
|
#include "hw/irq.h"
|
2013-02-04 15:40:22 +01:00
|
|
|
#include "hw/sysbus.h"
|
2012-12-17 18:20:00 +01:00
|
|
|
#include "qemu/timer.h"
|
2012-12-17 18:20:04 +01:00
|
|
|
#include "sysemu/sysemu.h"
|
2016-03-20 18:16:19 +01:00
|
|
|
#include "qemu/cutils.h"
|
2015-12-15 13:16:16 +01:00
|
|
|
#include "qemu/log.h"
|
2019-05-23 16:35:07 +02:00
|
|
|
#include "qemu/module.h"
|
2019-02-21 19:17:46 +01:00
|
|
|
#include "trace.h"
|
2007-06-30 19:32:17 +02:00
|
|
|
|
|
|
|
#define RTC_DR 0x00 /* Data read register */
|
|
|
|
#define RTC_MR 0x04 /* Match register */
|
|
|
|
#define RTC_LR 0x08 /* Data load register */
|
|
|
|
#define RTC_CR 0x0c /* Control register */
|
|
|
|
#define RTC_IMSC 0x10 /* Interrupt mask and set register */
|
|
|
|
#define RTC_RIS 0x14 /* Raw interrupt status register */
|
|
|
|
#define RTC_MIS 0x18 /* Masked interrupt status register */
|
|
|
|
#define RTC_ICR 0x1c /* Interrupt clear register */
|
|
|
|
|
|
|
|
static const unsigned char pl031_id[] = {
|
|
|
|
0x31, 0x10, 0x14, 0x00, /* Device ID */
|
|
|
|
0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */
|
|
|
|
};
|
|
|
|
|
2013-07-27 15:07:44 +02:00
|
|
|
static void pl031_update(PL031State *s)
|
2007-06-30 19:32:17 +02:00
|
|
|
{
|
2019-02-21 19:17:46 +01:00
|
|
|
uint32_t flags = s->is & s->im;
|
|
|
|
|
|
|
|
trace_pl031_irq_state(flags);
|
|
|
|
qemu_set_irq(s->irq, flags);
|
2007-06-30 19:32:17 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void pl031_interrupt(void * opaque)
|
|
|
|
{
|
2013-07-27 15:07:44 +02:00
|
|
|
PL031State *s = (PL031State *)opaque;
|
2007-06-30 19:32:17 +02:00
|
|
|
|
2012-02-16 10:56:10 +01:00
|
|
|
s->is = 1;
|
2019-02-21 19:17:46 +01:00
|
|
|
trace_pl031_alarm_raised();
|
2007-06-30 19:32:17 +02:00
|
|
|
pl031_update(s);
|
|
|
|
}
|
|
|
|
|
2013-07-27 15:07:44 +02:00
|
|
|
static uint32_t pl031_get_count(PL031State *s)
|
2007-06-30 19:32:17 +02:00
|
|
|
{
|
2013-08-21 17:03:04 +02:00
|
|
|
int64_t now = qemu_clock_get_ns(rtc_clock);
|
2016-03-21 17:02:30 +01:00
|
|
|
return s->tick_offset + now / NANOSECONDS_PER_SECOND;
|
2007-06-30 19:32:17 +02:00
|
|
|
}
|
|
|
|
|
2013-07-27 15:07:44 +02:00
|
|
|
static void pl031_set_alarm(PL031State *s)
|
2007-06-30 19:32:17 +02:00
|
|
|
{
|
|
|
|
uint32_t ticks;
|
|
|
|
|
|
|
|
/* The timer wraps around. This subtraction also wraps in the same way,
|
|
|
|
and gives correct results when alarm < now_ticks. */
|
2012-03-30 12:31:23 +02:00
|
|
|
ticks = s->mr - pl031_get_count(s);
|
2019-02-21 19:17:46 +01:00
|
|
|
trace_pl031_set_alarm(ticks);
|
2007-06-30 19:32:17 +02:00
|
|
|
if (ticks == 0) {
|
2013-08-21 17:03:08 +02:00
|
|
|
timer_del(s->timer);
|
2007-06-30 19:32:17 +02:00
|
|
|
pl031_interrupt(s);
|
|
|
|
} else {
|
2013-08-21 17:03:04 +02:00
|
|
|
int64_t now = qemu_clock_get_ns(rtc_clock);
|
2016-03-21 17:02:30 +01:00
|
|
|
timer_mod(s->timer, now + (int64_t)ticks * NANOSECONDS_PER_SECOND);
|
2007-06-30 19:32:17 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint64_t pl031_read(void *opaque, hwaddr offset,
|
2011-10-10 17:18:44 +02:00
|
|
|
unsigned size)
|
2007-06-30 19:32:17 +02:00
|
|
|
{
|
2013-07-27 15:07:44 +02:00
|
|
|
PL031State *s = (PL031State *)opaque;
|
2019-02-21 19:17:46 +01:00
|
|
|
uint64_t r;
|
2007-06-30 19:32:17 +02:00
|
|
|
|
|
|
|
switch (offset) {
|
|
|
|
case RTC_DR:
|
2019-02-21 19:17:46 +01:00
|
|
|
r = pl031_get_count(s);
|
|
|
|
break;
|
2007-06-30 19:32:17 +02:00
|
|
|
case RTC_MR:
|
2019-02-21 19:17:46 +01:00
|
|
|
r = s->mr;
|
|
|
|
break;
|
2007-06-30 19:32:17 +02:00
|
|
|
case RTC_IMSC:
|
2019-02-21 19:17:46 +01:00
|
|
|
r = s->im;
|
|
|
|
break;
|
2007-06-30 19:32:17 +02:00
|
|
|
case RTC_RIS:
|
2019-02-21 19:17:46 +01:00
|
|
|
r = s->is;
|
|
|
|
break;
|
2007-06-30 19:32:17 +02:00
|
|
|
case RTC_LR:
|
2019-02-21 19:17:46 +01:00
|
|
|
r = s->lr;
|
|
|
|
break;
|
2007-06-30 19:32:17 +02:00
|
|
|
case RTC_CR:
|
|
|
|
/* RTC is permanently enabled. */
|
2019-02-21 19:17:46 +01:00
|
|
|
r = 1;
|
|
|
|
break;
|
2007-06-30 19:32:17 +02:00
|
|
|
case RTC_MIS:
|
2019-02-21 19:17:46 +01:00
|
|
|
r = s->is & s->im;
|
|
|
|
break;
|
|
|
|
case 0xfe0 ... 0xfff:
|
|
|
|
r = pl031_id[(offset - 0xfe0) >> 2];
|
|
|
|
break;
|
2007-06-30 19:32:17 +02:00
|
|
|
case RTC_ICR:
|
2012-10-18 15:11:42 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"pl031: read of write-only register at offset 0x%x\n",
|
|
|
|
(int)offset);
|
2019-02-21 19:17:46 +01:00
|
|
|
r = 0;
|
2007-06-30 19:32:17 +02:00
|
|
|
break;
|
|
|
|
default:
|
2012-10-18 15:11:42 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"pl031_read: Bad offset 0x%x\n", (int)offset);
|
2019-02-21 19:17:46 +01:00
|
|
|
r = 0;
|
2007-06-30 19:32:17 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2019-02-21 19:17:46 +01:00
|
|
|
trace_pl031_read(offset, r);
|
|
|
|
return r;
|
2007-06-30 19:32:17 +02:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void pl031_write(void * opaque, hwaddr offset,
|
2011-10-10 17:18:44 +02:00
|
|
|
uint64_t value, unsigned size)
|
2007-06-30 19:32:17 +02:00
|
|
|
{
|
2013-07-27 15:07:44 +02:00
|
|
|
PL031State *s = (PL031State *)opaque;
|
2007-06-30 19:32:17 +02:00
|
|
|
|
2019-02-21 19:17:46 +01:00
|
|
|
trace_pl031_write(offset, value);
|
2007-06-30 19:32:17 +02:00
|
|
|
|
|
|
|
switch (offset) {
|
|
|
|
case RTC_LR:
|
|
|
|
s->tick_offset += value - pl031_get_count(s);
|
|
|
|
pl031_set_alarm(s);
|
|
|
|
break;
|
|
|
|
case RTC_MR:
|
|
|
|
s->mr = value;
|
|
|
|
pl031_set_alarm(s);
|
|
|
|
break;
|
|
|
|
case RTC_IMSC:
|
|
|
|
s->im = value & 1;
|
|
|
|
pl031_update(s);
|
|
|
|
break;
|
|
|
|
case RTC_ICR:
|
2011-04-28 17:20:35 +02:00
|
|
|
/* The PL031 documentation (DDI0224B) states that the interrupt is
|
2007-06-30 19:32:17 +02:00
|
|
|
cleared when bit 0 of the written value is set. However the
|
|
|
|
arm926e documentation (DDI0287B) states that the interrupt is
|
|
|
|
cleared when any value is written. */
|
|
|
|
s->is = 0;
|
|
|
|
pl031_update(s);
|
|
|
|
break;
|
|
|
|
case RTC_CR:
|
|
|
|
/* Written value is ignored. */
|
|
|
|
break;
|
|
|
|
|
|
|
|
case RTC_DR:
|
|
|
|
case RTC_MIS:
|
|
|
|
case RTC_RIS:
|
2012-10-18 15:11:42 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"pl031: write to read-only register at offset 0x%x\n",
|
|
|
|
(int)offset);
|
2007-06-30 19:32:17 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2012-10-18 15:11:42 +02:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"pl031_write: Bad offset 0x%x\n", (int)offset);
|
2007-06-30 19:32:17 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-10-10 17:18:44 +02:00
|
|
|
static const MemoryRegionOps pl031_ops = {
|
|
|
|
.read = pl031_read,
|
|
|
|
.write = pl031_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2007-06-30 19:32:17 +02:00
|
|
|
};
|
|
|
|
|
2016-02-18 15:16:21 +01:00
|
|
|
static void pl031_init(Object *obj)
|
2007-06-30 19:32:17 +02:00
|
|
|
{
|
2016-02-18 15:16:21 +01:00
|
|
|
PL031State *s = PL031(obj);
|
|
|
|
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
|
2008-02-17 12:42:19 +01:00
|
|
|
struct tm tm;
|
2007-06-30 19:32:17 +02:00
|
|
|
|
2016-02-18 15:16:21 +01:00
|
|
|
memory_region_init_io(&s->iomem, obj, &pl031_ops, s, "pl031", 0x1000);
|
2011-11-27 10:38:10 +01:00
|
|
|
sysbus_init_mmio(dev, &s->iomem);
|
2007-06-30 19:32:17 +02:00
|
|
|
|
2009-05-14 23:35:07 +02:00
|
|
|
sysbus_init_irq(dev, &s->irq);
|
2008-02-17 12:42:19 +01:00
|
|
|
qemu_get_timedate(&tm, 0);
|
2013-08-21 17:03:04 +02:00
|
|
|
s->tick_offset = mktimegm(&tm) -
|
2016-03-21 17:02:30 +01:00
|
|
|
qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
|
2007-06-30 19:32:17 +02:00
|
|
|
|
2013-08-21 17:03:04 +02:00
|
|
|
s->timer = timer_new_ns(rtc_clock, pl031_interrupt, s);
|
2007-06-30 19:32:17 +02:00
|
|
|
}
|
2009-05-14 23:35:07 +02:00
|
|
|
|
2017-09-25 13:29:12 +02:00
|
|
|
static int pl031_pre_save(void *opaque)
|
2012-03-30 12:31:23 +02:00
|
|
|
{
|
2013-07-27 15:07:44 +02:00
|
|
|
PL031State *s = opaque;
|
2012-03-30 12:31:23 +02:00
|
|
|
|
2019-07-15 15:17:04 +02:00
|
|
|
/*
|
|
|
|
* The PL031 device model code uses the tick_offset field, which is
|
|
|
|
* the offset between what the guest RTC should read and what the
|
|
|
|
* QEMU rtc_clock reads:
|
|
|
|
* guest_rtc = rtc_clock + tick_offset
|
|
|
|
* and so
|
|
|
|
* tick_offset = guest_rtc - rtc_clock
|
|
|
|
*
|
|
|
|
* We want to migrate this offset, which sounds straightforward.
|
|
|
|
* Unfortunately older versions of QEMU migrated a conversion of this
|
|
|
|
* offset into an offset from the vm_clock. (This was in turn an
|
|
|
|
* attempt to be compatible with even older QEMU versions, but it
|
|
|
|
* has incorrect behaviour if the rtc_clock is not the same as the
|
|
|
|
* vm_clock.) So we put the actual tick_offset into a migration
|
|
|
|
* subsection, and the backwards-compatible time-relative-to-vm_clock
|
|
|
|
* in the main migration state.
|
|
|
|
*
|
|
|
|
* Calculate base time relative to QEMU_CLOCK_VIRTUAL:
|
|
|
|
*/
|
2013-08-21 17:03:08 +02:00
|
|
|
int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
|
2016-03-21 17:02:30 +01:00
|
|
|
s->tick_offset_vmstate = s->tick_offset + delta / NANOSECONDS_PER_SECOND;
|
2017-09-25 13:29:12 +02:00
|
|
|
|
|
|
|
return 0;
|
2012-03-30 12:31:23 +02:00
|
|
|
}
|
|
|
|
|
2019-07-15 15:17:04 +02:00
|
|
|
static int pl031_pre_load(void *opaque)
|
|
|
|
{
|
|
|
|
PL031State *s = opaque;
|
|
|
|
|
|
|
|
s->tick_offset_migrated = false;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-03-30 12:31:22 +02:00
|
|
|
static int pl031_post_load(void *opaque, int version_id)
|
|
|
|
{
|
2013-07-27 15:07:44 +02:00
|
|
|
PL031State *s = opaque;
|
2012-03-30 12:31:22 +02:00
|
|
|
|
2019-07-15 15:17:04 +02:00
|
|
|
/*
|
|
|
|
* If we got the tick_offset subsection, then we can just use
|
|
|
|
* the value in that. Otherwise the source is an older QEMU and
|
|
|
|
* has given us the offset from the vm_clock; convert it back to
|
|
|
|
* an offset from the rtc_clock. This will cause time to incorrectly
|
|
|
|
* go backwards compared to the host RTC, but this is unavoidable.
|
|
|
|
*/
|
|
|
|
|
|
|
|
if (!s->tick_offset_migrated) {
|
|
|
|
int64_t delta = qemu_clock_get_ns(rtc_clock) -
|
|
|
|
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
|
|
|
|
s->tick_offset = s->tick_offset_vmstate -
|
|
|
|
delta / NANOSECONDS_PER_SECOND;
|
|
|
|
}
|
2012-03-30 12:31:22 +02:00
|
|
|
pl031_set_alarm(s);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-07-15 15:17:04 +02:00
|
|
|
static int pl031_tick_offset_post_load(void *opaque, int version_id)
|
|
|
|
{
|
|
|
|
PL031State *s = opaque;
|
|
|
|
|
|
|
|
s->tick_offset_migrated = true;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool pl031_tick_offset_needed(void *opaque)
|
|
|
|
{
|
|
|
|
PL031State *s = opaque;
|
|
|
|
|
|
|
|
return s->migrate_tick_offset;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const VMStateDescription vmstate_pl031_tick_offset = {
|
|
|
|
.name = "pl031/tick-offset",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
|
|
|
.needed = pl031_tick_offset_needed,
|
|
|
|
.post_load = pl031_tick_offset_post_load,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_UINT32(tick_offset, PL031State),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2012-03-30 12:31:22 +02:00
|
|
|
static const VMStateDescription vmstate_pl031 = {
|
|
|
|
.name = "pl031",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
2012-03-30 12:31:23 +02:00
|
|
|
.pre_save = pl031_pre_save,
|
2019-07-15 15:17:04 +02:00
|
|
|
.pre_load = pl031_pre_load,
|
2012-03-30 12:31:22 +02:00
|
|
|
.post_load = pl031_post_load,
|
|
|
|
.fields = (VMStateField[]) {
|
2013-07-27 15:07:44 +02:00
|
|
|
VMSTATE_UINT32(tick_offset_vmstate, PL031State),
|
|
|
|
VMSTATE_UINT32(mr, PL031State),
|
|
|
|
VMSTATE_UINT32(lr, PL031State),
|
|
|
|
VMSTATE_UINT32(cr, PL031State),
|
|
|
|
VMSTATE_UINT32(im, PL031State),
|
|
|
|
VMSTATE_UINT32(is, PL031State),
|
2012-03-30 12:31:22 +02:00
|
|
|
VMSTATE_END_OF_LIST()
|
2019-07-15 15:17:04 +02:00
|
|
|
},
|
|
|
|
.subsections = (const VMStateDescription*[]) {
|
|
|
|
&vmstate_pl031_tick_offset,
|
|
|
|
NULL
|
2012-03-30 12:31:22 +02:00
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2019-07-15 15:17:04 +02:00
|
|
|
static Property pl031_properties[] = {
|
|
|
|
/*
|
|
|
|
* True to correctly migrate the tick offset of the RTC. False to
|
|
|
|
* obtain backward migration compatibility with older QEMU versions,
|
|
|
|
* at the expense of the guest RTC going backwards compared with the
|
|
|
|
* host RTC when the VM is saved/restored if using -rtc host.
|
|
|
|
* (Even if set to 'true' older QEMU can migrate forward to newer QEMU;
|
|
|
|
* 'false' also permits newer QEMU to migrate to older QEMU.)
|
|
|
|
*/
|
|
|
|
DEFINE_PROP_BOOL("migrate-tick-offset",
|
|
|
|
PL031State, migrate_tick_offset, true),
|
|
|
|
DEFINE_PROP_END_OF_LIST()
|
|
|
|
};
|
|
|
|
|
2012-01-24 20:12:29 +01:00
|
|
|
static void pl031_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-24 20:12:29 +01:00
|
|
|
|
2011-12-08 04:34:16 +01:00
|
|
|
dc->vmsd = &vmstate_pl031;
|
2019-07-15 15:17:04 +02:00
|
|
|
dc->props = pl031_properties;
|
2012-01-24 20:12:29 +01:00
|
|
|
}
|
|
|
|
|
2013-01-10 16:19:07 +01:00
|
|
|
static const TypeInfo pl031_info = {
|
2013-07-27 15:10:14 +02:00
|
|
|
.name = TYPE_PL031,
|
2011-12-08 04:34:16 +01:00
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
2013-07-27 15:07:44 +02:00
|
|
|
.instance_size = sizeof(PL031State),
|
2016-02-18 15:16:21 +01:00
|
|
|
.instance_init = pl031_init,
|
2011-12-08 04:34:16 +01:00
|
|
|
.class_init = pl031_class_init,
|
2010-12-23 18:19:55 +01:00
|
|
|
};
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
static void pl031_register_types(void)
|
2009-05-14 23:35:07 +02:00
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
type_register_static(&pl031_info);
|
2009-05-14 23:35:07 +02:00
|
|
|
}
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
type_init(pl031_register_types)
|