2012-11-14 21:54:07 +01:00
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/*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* QEMU i82801b11 dmi-to-pci Bridge Emulation
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*
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* Copyright (c) 2009, 2010, 2011
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* Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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* Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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2016-01-26 19:17:15 +01:00
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#include "qemu/osdep.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/pci/pci.h"
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2019-08-12 07:23:45 +02:00
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#include "migration/vmstate.h"
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2019-05-23 16:35:07 +02:00
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#include "qemu/module.h"
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2013-02-05 17:06:20 +01:00
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#include "hw/i386/ich9.h"
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2012-11-14 21:54:07 +01:00
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/*****************************************************************************/
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/* ICH9 DMI-to-PCI bridge */
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#define I82801ba_SSVID_OFFSET 0x50
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#define I82801ba_SSVID_SVID 0
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#define I82801ba_SSVID_SSID 0
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typedef struct I82801b11Bridge {
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2013-07-12 19:21:22 +02:00
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/*< private >*/
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PCIBridge parent_obj;
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/*< public >*/
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2012-11-14 21:54:07 +01:00
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} I82801b11Bridge;
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2017-06-27 08:16:52 +02:00
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static void i82801b11_bridge_realize(PCIDevice *d, Error **errp)
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2012-11-14 21:54:07 +01:00
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{
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int rc;
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2016-01-15 03:23:32 +01:00
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pci_bridge_initfn(d, TYPE_PCI_BUS);
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2012-11-14 21:54:07 +01:00
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rc = pci_bridge_ssvid_init(d, I82801ba_SSVID_OFFSET,
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2017-06-27 08:16:52 +02:00
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I82801ba_SSVID_SVID, I82801ba_SSVID_SSID,
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errp);
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2012-11-14 21:54:07 +01:00
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if (rc < 0) {
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goto err_bridge;
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}
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2013-07-09 19:36:05 +02:00
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pci_config_set_prog_interface(d->config, PCI_CLASS_BRIDGE_PCI_INF_SUB);
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2017-06-27 08:16:52 +02:00
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return;
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2012-11-14 21:54:07 +01:00
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err_bridge:
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pci_bridge_exitfn(d);
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}
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2016-04-04 17:54:41 +02:00
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static const VMStateDescription i82801b11_bridge_dev_vmstate = {
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.name = "i82801b11_bridge",
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pci/bus: let it has higher migration priority
In the past, we prioritized IOMMU migration so that we have such a
priority order:
IOMMU > PCI Devices
When migrating a guest with both vIOMMU and a pcie-root-port, we'll
always migrate vIOMMU first, since pci buses will be seen to have the
same priority of general PCI devices.
That's problematic.
The thing is that PCI bus number information is stored in the root port,
and that is needed by vIOMMU during post_load(), e.g., to figure out
context entry for a device. If we don't have correct bus numbers for
devices, we won't be able to recover device state of the DMAR memory
regions, and things will be messed up.
So let's boost the PCIe root ports to be even with higher priority:
PCIe Root Port > IOMMU > PCI Devices
A smoke test shows that this patch fixes bug 1538953.
Also, apply this rule to all the PCI bus/bridge devices: ioh3420,
xio3130_downstream, xio3130_upstream, pcie_pci_bridge, pci-pci bridge,
i82801b11.
I noted that we set pcie_pci_bridge_dev_vmstate twice. Clean that up
together.
CC: Alex Williamson <alex.williamson@redhat.com>
CC: Marcel Apfelbaum <marcel@redhat.com>
CC: Michael S. Tsirkin <mst@redhat.com>
CC: Dr. David Alan Gilbert <dgilbert@redhat.com>
CC: Juan Quintela <quintela@redhat.com>
CC: Laurent Vivier <lvivier@redhat.com>
Bug: https://bugzilla.redhat.com/show_bug.cgi?id=1538953
Reported-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Signed-off-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-02-06 08:39:33 +01:00
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.priority = MIG_PRI_PCI_BUS,
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2016-04-04 17:54:41 +02:00
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
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VMSTATE_END_OF_LIST()
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}
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};
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2012-11-14 21:54:07 +01:00
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static void i82801b11_bridge_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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2013-07-29 16:17:45 +02:00
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DeviceClass *dc = DEVICE_CLASS(klass);
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2012-11-14 21:54:07 +01:00
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2019-05-13 08:19:38 +02:00
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k->is_bridge = true;
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2012-11-14 21:54:07 +01:00
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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k->device_id = PCI_DEVICE_ID_INTEL_82801BA_11;
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k->revision = ICH9_D2P_A2_REVISION;
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2017-06-27 08:16:52 +02:00
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k->realize = i82801b11_bridge_realize;
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2013-08-05 16:36:40 +02:00
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k->config_write = pci_bridge_write_config;
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2016-04-04 17:54:41 +02:00
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dc->vmsd = &i82801b11_bridge_dev_vmstate;
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pci-bridge/i82801b11: clear bridge registers on platform reset
The "i82801b11-bridge" device model is a descendant of "base-pci-bridge"
(TYPE_PCI_BRIDGE). However, unlike other similar devices, such as
- pci-bridge,
- pcie-pci-bridge,
- PCIE Root Port,
- xio3130 switch upstream and downstream ports,
- dec-21154-p2p-bridge,
- pbm-bridge,
- xilinx-pcie-root,
"i82801b11-bridge" does not clear the bridge specific registers at
platform reset.
This is a problem because devices on "i82801b11-bridge" continue to
respond to config space cycles after platform reset, when addressed with
the bus number that was previously programmed into the secondary bus
number register of "i82801b11-bridge". This error breaks OVMF's search for
extra (PXB) root buses, for example.
The device class reset method for "i82801b11-bridge" is currently NULL;
set it directly to pci_bridge_reset(), like the last three bridge models
in the above listing do.
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Marcel Apfelbaum <marcel@redhat.com>
Cc: qemu-stable@nongnu.org
Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1541839
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-02-07 13:10:27 +01:00
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dc->reset = pci_bridge_reset;
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2013-07-29 16:17:45 +02:00
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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2012-11-14 21:54:07 +01:00
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}
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static const TypeInfo i82801b11_bridge_info = {
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.name = "i82801b11-bridge",
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2013-07-11 17:13:43 +02:00
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.parent = TYPE_PCI_BRIDGE,
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2012-11-14 21:54:07 +01:00
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.instance_size = sizeof(I82801b11Bridge),
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.class_init = i82801b11_bridge_class_init,
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2017-09-27 21:56:34 +02:00
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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2012-11-14 21:54:07 +01:00
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};
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static void d2pbr_register(void)
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{
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type_register_static(&i82801b11_bridge_info);
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}
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type_init(d2pbr_register);
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