2007-10-25 23:35:50 +02:00
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/*
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* PowerPC emulation special registers manipulation helpers for qemu.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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2009-07-16 22:47:01 +02:00
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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2007-10-25 23:35:50 +02:00
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*/
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#if !defined(__HELPER_REGS_H__)
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#define __HELPER_REGS_H__
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/* Swap temporary saved registers with GPRs */
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2009-08-16 11:06:54 +02:00
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static inline void hreg_swap_gpr_tgpr(CPUPPCState *env)
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2007-10-25 23:35:50 +02:00
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{
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2008-09-04 07:26:09 +02:00
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target_ulong tmp;
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2007-10-25 23:35:50 +02:00
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tmp = env->gpr[0];
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env->gpr[0] = env->tgpr[0];
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env->tgpr[0] = tmp;
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tmp = env->gpr[1];
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env->gpr[1] = env->tgpr[1];
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env->tgpr[1] = tmp;
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tmp = env->gpr[2];
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env->gpr[2] = env->tgpr[2];
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env->tgpr[2] = tmp;
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tmp = env->gpr[3];
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env->gpr[3] = env->tgpr[3];
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env->tgpr[3] = tmp;
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}
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2009-08-16 11:06:54 +02:00
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static inline void hreg_compute_mem_idx(CPUPPCState *env)
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2007-11-04 03:55:33 +01:00
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{
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2016-05-03 18:03:24 +02:00
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/* This is our encoding for server processors
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*
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* 0 = Guest User space virtual mode
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* 1 = Guest Kernel space virtual mode
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* 2 = Guest Kernel space real mode
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* 3 = HV User space virtual mode
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* 4 = HV Kernel space virtual mode
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* 5 = HV Kernel space real mode
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*
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* The combination PR=1 IR&DR=0 is invalid, we will treat
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* it as IR=DR=1
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*
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* For BookE, we need 8 MMU modes as follow:
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*
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* 0 = AS 0 HV User space
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* 1 = AS 0 HV Kernel space
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* 2 = AS 1 HV User space
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* 3 = AS 1 HV Kernel space
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* 4 = AS 0 Guest User space
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* 5 = AS 0 Guest Kernel space
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* 6 = AS 1 Guest User space
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* 7 = AS 1 Guest Kernel space
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*/
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if (env->mmu_model & POWERPC_MMU_BOOKE) {
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env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1;
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env->immu_idx += msr_is ? 2 : 0;
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env->dmmu_idx += msr_ds ? 2 : 0;
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env->immu_idx += msr_gs ? 4 : 0;
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env->dmmu_idx += msr_gs ? 4 : 0;
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2007-11-17 22:14:09 +01:00
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} else {
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2016-05-03 18:03:24 +02:00
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/* First calucalte a base value independent of HV */
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if (msr_pr != 0) {
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/* User space, ignore IR and DR */
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env->immu_idx = env->dmmu_idx = 0;
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} else {
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/* Kernel, setup a base I/D value */
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env->immu_idx = msr_ir ? 1 : 2;
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env->dmmu_idx = msr_dr ? 1 : 2;
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}
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/* Then offset it for HV */
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if (msr_hv) {
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env->immu_idx += 3;
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env->dmmu_idx += 3;
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}
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2007-11-17 22:14:09 +01:00
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}
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2007-11-04 03:55:33 +01:00
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}
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2009-08-16 11:06:54 +02:00
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static inline void hreg_compute_hflags(CPUPPCState *env)
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2007-10-25 23:35:50 +02:00
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{
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target_ulong hflags_mask;
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/* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */
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hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) |
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(1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |
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2013-12-18 09:21:02 +01:00
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(1 << MSR_LE) | (1 << MSR_VSX);
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2007-11-17 22:14:09 +01:00
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hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB;
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2007-11-04 03:55:33 +01:00
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hreg_compute_mem_idx(env);
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2007-10-25 23:35:50 +02:00
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env->hflags = env->msr & hflags_mask;
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2007-11-04 03:55:33 +01:00
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/* Merge with hflags coming from other registers */
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env->hflags |= env->hflags_nmsr;
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2007-10-25 23:35:50 +02:00
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}
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2009-08-16 11:06:54 +02:00
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static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
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int alter_hv)
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2007-10-25 23:35:50 +02:00
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{
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2007-10-26 01:14:50 +02:00
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int excp;
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2013-01-17 18:51:17 +01:00
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#if !defined(CONFIG_USER_ONLY)
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CPUState *cs = CPU(ppc_env_get_cpu(env));
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#endif
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2007-10-25 23:35:50 +02:00
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excp = 0;
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value &= env->msr_mask;
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2013-01-17 18:51:17 +01:00
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#if !defined(CONFIG_USER_ONLY)
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2007-11-17 22:14:09 +01:00
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if (!alter_hv) {
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/* mtmsr cannot alter the hypervisor state */
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value &= ~MSR_HVB;
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value |= env->msr & MSR_HVB;
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}
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2007-10-25 23:35:50 +02:00
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if (((value >> MSR_IR) & 1) != msr_ir ||
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((value >> MSR_DR) & 1) != msr_dr) {
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2016-05-03 18:03:24 +02:00
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cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
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}
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if ((env->mmu_model & POWERPC_MMU_BOOKE) &&
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((value >> MSR_GS) & 1) != msr_gs) {
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2013-01-17 18:51:17 +01:00
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cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
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2007-10-25 23:35:50 +02:00
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}
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if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
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((value ^ env->msr) & (1 << MSR_TGPR)))) {
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/* Swap temporary saved registers with GPRs */
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hreg_swap_gpr_tgpr(env);
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}
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if (unlikely((value >> MSR_EP) & 1) != msr_ep) {
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/* Change the exception prefix on PowerPC 601 */
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env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000;
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}
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#endif
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env->msr = value;
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hreg_compute_hflags(env);
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2013-01-17 18:51:17 +01:00
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#if !defined(CONFIG_USER_ONLY)
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2007-10-25 23:35:50 +02:00
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if (unlikely(msr_pow == 1)) {
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2014-04-06 22:40:47 +02:00
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if (!env->pending_interrupts && (*env->check_pow)(env)) {
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2013-01-17 18:51:17 +01:00
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cs->halted = 1;
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2007-10-25 23:35:50 +02:00
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excp = EXCP_HALTED;
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}
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}
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#endif
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return excp;
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}
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ppc: Do some batching of TCG tlb flushes
On ppc64 especially, we flush the tlb on any slbie or tlbie instruction.
However, those instructions often come in bursts of 3 or more (context
switch will favor a series of slbie's for example to an slbia if the
SLB has less than a certain number of entries in it, and tlbie's can
happen in a series, with PAPR, H_BULK_REMOVE can remove up to 4 entries
at a time.
Doing a tlb_flush() each time is a waste of time. We end up doing a memset
of the whole TLB, reloading it for the next instruction, memset'ing again,
etc...
Those instructions don't have to take effect immediately. For slbie, they
can wait for the next context synchronizing event. For tlbie, the next
tlbsync.
This implements batching by keeping a flag that indicates that we have a
TLB in need of flushing. We check it on interrupts, rfi's, isync's and
tlbsync and flush the TLB if needed.
This reduces the number of tlb_flush() on a boot to a ubuntu installer
first dialog screen from roughly 360K down to 36K.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: added a 'CPUPPCState *' variable in h_remove() and
h_bulk_remove() ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[dwg: removed spurious whitespace change, use 0/1 not true/false
consistently, since tlb_need_flush has int type]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-05-03 18:03:25 +02:00
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#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
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static inline void check_tlb_flush(CPUPPCState *env)
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{
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CPUState *cs = CPU(ppc_env_get_cpu(env));
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if (env->tlb_need_flush) {
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env->tlb_need_flush = 0;
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tlb_flush(cs, 1);
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}
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}
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#else
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static inline void check_tlb_flush(CPUPPCState *env) { }
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#endif
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2007-10-25 23:35:50 +02:00
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#endif /* !defined(__HELPER_REGS_H__) */
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