2012-03-05 05:39:13 +01:00
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/*
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* Xilinx Zynq Baseboard System emulation.
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*
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* Copyright (c) 2010 Xilinx.
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* Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
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* Copyright (c) 2012 Petalogix Pty Ltd.
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* Written by Haibing Ma
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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2015-12-07 17:23:45 +01:00
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#include "qemu/osdep.h"
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include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 09:01:28 +01:00
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#include "qapi/error.h"
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2016-01-19 21:51:44 +01:00
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#include "qemu-common.h"
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#include "cpu.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/sysbus.h"
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2013-04-09 16:26:55 +02:00
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#include "hw/arm/arm.h"
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2012-10-24 08:43:34 +02:00
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#include "net/net.h"
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2012-12-17 18:19:49 +01:00
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#include "exec/address-spaces.h"
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2012-12-17 18:20:04 +01:00
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#include "sysemu/sysemu.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/boards.h"
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2013-02-05 17:06:20 +01:00
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#include "hw/block/flash.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/loader.h"
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2015-11-12 18:54:55 +01:00
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#include "hw/misc/zynq-xadc.h"
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2016-01-21 15:15:03 +01:00
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#include "hw/ssi/ssi.h"
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2013-12-17 20:42:28 +01:00
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#include "qemu/error-report.h"
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2017-09-04 16:21:53 +02:00
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#include "hw/sd/sdhci.h"
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2016-06-06 17:59:31 +02:00
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#include "hw/char/cadence_uart.h"
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2017-09-04 16:21:53 +02:00
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#include "hw/net/cadence_gem.h"
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#include "hw/cpu/a9mpcore.h"
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2012-08-03 08:08:48 +02:00
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#define NUM_SPI_FLASHES 4
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2012-10-15 06:40:21 +02:00
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#define NUM_QSPI_FLASHES 2
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#define NUM_QSPI_BUSSES 2
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2012-03-05 05:39:13 +01:00
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#define FLASH_SIZE (64 * 1024 * 1024)
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#define FLASH_SECTOR_SIZE (128 * 1024)
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#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
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2013-12-17 20:42:29 +01:00
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#define MPCORE_PERIPHBASE 0xF8F00000
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2014-01-31 15:47:33 +01:00
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#define ZYNQ_BOARD_MIDR 0x413FC090
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2013-12-17 20:42:29 +01:00
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2013-03-15 17:41:58 +01:00
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static const int dma_irqs[8] = {
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46, 47, 48, 49, 72, 73, 74, 75
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};
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2015-11-03 14:49:41 +01:00
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#define BOARD_SETUP_ADDR 0x100
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#define SLCR_LOCK_OFFSET 0x004
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#define SLCR_UNLOCK_OFFSET 0x008
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#define SLCR_ARM_PLL_OFFSET 0x100
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#define SLCR_XILINX_UNLOCK_KEY 0xdf0d
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#define SLCR_XILINX_LOCK_KEY 0x767b
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2018-02-08 17:48:04 +01:00
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#define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */
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2015-11-03 14:49:41 +01:00
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#define ARMV7_IMM16(x) (extract32((x), 0, 12) | \
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extract32((x), 12, 4) << 16)
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/* Write immediate val to address r0 + addr. r0 should contain base offset
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* of the SLCR block. Clobbers r1.
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*/
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#define SLCR_WRITE(addr, val) \
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0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \
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0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
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0xe5801000 + (addr)
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static void zynq_write_board_setup(ARMCPU *cpu,
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const struct arm_boot_info *info)
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{
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int n;
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uint32_t board_setup_blob[] = {
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0xe3a004f8, /* mov r0, #0xf8000000 */
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SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY),
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SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008),
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SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY),
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0xe12fff1e, /* bx lr */
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};
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for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
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board_setup_blob[n] = tswap32(board_setup_blob[n]);
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}
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rom_add_blob_fixed("board-setup", board_setup_blob,
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sizeof(board_setup_blob), BOARD_SETUP_ADDR);
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}
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2012-03-05 05:39:13 +01:00
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static struct arm_boot_info zynq_binfo = {};
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static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
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{
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DeviceState *dev;
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SysBusDevice *s;
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|
2017-09-04 16:21:53 +02:00
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dev = qdev_create(NULL, TYPE_CADENCE_GEM);
|
2014-01-04 02:58:43 +01:00
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if (nd->used) {
|
2017-09-04 16:21:53 +02:00
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qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
|
2014-01-04 02:58:43 +01:00
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qdev_set_nic_properties(dev, nd);
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}
|
2012-03-05 05:39:13 +01:00
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qdev_init_nofail(dev);
|
2013-01-20 02:47:33 +01:00
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s = SYS_BUS_DEVICE(dev);
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2012-03-05 05:39:13 +01:00
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sysbus_mmio_map(s, 0, base);
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sysbus_connect_irq(s, 0, irq);
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}
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2012-10-15 06:40:21 +02:00
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static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
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bool is_qspi)
|
2012-08-03 08:08:48 +02:00
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{
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DeviceState *dev;
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SysBusDevice *busdev;
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SSIBus *spi;
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2012-12-11 12:30:37 +01:00
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DeviceState *flash_dev;
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2012-10-15 06:40:21 +02:00
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int i, j;
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int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1;
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int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
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2012-08-03 08:08:48 +02:00
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2013-06-03 18:17:41 +02:00
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dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
|
2012-10-15 06:40:21 +02:00
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qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
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qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
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qdev_prop_set_uint8(dev, "num-busses", num_busses);
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2012-08-03 08:08:48 +02:00
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qdev_init_nofail(dev);
|
2013-01-20 02:47:33 +01:00
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busdev = SYS_BUS_DEVICE(dev);
|
2012-08-03 08:08:48 +02:00
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sysbus_mmio_map(busdev, 0, base_addr);
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2012-10-15 06:40:21 +02:00
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if (is_qspi) {
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sysbus_mmio_map(busdev, 1, 0xFC000000);
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}
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2012-08-03 08:08:48 +02:00
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sysbus_connect_irq(busdev, 0, irq);
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2012-10-15 06:40:21 +02:00
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for (i = 0; i < num_busses; ++i) {
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char bus_name[16];
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2012-08-03 08:08:48 +02:00
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qemu_irq cs_line;
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2012-10-15 06:40:21 +02:00
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snprintf(bus_name, 16, "spi%d", i);
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spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);
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for (j = 0; j < num_ss; ++j) {
|
2016-07-04 14:06:37 +02:00
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DriveInfo *dinfo = drive_get_next(IF_MTD);
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flash_dev = ssi_create_slave_no_init(spi, "n25q128");
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if (dinfo) {
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qdev_prop_set_drive(flash_dev, "drive",
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blk_by_legacy_dinfo(dinfo), &error_fatal);
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}
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qdev_init_nofail(flash_dev);
|
2012-08-03 08:08:48 +02:00
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2014-05-20 08:31:33 +02:00
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cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
|
2012-10-15 06:40:21 +02:00
|
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sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
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}
|
2012-08-03 08:08:48 +02:00
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}
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}
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2014-05-07 16:42:57 +02:00
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static void zynq_init(MachineState *machine)
|
2012-03-05 05:39:13 +01:00
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{
|
2014-05-07 16:42:57 +02:00
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ram_addr_t ram_size = machine->ram_size;
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const char *kernel_filename = machine->kernel_filename;
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const char *kernel_cmdline = machine->kernel_cmdline;
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const char *initrd_filename = machine->initrd_filename;
|
2012-05-14 02:55:25 +02:00
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ARMCPU *cpu;
|
2012-03-05 05:39:13 +01:00
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
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MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
|
2018-02-08 17:48:04 +01:00
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DeviceState *dev;
|
2012-03-05 05:39:13 +01:00
|
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SysBusDevice *busdev;
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qemu_irq pic[64];
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int n;
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|
2017-09-13 18:04:57 +02:00
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cpu = ARM_CPU(object_new(machine->cpu_type));
|
2013-12-17 20:42:28 +01:00
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|
2014-12-16 00:09:51 +01:00
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/* By default A9 CPUs have EL3 enabled. This board does not
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* currently support EL3 so the CPU EL3 property is disabled before
|
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* realization.
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*/
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|
if (object_property_find(OBJECT(cpu), "has_el3", NULL)) {
|
2015-09-11 15:04:45 +02:00
|
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|
object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal);
|
2014-01-31 15:47:33 +01:00
|
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}
|
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|
2015-09-11 15:04:45 +02:00
|
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|
object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr",
|
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|
|
&error_fatal);
|
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|
|
object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
|
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|
|
&error_fatal);
|
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|
|
object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal);
|
2012-03-05 05:39:13 +01:00
|
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|
|
/* max 2GB ram */
|
|
|
|
if (ram_size > 0x80000000) {
|
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|
|
ram_size = 0x80000000;
|
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|
|
}
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/* DDR remapped to address zero. */
|
2015-04-04 14:24:38 +02:00
|
|
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memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram",
|
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|
|
ram_size);
|
2012-03-05 05:39:13 +01:00
|
|
|
memory_region_add_subregion(address_space_mem, 0, ext_ram);
|
|
|
|
|
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|
|
/* 256K of on-chip memory */
|
2017-07-07 16:42:53 +02:00
|
|
|
memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10,
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 16:51:43 +02:00
|
|
|
&error_fatal);
|
2012-03-05 05:39:13 +01:00
|
|
|
memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
|
|
|
|
|
|
|
|
DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
|
|
|
|
|
|
|
|
/* AMD */
|
2019-03-08 10:46:09 +01:00
|
|
|
pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE,
|
2014-10-07 13:59:18 +02:00
|
|
|
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
|
2014-10-07 13:59:13 +02:00
|
|
|
FLASH_SECTOR_SIZE,
|
2012-03-05 05:39:13 +01:00
|
|
|
FLASH_SIZE/FLASH_SECTOR_SIZE, 1,
|
|
|
|
1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
|
|
|
|
0);
|
|
|
|
|
|
|
|
dev = qdev_create(NULL, "xilinx,zynq_slcr");
|
|
|
|
qdev_init_nofail(dev);
|
2013-01-20 02:47:33 +01:00
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);
|
2012-03-05 05:39:13 +01:00
|
|
|
|
2017-09-04 16:21:53 +02:00
|
|
|
dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
|
2012-03-05 05:39:13 +01:00
|
|
|
qdev_prop_set_uint32(dev, "num-cpu", 1);
|
|
|
|
qdev_init_nofail(dev);
|
2013-01-20 02:47:33 +01:00
|
|
|
busdev = SYS_BUS_DEVICE(dev);
|
2013-12-17 20:42:29 +01:00
|
|
|
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
|
2013-08-20 15:54:30 +02:00
|
|
|
sysbus_connect_irq(busdev, 0,
|
|
|
|
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
|
2012-03-05 05:39:13 +01:00
|
|
|
|
|
|
|
for (n = 0; n < 64; n++) {
|
|
|
|
pic[n] = qdev_get_gpio_in(dev, n);
|
|
|
|
}
|
|
|
|
|
2012-10-15 06:40:21 +02:00
|
|
|
zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);
|
|
|
|
zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
|
|
|
|
zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);
|
2012-08-03 08:08:48 +02:00
|
|
|
|
2012-10-29 02:34:38 +01:00
|
|
|
sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]);
|
2013-02-07 07:58:15 +01:00
|
|
|
sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]);
|
2012-10-29 02:34:38 +01:00
|
|
|
|
2018-04-20 16:52:43 +02:00
|
|
|
cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0));
|
|
|
|
cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1));
|
2012-03-05 05:39:13 +01:00
|
|
|
|
|
|
|
sysbus_create_varargs("cadence_ttc", 0xF8001000,
|
|
|
|
pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
|
|
|
|
sysbus_create_varargs("cadence_ttc", 0xF8002000,
|
|
|
|
pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
|
|
|
|
|
2014-01-04 02:58:43 +01:00
|
|
|
gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
|
|
|
|
gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);
|
2012-03-05 05:39:13 +01:00
|
|
|
|
2018-02-08 17:48:04 +01:00
|
|
|
for (n = 0; n < 2; n++) {
|
|
|
|
int hci_irq = n ? 79 : 56;
|
|
|
|
hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000;
|
|
|
|
DriveInfo *di;
|
|
|
|
BlockBackend *blk;
|
|
|
|
DeviceState *carddev;
|
|
|
|
|
|
|
|
/* Compatible with:
|
|
|
|
* - SD Host Controller Specification Version 2.0 Part A2
|
|
|
|
* - SDIO Specification Version 2.0
|
|
|
|
* - MMC Specification Version 3.31
|
|
|
|
*/
|
|
|
|
dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
|
|
|
|
qdev_prop_set_uint8(dev, "sd-spec-version", 2);
|
|
|
|
qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES);
|
|
|
|
qdev_init_nofail(dev);
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);
|
|
|
|
|
|
|
|
di = drive_get_next(IF_SD);
|
|
|
|
blk = di ? blk_by_legacy_dinfo(di) : NULL;
|
|
|
|
carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
|
|
|
|
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
|
|
|
|
object_property_set_bool(OBJECT(carddev), true, "realized",
|
|
|
|
&error_fatal);
|
|
|
|
}
|
2016-02-18 15:16:18 +01:00
|
|
|
|
2015-11-12 18:54:55 +01:00
|
|
|
dev = qdev_create(NULL, TYPE_ZYNQ_XADC);
|
|
|
|
qdev_init_nofail(dev);
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
|
|
|
|
|
2013-03-15 17:41:58 +01:00
|
|
|
dev = qdev_create(NULL, "pl330");
|
|
|
|
qdev_prop_set_uint8(dev, "num_chnls", 8);
|
|
|
|
qdev_prop_set_uint8(dev, "num_periph_req", 4);
|
|
|
|
qdev_prop_set_uint8(dev, "num_events", 16);
|
|
|
|
|
|
|
|
qdev_prop_set_uint8(dev, "data_width", 64);
|
|
|
|
qdev_prop_set_uint8(dev, "wr_cap", 8);
|
|
|
|
qdev_prop_set_uint8(dev, "wr_q_dep", 16);
|
|
|
|
qdev_prop_set_uint8(dev, "rd_cap", 8);
|
|
|
|
qdev_prop_set_uint8(dev, "rd_q_dep", 16);
|
|
|
|
qdev_prop_set_uint16(dev, "data_buffer_dep", 256);
|
|
|
|
|
|
|
|
qdev_init_nofail(dev);
|
|
|
|
busdev = SYS_BUS_DEVICE(dev);
|
|
|
|
sysbus_mmio_map(busdev, 0, 0xF8003000);
|
|
|
|
sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
|
2018-10-30 16:23:56 +01:00
|
|
|
for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */
|
2013-03-15 17:41:58 +01:00
|
|
|
sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
|
|
|
|
}
|
|
|
|
|
2016-07-04 14:06:37 +02:00
|
|
|
dev = qdev_create(NULL, "xlnx.ps7-dev-cfg");
|
|
|
|
qdev_init_nofail(dev);
|
|
|
|
busdev = SYS_BUS_DEVICE(dev);
|
|
|
|
sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
|
|
|
|
sysbus_mmio_map(busdev, 0, 0xF8007000);
|
|
|
|
|
2012-03-05 05:39:13 +01:00
|
|
|
zynq_binfo.ram_size = ram_size;
|
|
|
|
zynq_binfo.kernel_filename = kernel_filename;
|
|
|
|
zynq_binfo.kernel_cmdline = kernel_cmdline;
|
|
|
|
zynq_binfo.initrd_filename = initrd_filename;
|
|
|
|
zynq_binfo.nb_cpus = 1;
|
|
|
|
zynq_binfo.board_id = 0xd32;
|
|
|
|
zynq_binfo.loader_start = 0;
|
2015-11-03 14:49:41 +01:00
|
|
|
zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
|
|
|
|
zynq_binfo.write_board_setup = zynq_write_board_setup;
|
|
|
|
|
2013-05-29 22:29:20 +02:00
|
|
|
arm_load_kernel(ARM_CPU(first_cpu), &zynq_binfo);
|
2012-03-05 05:39:13 +01:00
|
|
|
}
|
|
|
|
|
2015-09-04 20:37:08 +02:00
|
|
|
static void zynq_machine_init(MachineClass *mc)
|
2012-03-05 05:39:13 +01:00
|
|
|
{
|
2015-09-04 20:37:08 +02:00
|
|
|
mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
|
|
|
|
mc->init = zynq_init;
|
|
|
|
mc->max_cpus = 1;
|
|
|
|
mc->no_sdcard = 1;
|
2017-09-07 14:54:54 +02:00
|
|
|
mc->ignore_memory_transaction_failures = true;
|
2017-09-13 18:04:57 +02:00
|
|
|
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
|
2012-03-05 05:39:13 +01:00
|
|
|
}
|
|
|
|
|
2015-09-04 20:37:08 +02:00
|
|
|
DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)
|