2008-04-07 21:47:14 +02:00
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/*
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* QEMU MIPS Jazz support
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*
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* Copyright (c) 2007-2008 Hervé Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2013-02-04 15:40:22 +01:00
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#include "hw/hw.h"
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2013-02-05 17:06:20 +01:00
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#include "hw/mips/mips.h"
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#include "hw/mips/cpudevs.h"
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#include "hw/i386/pc.h"
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#include "hw/char/serial.h"
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#include "hw/isa/isa.h"
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#include "hw/block/fdc.h"
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2012-12-17 18:20:04 +01:00
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#include "sysemu/sysemu.h"
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#include "sysemu/arch_init.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/boards.h"
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2012-10-24 08:43:34 +02:00
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#include "net/net.h"
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2013-02-05 17:06:20 +01:00
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#include "hw/scsi/esp.h"
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#include "hw/mips/bios.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/loader.h"
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2013-02-05 17:06:20 +01:00
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#include "hw/timer/mc146818rtc.h"
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#include "hw/timer/i8254.h"
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#include "hw/audio/pcspk.h"
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2014-10-07 13:59:18 +02:00
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#include "sysemu/block-backend.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/sysbus.h"
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2012-12-17 18:19:49 +01:00
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#include "exec/address-spaces.h"
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2013-07-29 16:05:32 +02:00
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#include "sysemu/qtest.h"
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2013-08-03 16:03:18 +02:00
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#include "qemu/error-report.h"
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2008-04-07 21:47:14 +02:00
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enum jazz_model_e
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{
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JAZZ_MAGNUM,
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2008-04-08 21:51:06 +02:00
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JAZZ_PICA61,
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2008-04-07 21:47:14 +02:00
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};
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static void main_cpu_reset(void *opaque)
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{
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2012-05-05 14:06:50 +02:00
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MIPSCPU *cpu = opaque;
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cpu_reset(CPU(cpu));
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2008-04-07 21:47:14 +02:00
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}
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2012-10-23 12:30:10 +02:00
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static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
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2008-04-07 21:47:14 +02:00
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{
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2015-02-01 09:12:52 +01:00
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uint8_t val;
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2015-04-26 17:49:24 +02:00
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address_space_read(&address_space_memory, 0x90000071,
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MEMTXATTRS_UNSPECIFIED, &val, 1);
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2015-02-01 09:12:52 +01:00
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return val;
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2008-04-07 21:47:14 +02:00
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}
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2012-10-23 12:30:10 +02:00
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static void rtc_write(void *opaque, hwaddr addr,
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2011-08-08 20:59:19 +02:00
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uint64_t val, unsigned size)
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2008-04-07 21:47:14 +02:00
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{
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2015-02-01 09:12:52 +01:00
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uint8_t buf = val & 0xff;
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2015-04-26 17:49:24 +02:00
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address_space_write(&address_space_memory, 0x90000071,
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MEMTXATTRS_UNSPECIFIED, &buf, 1);
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2008-04-07 21:47:14 +02:00
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}
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2011-08-08 20:59:19 +02:00
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static const MemoryRegionOps rtc_ops = {
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.read = rtc_read,
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.write = rtc_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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2008-04-07 21:47:14 +02:00
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};
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2012-10-23 12:30:10 +02:00
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static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
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2011-08-08 20:59:19 +02:00
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unsigned size)
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2009-01-01 14:03:36 +01:00
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{
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/* Nothing to do. That is only to ensure that
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* the current DMA acknowledge cycle is completed. */
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2011-08-08 20:59:19 +02:00
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return 0xff;
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2009-01-01 14:03:36 +01:00
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}
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2012-10-23 12:30:10 +02:00
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static void dma_dummy_write(void *opaque, hwaddr addr,
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2011-08-08 20:59:19 +02:00
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uint64_t val, unsigned size)
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{
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/* Nothing to do. That is only to ensure that
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* the current DMA acknowledge cycle is completed. */
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}
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2009-01-01 14:03:36 +01:00
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2011-08-08 20:59:19 +02:00
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static const MemoryRegionOps dma_dummy_ops = {
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.read = dma_dummy_read,
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.write = dma_dummy_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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2009-01-01 14:03:36 +01:00
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};
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2008-04-07 21:47:14 +02:00
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#define MAGNUM_BIOS_SIZE_MAX 0x7e000
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#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
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2010-05-22 10:00:52 +02:00
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static void cpu_request_exit(void *opaque, int irq, int level)
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{
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2013-05-27 05:17:50 +02:00
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CPUState *cpu = current_cpu;
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2010-05-22 10:00:52 +02:00
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2013-05-27 05:17:50 +02:00
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if (cpu && level) {
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cpu_exit(cpu);
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2010-05-22 10:00:52 +02:00
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}
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}
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2013-11-04 23:26:17 +01:00
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static CPUUnassignedAccess real_do_unassigned_access;
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static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr,
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bool is_write, bool is_exec,
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int opaque, unsigned size)
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{
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if (!is_exec) {
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/* ignore invalid access (ie do not raise exception) */
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return;
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}
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(*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size);
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}
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2015-02-01 09:12:51 +01:00
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static void mips_jazz_init(MachineState *machine,
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2011-08-11 00:28:11 +02:00
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enum jazz_model_e jazz_model)
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2008-04-07 21:47:14 +02:00
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{
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2015-02-01 09:12:51 +01:00
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MemoryRegion *address_space = get_system_memory();
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const char *cpu_model = machine->cpu_model;
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2009-05-30 01:52:44 +02:00
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char *filename;
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2008-04-07 21:47:14 +02:00
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int bios_size, n;
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2012-05-05 14:05:42 +02:00
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MIPSCPU *cpu;
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2013-11-04 23:26:17 +01:00
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CPUClass *cc;
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2012-03-14 01:38:23 +01:00
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CPUMIPSState *env;
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2008-04-07 21:47:14 +02:00
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qemu_irq *rc4030, *i8259;
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2009-01-01 14:03:36 +01:00
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rc4030_dma *dmas;
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2015-06-03 22:45:37 +02:00
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MemoryRegion *rc4030_dma_mr;
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2015-02-01 09:12:52 +01:00
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MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
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MemoryRegion *isa_io = g_new(MemoryRegion, 1);
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2011-08-08 20:59:19 +02:00
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MemoryRegion *rtc = g_new(MemoryRegion, 1);
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2011-08-11 00:28:17 +02:00
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MemoryRegion *i8042 = g_new(MemoryRegion, 1);
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2011-08-08 20:59:19 +02:00
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MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
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2009-04-15 16:57:54 +02:00
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NICInfo *nd;
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2011-07-18 23:34:22 +02:00
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DeviceState *dev;
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SysBusDevice *sysbus;
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2011-12-15 22:09:51 +01:00
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ISABus *isa_bus;
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2011-02-13 20:54:40 +01:00
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ISADevice *pit;
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2009-09-22 13:53:18 +02:00
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DriveInfo *fds[MAX_FD];
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2010-09-11 18:38:33 +02:00
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qemu_irq esp_reset, dma_enable;
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2010-05-22 10:00:52 +02:00
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qemu_irq *cpu_exit_irq;
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2011-08-08 20:59:19 +02:00
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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MemoryRegion *bios = g_new(MemoryRegion, 1);
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MemoryRegion *bios2 = g_new(MemoryRegion, 1);
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2008-04-07 21:47:14 +02:00
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/* init CPUs */
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if (cpu_model == NULL) {
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cpu_model = "R4000";
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}
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2012-05-05 14:05:42 +02:00
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cpu = cpu_mips_init(cpu_model);
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if (cpu == NULL) {
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2008-04-07 21:47:14 +02:00
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fprintf(stderr, "Unable to find CPU definition\n");
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exit(1);
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}
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2012-05-05 14:05:42 +02:00
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env = &cpu->env;
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2012-05-05 14:06:50 +02:00
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qemu_register_reset(main_cpu_reset, cpu);
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2008-04-07 21:47:14 +02:00
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2013-11-04 23:26:17 +01:00
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/* Chipset returns 0 in invalid reads and do not raise data exceptions.
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* However, we can't simply add a global memory region to catch
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* everything, as memory core directly call unassigned_mem_read/write
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* on some invalid accesses, which call do_unassigned_access on the
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* CPU, which raise an exception.
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* Handle that case by hijacking the do_unassigned_access method on
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* the CPU, and do not raise exceptions for data access. */
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cc = CPU_GET_CLASS(cpu);
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real_do_unassigned_access = cc->do_unassigned_access;
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cc->do_unassigned_access = mips_jazz_do_unassigned_access;
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2008-04-07 21:47:14 +02:00
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/* allocate RAM */
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2015-03-24 22:28:15 +01:00
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memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram",
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machine->ram_size);
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2011-08-08 20:59:19 +02:00
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memory_region_add_subregion(address_space, 0, ram);
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2009-04-09 22:05:49 +02:00
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2014-09-09 07:27:55 +02:00
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memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE,
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&error_abort);
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2011-12-20 14:59:12 +01:00
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vmstate_register_ram_global(bios);
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2011-08-08 20:59:19 +02:00
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memory_region_set_readonly(bios, true);
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2013-06-06 11:41:28 +02:00
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memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
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2011-08-08 20:59:19 +02:00
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0, MAGNUM_BIOS_SIZE);
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memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
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memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
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2008-04-07 21:47:14 +02:00
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/* load the BIOS image. */
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2009-01-01 14:03:36 +01:00
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if (bios_name == NULL)
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bios_name = BIOS_FILENAME;
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2009-05-30 01:52:44 +02:00
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
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if (filename) {
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bios_size = load_image_targphys(filename, 0xfff00000LL,
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MAGNUM_BIOS_SIZE);
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2011-08-21 05:09:37 +02:00
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g_free(filename);
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2009-05-30 01:52:44 +02:00
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} else {
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bios_size = -1;
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}
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2013-07-29 16:05:32 +02:00
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if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {
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2013-08-03 16:03:18 +02:00
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error_report("Could not load MIPS bios '%s'", bios_name);
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exit(1);
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2008-04-07 21:47:14 +02:00
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}
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/* Init CPU internal devices */
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cpu_mips_irq_init_cpu(env);
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cpu_mips_clock_init(env);
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/* Chipset */
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2015-06-03 22:45:37 +02:00
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rc4030_dma_mr = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas,
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2011-11-06 18:30:48 +01:00
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address_space);
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2013-06-06 11:41:28 +02:00
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memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
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2011-08-08 20:59:19 +02:00
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memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
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2008-04-07 21:47:14 +02:00
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2015-02-01 09:12:52 +01:00
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/* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
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memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
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memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
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memory_region_add_subregion(address_space, 0x90000000, isa_io);
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memory_region_add_subregion(address_space, 0x91000000, isa_mem);
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isa_bus = isa_bus_new(NULL, isa_mem, isa_io);
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2008-04-07 21:47:14 +02:00
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/* ISA devices */
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2011-12-15 22:09:51 +01:00
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i8259 = i8259_init(isa_bus, env->irq[4]);
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isa_bus_irqs(isa_bus, i8259);
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2010-05-22 10:00:52 +02:00
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cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
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DMA_init(0, cpu_exit_irq);
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2012-02-01 20:31:40 +01:00
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pit = pit_init(isa_bus, 0x40, 0, NULL);
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2012-02-17 11:24:34 +01:00
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pcspk_init(isa_bus, pit);
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2008-04-07 21:47:14 +02:00
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/* Video card */
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switch (jazz_model) {
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case JAZZ_MAGNUM:
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2011-08-26 21:20:12 +02:00
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dev = qdev_create(NULL, "sysbus-g364");
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qdev_init_nofail(dev);
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2013-01-20 02:47:33 +01:00
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sysbus = SYS_BUS_DEVICE(dev);
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2011-08-26 21:20:12 +02:00
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sysbus_mmio_map(sysbus, 0, 0x60080000);
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sysbus_mmio_map(sysbus, 1, 0x40000000);
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sysbus_connect_irq(sysbus, 0, rc4030[3]);
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{
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/* Simple ROM, so user doesn't have to provide one */
|
2011-08-08 20:59:19 +02:00
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MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
|
2014-09-09 07:27:55 +02:00
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memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000,
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&error_abort);
|
2011-12-20 14:59:12 +01:00
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vmstate_register_ram_global(rom_mr);
|
2011-08-08 20:59:19 +02:00
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memory_region_set_readonly(rom_mr, true);
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uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
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memory_region_add_subregion(address_space, 0x60000000, rom_mr);
|
2011-08-26 21:20:12 +02:00
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|
rom[0] = 0x10; /* Mips G364 */
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}
|
2008-04-07 21:47:14 +02:00
|
|
|
break;
|
2008-04-08 21:51:06 +02:00
|
|
|
case JAZZ_PICA61:
|
2011-08-15 16:17:37 +02:00
|
|
|
isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
|
2008-04-08 21:51:06 +02:00
|
|
|
break;
|
2008-04-07 21:47:14 +02:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Network controller */
|
2009-04-15 16:57:54 +02:00
|
|
|
for (n = 0; n < nb_nics; n++) {
|
|
|
|
nd = &nd_table[n];
|
|
|
|
if (!nd->model)
|
2011-08-21 05:09:37 +02:00
|
|
|
nd->model = g_strdup("dp83932");
|
2009-04-15 16:57:54 +02:00
|
|
|
if (strcmp(nd->model, "dp83932") == 0) {
|
2011-11-09 17:22:37 +01:00
|
|
|
dp83932_init(nd, 0x80001000, 2, get_system_memory(), rc4030[4],
|
2015-06-03 22:45:37 +02:00
|
|
|
rc4030_dma_mr);
|
2009-04-15 16:57:54 +02:00
|
|
|
break;
|
2012-08-02 14:45:54 +02:00
|
|
|
} else if (is_help_option(nd->model)) {
|
2009-04-15 16:57:54 +02:00
|
|
|
fprintf(stderr, "qemu: Supported NICs: dp83932\n");
|
|
|
|
exit(1);
|
|
|
|
} else {
|
|
|
|
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
}
|
2008-04-07 21:47:14 +02:00
|
|
|
|
|
|
|
/* SCSI adapter */
|
2009-05-14 23:35:07 +02:00
|
|
|
esp_init(0x80002000, 0,
|
|
|
|
rc4030_dma_read, rc4030_dma_write, dmas[0],
|
2010-09-11 18:38:33 +02:00
|
|
|
rc4030[5], &esp_reset, &dma_enable);
|
2008-04-07 21:47:14 +02:00
|
|
|
|
|
|
|
/* Floppy */
|
|
|
|
if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
|
|
|
|
fprintf(stderr, "qemu: too many floppy drives\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
for (n = 0; n < MAX_FD; n++) {
|
2009-09-22 13:53:18 +02:00
|
|
|
fds[n] = drive_get(IF_FLOPPY, 0, n);
|
2008-04-07 21:47:14 +02:00
|
|
|
}
|
2009-08-14 11:36:14 +02:00
|
|
|
fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);
|
2008-04-07 21:47:14 +02:00
|
|
|
|
|
|
|
/* Real time clock */
|
2011-12-15 22:09:51 +01:00
|
|
|
rtc_init(isa_bus, 1980, NULL);
|
2013-06-06 11:41:28 +02:00
|
|
|
memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
|
2011-08-08 20:59:19 +02:00
|
|
|
memory_region_add_subregion(address_space, 0x80004000, rtc);
|
2008-04-07 21:47:14 +02:00
|
|
|
|
|
|
|
/* Keyboard (i8042) */
|
2011-08-11 00:28:17 +02:00
|
|
|
i8042_mm_init(rc4030[6], rc4030[7], i8042, 0x1000, 0x1);
|
|
|
|
memory_region_add_subregion(address_space, 0x80005000, i8042);
|
2008-04-07 21:47:14 +02:00
|
|
|
|
|
|
|
/* Serial ports */
|
2010-03-21 20:47:11 +01:00
|
|
|
if (serial_hds[0]) {
|
2011-08-12 01:07:16 +02:00
|
|
|
serial_mm_init(address_space, 0x80006000, 0, rc4030[8], 8000000/16,
|
|
|
|
serial_hds[0], DEVICE_NATIVE_ENDIAN);
|
2010-03-21 20:47:11 +01:00
|
|
|
}
|
|
|
|
if (serial_hds[1]) {
|
2011-08-12 01:07:16 +02:00
|
|
|
serial_mm_init(address_space, 0x80007000, 0, rc4030[9], 8000000/16,
|
|
|
|
serial_hds[1], DEVICE_NATIVE_ENDIAN);
|
2010-03-21 20:47:11 +01:00
|
|
|
}
|
2008-04-07 21:47:14 +02:00
|
|
|
|
|
|
|
/* Parallel port */
|
|
|
|
if (parallel_hds[0])
|
2011-10-06 16:44:26 +02:00
|
|
|
parallel_mm_init(address_space, 0x80008000, 0, rc4030[0],
|
|
|
|
parallel_hds[0]);
|
2008-04-07 21:47:14 +02:00
|
|
|
|
|
|
|
/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
|
|
|
|
|
2011-07-18 23:34:22 +02:00
|
|
|
/* NVRAM */
|
|
|
|
dev = qdev_create(NULL, "ds1225y");
|
|
|
|
qdev_init_nofail(dev);
|
2013-01-20 02:47:33 +01:00
|
|
|
sysbus = SYS_BUS_DEVICE(dev);
|
2011-07-18 23:34:22 +02:00
|
|
|
sysbus_mmio_map(sysbus, 0, 0x80009000);
|
2008-04-07 21:47:14 +02:00
|
|
|
|
|
|
|
/* LED indicator */
|
2012-02-17 20:27:16 +01:00
|
|
|
sysbus_create_simple("jazz-led", 0x8000f000, NULL);
|
2008-04-07 21:47:14 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static
|
2014-05-07 16:42:57 +02:00
|
|
|
void mips_magnum_init(MachineState *machine)
|
2008-04-07 21:47:14 +02:00
|
|
|
{
|
2015-02-01 09:12:51 +01:00
|
|
|
mips_jazz_init(machine, JAZZ_MAGNUM);
|
2008-04-07 21:47:14 +02:00
|
|
|
}
|
|
|
|
|
2008-04-08 21:51:06 +02:00
|
|
|
static
|
2014-05-07 16:42:57 +02:00
|
|
|
void mips_pica61_init(MachineState *machine)
|
2008-04-08 21:51:06 +02:00
|
|
|
{
|
2015-02-01 09:12:51 +01:00
|
|
|
mips_jazz_init(machine, JAZZ_PICA61);
|
2008-04-08 21:51:06 +02:00
|
|
|
}
|
|
|
|
|
2009-05-21 01:38:09 +02:00
|
|
|
static QEMUMachine mips_magnum_machine = {
|
2008-08-13 15:01:28 +02:00
|
|
|
.name = "magnum",
|
|
|
|
.desc = "MIPS Magnum",
|
|
|
|
.init = mips_magnum_init,
|
2012-11-20 15:30:34 +01:00
|
|
|
.block_default_type = IF_SCSI,
|
2008-04-07 21:47:14 +02:00
|
|
|
};
|
2008-04-08 21:51:06 +02:00
|
|
|
|
2009-05-21 01:38:09 +02:00
|
|
|
static QEMUMachine mips_pica61_machine = {
|
2008-08-13 15:01:28 +02:00
|
|
|
.name = "pica61",
|
|
|
|
.desc = "Acer Pica 61",
|
|
|
|
.init = mips_pica61_init,
|
2012-11-20 15:30:34 +01:00
|
|
|
.block_default_type = IF_SCSI,
|
2008-04-08 21:51:06 +02:00
|
|
|
};
|
2009-05-21 01:38:09 +02:00
|
|
|
|
|
|
|
static void mips_jazz_machine_init(void)
|
|
|
|
{
|
|
|
|
qemu_register_machine(&mips_magnum_machine);
|
|
|
|
qemu_register_machine(&mips_pica61_machine);
|
|
|
|
}
|
|
|
|
|
|
|
|
machine_init(mips_jazz_machine_init);
|