2009-05-20 20:16:11 +02:00
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/* OPB Interrupt Controller. */
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qemu_irq *microblaze_pic_init_cpu(CPUState *env);
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static inline DeviceState *
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2009-10-01 20:20:47 +02:00
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xilinx_intc_create(a_target_phys_addr base, qemu_irq irq, int kind_of_intr)
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2009-05-20 20:16:11 +02:00
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{
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DeviceState *dev;
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dev = qdev_create(NULL, "xilinx,intc");
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2009-07-15 13:43:31 +02:00
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qdev_prop_set_uint32(dev, "kind-of-intr", kind_of_intr);
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2009-05-20 20:16:11 +02:00
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qdev_init(dev);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
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return dev;
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}
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/* OPB Timer/Counter. */
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static inline DeviceState *
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2009-10-01 20:20:47 +02:00
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xilinx_timer_create(a_target_phys_addr base, qemu_irq irq, int nr, int freq)
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2009-05-20 20:16:11 +02:00
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{
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DeviceState *dev;
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dev = qdev_create(NULL, "xilinx,timer");
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2009-07-15 13:43:31 +02:00
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qdev_prop_set_uint32(dev, "nr-timers", nr);
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qdev_prop_set_uint32(dev, "frequency", freq);
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2009-05-20 20:16:11 +02:00
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qdev_init(dev);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
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return dev;
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}
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/* XPS Ethernet Lite MAC. */
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static inline DeviceState *
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2009-10-01 20:20:47 +02:00
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xilinx_ethlite_create(NICInfo *nd, a_target_phys_addr base, qemu_irq irq,
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2009-05-20 20:16:11 +02:00
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int txpingpong, int rxpingpong)
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{
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DeviceState *dev;
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qemu_check_nic_model(nd, "xilinx-ethlite");
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dev = qdev_create(NULL, "xilinx,ethlite");
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2009-07-15 13:43:31 +02:00
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dev->nd = nd;
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qdev_prop_set_uint32(dev, "txpingpong", txpingpong);
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qdev_prop_set_uint32(dev, "rxpingpong", rxpingpong);
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2009-05-20 20:16:11 +02:00
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qdev_init(dev);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
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return dev;
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}
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