1064 lines
25 KiB
C
1064 lines
25 KiB
C
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/*
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* MIPS ASE DSP Instruction emulation helpers for QEMU.
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*
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* Copyright (c) 2012 Jia Liu <proljc@gmail.com>
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* Dongxue Zhang <elat.era@gmail.com>
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "helper.h"
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/*** MIPS DSP internal functions begin ***/
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#define MIPSDSP_ABS(x) (((x) >= 0) ? x : -x)
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#define MIPSDSP_OVERFLOW(a, b, c, d) (!(!((a ^ b ^ -1) & (a ^ c) & d)))
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static inline void set_DSPControl_overflow_flag(uint32_t flag, int position,
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CPUMIPSState *env)
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{
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env->active_tc.DSPControl |= (target_ulong)flag << position;
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}
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static inline void set_DSPControl_carryflag(uint32_t flag, CPUMIPSState *env)
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{
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env->active_tc.DSPControl |= (target_ulong)flag << 13;
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}
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static inline uint32_t get_DSPControl_carryflag(CPUMIPSState *env)
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{
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return (env->active_tc.DSPControl >> 13) & 0x01;
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}
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static inline void set_DSPControl_24(uint32_t flag, int len, CPUMIPSState *env)
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{
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uint32_t filter;
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filter = ((0x01 << len) - 1) << 24;
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filter = ~filter;
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env->active_tc.DSPControl &= filter;
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env->active_tc.DSPControl |= (target_ulong)flag << 24;
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}
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static inline uint32_t get_DSPControl_24(int len, CPUMIPSState *env)
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{
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uint32_t filter;
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filter = (0x01 << len) - 1;
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return (env->active_tc.DSPControl >> 24) & filter;
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}
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static inline void set_DSPControl_pos(uint32_t pos, CPUMIPSState *env)
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{
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target_ulong dspc;
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dspc = env->active_tc.DSPControl;
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#ifndef TARGET_MIPS64
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dspc = dspc & 0xFFFFFFC0;
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dspc |= pos;
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#else
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dspc = dspc & 0xFFFFFF80;
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dspc |= pos;
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#endif
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env->active_tc.DSPControl = dspc;
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}
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static inline uint32_t get_DSPControl_pos(CPUMIPSState *env)
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{
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target_ulong dspc;
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uint32_t pos;
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dspc = env->active_tc.DSPControl;
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#ifndef TARGET_MIPS64
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pos = dspc & 0x3F;
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#else
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pos = dspc & 0x7F;
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#endif
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return pos;
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}
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static inline void set_DSPControl_efi(uint32_t flag, CPUMIPSState *env)
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{
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env->active_tc.DSPControl &= 0xFFFFBFFF;
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env->active_tc.DSPControl |= (target_ulong)flag << 14;
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}
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#define DO_MIPS_SAT_ABS(size) \
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static inline int##size##_t mipsdsp_sat_abs##size(int##size##_t a, \
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CPUMIPSState *env) \
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{ \
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if (a == INT##size##_MIN) { \
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set_DSPControl_overflow_flag(1, 20, env); \
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return INT##size##_MAX; \
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} else { \
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return MIPSDSP_ABS(a); \
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} \
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}
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DO_MIPS_SAT_ABS(8)
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DO_MIPS_SAT_ABS(16)
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DO_MIPS_SAT_ABS(32)
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#undef DO_MIPS_SAT_ABS
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/* get sum value */
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static inline int16_t mipsdsp_add_i16(int16_t a, int16_t b, CPUMIPSState *env)
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{
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int16_t tempI;
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tempI = a + b;
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if (MIPSDSP_OVERFLOW(a, b, tempI, 0x8000)) {
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set_DSPControl_overflow_flag(1, 20, env);
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}
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return tempI;
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}
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static inline int16_t mipsdsp_sat_add_i16(int16_t a, int16_t b,
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CPUMIPSState *env)
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{
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int16_t tempS;
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tempS = a + b;
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if (MIPSDSP_OVERFLOW(a, b, tempS, 0x8000)) {
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if (a > 0) {
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tempS = 0x7FFF;
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} else {
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tempS = 0x8000;
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}
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set_DSPControl_overflow_flag(1, 20, env);
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}
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return tempS;
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}
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static inline int32_t mipsdsp_sat_add_i32(int32_t a, int32_t b,
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CPUMIPSState *env)
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{
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int32_t tempI;
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tempI = a + b;
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if (MIPSDSP_OVERFLOW(a, b, tempI, 0x80000000)) {
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if (a > 0) {
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tempI = 0x7FFFFFFF;
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} else {
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tempI = 0x80000000;
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}
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set_DSPControl_overflow_flag(1, 20, env);
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}
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return tempI;
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}
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static inline uint8_t mipsdsp_add_u8(uint8_t a, uint8_t b, CPUMIPSState *env)
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{
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uint16_t temp;
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temp = (uint16_t)a + (uint16_t)b;
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if (temp & 0x0100) {
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set_DSPControl_overflow_flag(1, 20, env);
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}
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return temp & 0xFF;
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}
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static inline uint16_t mipsdsp_add_u16(uint16_t a, uint16_t b,
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CPUMIPSState *env)
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{
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uint32_t temp;
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temp = (uint32_t)a + (uint32_t)b;
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if (temp & 0x00010000) {
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set_DSPControl_overflow_flag(1, 20, env);
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}
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return temp & 0xFFFF;
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}
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static inline uint8_t mipsdsp_sat_add_u8(uint8_t a, uint8_t b,
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CPUMIPSState *env)
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{
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uint8_t result;
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uint16_t temp;
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temp = (uint16_t)a + (uint16_t)b;
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result = temp & 0xFF;
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if (0x0100 & temp) {
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result = 0xFF;
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set_DSPControl_overflow_flag(1, 20, env);
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}
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return result;
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}
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static inline uint16_t mipsdsp_sat_add_u16(uint16_t a, uint16_t b,
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CPUMIPSState *env)
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{
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uint16_t result;
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uint32_t temp;
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temp = (uint32_t)a + (uint32_t)b;
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result = temp & 0xFFFF;
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if (0x00010000 & temp) {
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result = 0xFFFF;
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set_DSPControl_overflow_flag(1, 20, env);
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}
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return result;
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}
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static inline int32_t mipsdsp_sat32_acc_q31(int32_t acc, int32_t a,
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CPUMIPSState *env)
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{
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int64_t temp;
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int32_t temp32, temp31, result;
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int64_t temp_sum;
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#ifndef TARGET_MIPS64
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temp = ((uint64_t)env->active_tc.HI[acc] << 32) |
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(uint64_t)env->active_tc.LO[acc];
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#else
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temp = (uint64_t)env->active_tc.LO[acc];
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#endif
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temp_sum = (int64_t)a + temp;
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temp32 = (temp_sum >> 32) & 0x01;
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temp31 = (temp_sum >> 31) & 0x01;
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result = temp_sum & 0xFFFFFFFF;
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/* FIXME
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This sat function may wrong, because user manual wrote:
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temp127..0 ← temp + ( (signA) || a31..0
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if ( temp32 ≠ temp31 ) then
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if ( temp32 = 0 ) then
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temp31..0 ← 0x80000000
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else
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temp31..0 ← 0x7FFFFFFF
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endif
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DSPControlouflag:16+acc ← 1
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endif
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*/
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if (temp32 != temp31) {
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if (temp32 == 0) {
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result = 0x7FFFFFFF;
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} else {
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result = 0x80000000;
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}
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set_DSPControl_overflow_flag(1, 16 + acc, env);
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}
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return result;
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}
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/* a[0] is LO, a[1] is HI. */
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static inline void mipsdsp_sat64_acc_add_q63(int64_t *ret,
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int32_t ac,
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int64_t *a,
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CPUMIPSState *env)
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{
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bool temp64;
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ret[0] = env->active_tc.LO[ac] + a[0];
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ret[1] = env->active_tc.HI[ac] + a[1];
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if (((uint64_t)ret[0] < (uint64_t)env->active_tc.LO[ac]) &&
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((uint64_t)ret[0] < (uint64_t)a[0])) {
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ret[1] += 1;
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}
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temp64 = ret[1] & 1;
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if (temp64 != ((ret[0] >> 63) & 0x01)) {
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if (temp64) {
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ret[0] = (0x01ull << 63);
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ret[1] = ~0ull;
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} else {
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ret[0] = (0x01ull << 63) - 1;
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ret[1] = 0x00;
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}
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set_DSPControl_overflow_flag(1, 16 + ac, env);
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}
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}
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static inline void mipsdsp_sat64_acc_sub_q63(int64_t *ret,
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int32_t ac,
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int64_t *a,
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CPUMIPSState *env)
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{
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bool temp64;
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ret[0] = env->active_tc.LO[ac] - a[0];
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ret[1] = env->active_tc.HI[ac] - a[1];
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if ((uint64_t)ret[0] > (uint64_t)env->active_tc.LO[ac]) {
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ret[1] -= 1;
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}
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temp64 = ret[1] & 1;
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if (temp64 != ((ret[0] >> 63) & 0x01)) {
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if (temp64) {
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ret[0] = (0x01ull << 63);
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ret[1] = ~0ull;
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} else {
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ret[0] = (0x01ull << 63) - 1;
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ret[1] = 0x00;
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}
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set_DSPControl_overflow_flag(1, 16 + ac, env);
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}
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}
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static inline int32_t mipsdsp_mul_i16_i16(int16_t a, int16_t b,
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CPUMIPSState *env)
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{
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int32_t temp;
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temp = (int32_t)a * (int32_t)b;
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if ((temp > (int)0x7FFF) || (temp < (int)0xFFFF8000)) {
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set_DSPControl_overflow_flag(1, 21, env);
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}
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temp &= 0x0000FFFF;
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return temp;
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}
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static inline int32_t mipsdsp_mul_u16_u16(int32_t a, int32_t b)
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{
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return a * b;
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}
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static inline int32_t mipsdsp_mul_i32_i32(int32_t a, int32_t b)
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{
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return a * b;
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}
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static inline int32_t mipsdsp_sat16_mul_i16_i16(int16_t a, int16_t b,
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CPUMIPSState *env)
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{
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int32_t temp;
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temp = (int32_t)a * (int32_t)b;
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if (temp > (int)0x7FFF) {
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temp = 0x00007FFF;
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set_DSPControl_overflow_flag(1, 21, env);
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} else if (temp < (int)0xffff8000) {
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temp = 0xFFFF8000;
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set_DSPControl_overflow_flag(1, 21, env);
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}
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temp &= 0x0000FFFF;
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return temp;
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}
|
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static inline int32_t mipsdsp_mul_q15_q15_overflowflag21(uint16_t a, uint16_t b,
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CPUMIPSState *env)
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{
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int32_t temp;
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if ((a == 0x8000) && (b == 0x8000)) {
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temp = 0x7FFFFFFF;
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set_DSPControl_overflow_flag(1, 21, env);
|
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} else {
|
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temp = ((int32_t)(int16_t)a * (int32_t)(int16_t)b) << 1;
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}
|
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return temp;
|
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}
|
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|
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/* right shift */
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static inline uint8_t mipsdsp_rshift_u8(uint8_t a, target_ulong mov)
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{
|
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return a >> mov;
|
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}
|
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static inline uint16_t mipsdsp_rshift_u16(uint16_t a, target_ulong mov)
|
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{
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return a >> mov;
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}
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static inline int8_t mipsdsp_rashift8(int8_t a, target_ulong mov)
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{
|
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return a >> mov;
|
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}
|
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static inline int16_t mipsdsp_rashift16(int16_t a, target_ulong mov)
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{
|
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return a >> mov;
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}
|
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static inline int32_t mipsdsp_rashift32(int32_t a, target_ulong mov)
|
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{
|
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return a >> mov;
|
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}
|
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|
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static inline int16_t mipsdsp_rshift1_add_q16(int16_t a, int16_t b)
|
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|
{
|
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int32_t temp;
|
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|
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temp = (int32_t)a + (int32_t)b;
|
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|
|
||
|
return (temp >> 1) & 0xFFFF;
|
||
|
}
|
||
|
|
||
|
/* round right shift */
|
||
|
static inline int16_t mipsdsp_rrshift1_add_q16(int16_t a, int16_t b)
|
||
|
{
|
||
|
int32_t temp;
|
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|
|
||
|
temp = (int32_t)a + (int32_t)b;
|
||
|
temp += 1;
|
||
|
|
||
|
return (temp >> 1) & 0xFFFF;
|
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|
}
|
||
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|
||
|
static inline int32_t mipsdsp_rshift1_add_q32(int32_t a, int32_t b)
|
||
|
{
|
||
|
int64_t temp;
|
||
|
|
||
|
temp = (int64_t)a + (int64_t)b;
|
||
|
|
||
|
return (temp >> 1) & 0xFFFFFFFF;
|
||
|
}
|
||
|
|
||
|
static inline int32_t mipsdsp_rrshift1_add_q32(int32_t a, int32_t b)
|
||
|
{
|
||
|
int64_t temp;
|
||
|
|
||
|
temp = (int64_t)a + (int64_t)b;
|
||
|
temp += 1;
|
||
|
|
||
|
return (temp >> 1) & 0xFFFFFFFF;
|
||
|
}
|
||
|
|
||
|
static inline uint8_t mipsdsp_rshift1_add_u8(uint8_t a, uint8_t b)
|
||
|
{
|
||
|
uint16_t temp;
|
||
|
|
||
|
temp = (uint16_t)a + (uint16_t)b;
|
||
|
|
||
|
return (temp >> 1) & 0x00FF;
|
||
|
}
|
||
|
|
||
|
static inline uint8_t mipsdsp_rrshift1_add_u8(uint8_t a, uint8_t b)
|
||
|
{
|
||
|
uint16_t temp;
|
||
|
|
||
|
temp = (uint16_t)a + (uint16_t)b + 1;
|
||
|
|
||
|
return (temp >> 1) & 0x00FF;
|
||
|
}
|
||
|
|
||
|
static inline uint8_t mipsdsp_rshift1_sub_u8(uint8_t a, uint8_t b)
|
||
|
{
|
||
|
uint16_t temp;
|
||
|
|
||
|
temp = (uint16_t)a - (uint16_t)b;
|
||
|
|
||
|
return (temp >> 1) & 0x00FF;
|
||
|
}
|
||
|
|
||
|
static inline uint8_t mipsdsp_rrshift1_sub_u8(uint8_t a, uint8_t b)
|
||
|
{
|
||
|
uint16_t temp;
|
||
|
|
||
|
temp = (uint16_t)a - (uint16_t)b + 1;
|
||
|
|
||
|
return (temp >> 1) & 0x00FF;
|
||
|
}
|
||
|
|
||
|
static inline int64_t mipsdsp_rashift_short_acc(int32_t ac,
|
||
|
int32_t shift,
|
||
|
CPUMIPSState *env)
|
||
|
{
|
||
|
int32_t sign, temp31;
|
||
|
int64_t temp, acc;
|
||
|
|
||
|
sign = (env->active_tc.HI[ac] >> 31) & 0x01;
|
||
|
acc = ((int64_t)env->active_tc.HI[ac] << 32) |
|
||
|
((int64_t)env->active_tc.LO[ac] & 0xFFFFFFFF);
|
||
|
if (shift == 0) {
|
||
|
temp = acc;
|
||
|
} else {
|
||
|
if (sign == 0) {
|
||
|
temp = (((int64_t)0x01 << (32 - shift + 1)) - 1) & (acc >> shift);
|
||
|
} else {
|
||
|
temp = ((((int64_t)0x01 << (shift + 1)) - 1) << (32 - shift)) |
|
||
|
(acc >> shift);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
temp31 = (temp >> 31) & 0x01;
|
||
|
if (sign != temp31) {
|
||
|
set_DSPControl_overflow_flag(1, 23, env);
|
||
|
}
|
||
|
|
||
|
return temp;
|
||
|
}
|
||
|
|
||
|
/* 128 bits long. p[0] is LO, p[1] is HI. */
|
||
|
static inline void mipsdsp_rndrashift_short_acc(int64_t *p,
|
||
|
int32_t ac,
|
||
|
int32_t shift,
|
||
|
CPUMIPSState *env)
|
||
|
{
|
||
|
int64_t acc;
|
||
|
|
||
|
acc = ((int64_t)env->active_tc.HI[ac] << 32) |
|
||
|
((int64_t)env->active_tc.LO[ac] & 0xFFFFFFFF);
|
||
|
if (shift == 0) {
|
||
|
p[0] = acc << 1;
|
||
|
p[1] = (acc >> 63) & 0x01;
|
||
|
} else {
|
||
|
p[0] = acc >> (shift - 1);
|
||
|
p[1] = 0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
/* 128 bits long. p[0] is LO, p[1] is HI */
|
||
|
static inline void mipsdsp_rashift_acc(uint64_t *p,
|
||
|
uint32_t ac,
|
||
|
uint32_t shift,
|
||
|
CPUMIPSState *env)
|
||
|
{
|
||
|
uint64_t tempB, tempA;
|
||
|
|
||
|
tempB = env->active_tc.HI[ac];
|
||
|
tempA = env->active_tc.LO[ac];
|
||
|
shift = shift & 0x1F;
|
||
|
|
||
|
if (shift == 0) {
|
||
|
p[1] = tempB;
|
||
|
p[0] = tempA;
|
||
|
} else {
|
||
|
p[0] = (tempB << (64 - shift)) | (tempA >> shift);
|
||
|
p[1] = (int64_t)tempB >> shift;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
/* 128 bits long. p[0] is LO, p[1] is HI , p[2] is sign of HI.*/
|
||
|
static inline void mipsdsp_rndrashift_acc(uint64_t *p,
|
||
|
uint32_t ac,
|
||
|
uint32_t shift,
|
||
|
CPUMIPSState *env)
|
||
|
{
|
||
|
int64_t tempB, tempA;
|
||
|
|
||
|
tempB = env->active_tc.HI[ac];
|
||
|
tempA = env->active_tc.LO[ac];
|
||
|
shift = shift & 0x3F;
|
||
|
|
||
|
if (shift == 0) {
|
||
|
p[2] = tempB >> 63;
|
||
|
p[1] = (tempB << 1) | (tempA >> 63);
|
||
|
p[0] = tempA << 1;
|
||
|
} else {
|
||
|
p[0] = (tempB << (65 - shift)) | (tempA >> (shift - 1));
|
||
|
p[1] = (int64_t)tempB >> (shift - 1);
|
||
|
if (tempB >= 0) {
|
||
|
p[2] = 0x0;
|
||
|
} else {
|
||
|
p[2] = ~0ull;
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
|
||
|
static inline int32_t mipsdsp_mul_q15_q15(int32_t ac, uint16_t a, uint16_t b,
|
||
|
CPUMIPSState *env)
|
||
|
{
|
||
|
int32_t temp;
|
||
|
|
||
|
if ((a == 0x8000) && (b == 0x8000)) {
|
||
|
temp = 0x7FFFFFFF;
|
||
|
set_DSPControl_overflow_flag(1, 16 + ac, env);
|
||
|
} else {
|
||
|
temp = ((uint32_t)a * (uint32_t)b) << 1;
|
||
|
}
|
||
|
|
||
|
return temp;
|
||
|
}
|
||
|
|
||
|
static inline int64_t mipsdsp_mul_q31_q31(int32_t ac, uint32_t a, uint32_t b,
|
||
|
CPUMIPSState *env)
|
||
|
{
|
||
|
uint64_t temp;
|
||
|
|
||
|
if ((a == 0x80000000) && (b == 0x80000000)) {
|
||
|
temp = (0x01ull << 63) - 1;
|
||
|
set_DSPControl_overflow_flag(1, 16 + ac, env);
|
||
|
} else {
|
||
|
temp = ((uint64_t)a * (uint64_t)b) << 1;
|
||
|
}
|
||
|
|
||
|
return temp;
|
||
|
}
|
||
|
|
||
|
static inline uint16_t mipsdsp_mul_u8_u8(uint8_t a, uint8_t b)
|
||
|
{
|
||
|
return (uint16_t)a * (uint16_t)b;
|
||
|
}
|
||
|
|
||
|
static inline uint16_t mipsdsp_mul_u8_u16(uint8_t a, uint16_t b,
|
||
|
CPUMIPSState *env)
|
||
|
{
|
||
|
uint32_t tempI;
|
||
|
|
||
|
tempI = (uint32_t)a * (uint32_t)b;
|
||
|
if (tempI > 0x0000FFFF) {
|
||
|
tempI = 0x0000FFFF;
|
||
|
set_DSPControl_overflow_flag(1, 21, env);
|
||
|
}
|
||
|
|
||
|
return tempI & 0x0000FFFF;
|
||
|
}
|
||
|
|
||
|
static inline uint64_t mipsdsp_mul_u32_u32(uint32_t a, uint32_t b)
|
||
|
{
|
||
|
return (uint64_t)a * (uint64_t)b;
|
||
|
}
|
||
|
|
||
|
static inline int16_t mipsdsp_rndq15_mul_q15_q15(uint16_t a, uint16_t b,
|
||
|
CPUMIPSState *env)
|
||
|
{
|
||
|
uint32_t temp;
|
||
|
|
||
|
if ((a == 0x8000) && (b == 0x8000)) {
|
||
|
temp = 0x7FFF0000;
|
||
|
set_DSPControl_overflow_flag(1, 21, env);
|
||
|
} else {
|
||
|
temp = (a * b) << 1;
|
||
|
temp = temp + 0x00008000;
|
||
|
}
|
||
|
|
||
|
return (temp & 0xFFFF0000) >> 16;
|
||
|
}
|
||
|
|
||
|
static inline int32_t mipsdsp_sat16_mul_q15_q15(uint16_t a, uint16_t b,
|
||
|
CPUMIPSState *env)
|
||
|
{
|
||
|
int32_t temp;
|
||
|
|
||
|
if ((a == 0x8000) && (b == 0x8000)) {
|
||
|
temp = 0x7FFF0000;
|
||
|
set_DSPControl_overflow_flag(1, 21, env);
|
||
|
} else {
|
||
|
temp = ((uint32_t)a * (uint32_t)b);
|
||
|
temp = temp << 1;
|
||
|
}
|
||
|
|
||
|
return (temp >> 16) & 0x0000FFFF;
|
||
|
}
|
||
|
|
||
|
static inline uint16_t mipsdsp_trunc16_sat16_round(int32_t a,
|
||
|
CPUMIPSState *env)
|
||
|
{
|
||
|
int64_t temp;
|
||
|
|
||
|
temp = (int32_t)a + 0x00008000;
|
||
|
|
||
|
if (a > (int)0x7fff8000) {
|
||
|
temp = 0x7FFFFFFF;
|
||
|
set_DSPControl_overflow_flag(1, 22, env);
|
||
|
}
|
||
|
|
||
|
return (temp >> 16) & 0xFFFF;
|
||
|
}
|
||
|
|
||
|
static inline uint8_t mipsdsp_sat8_reduce_precision(uint16_t a,
|
||
|
CPUMIPSState *env)
|
||
|
{
|
||
|
uint16_t mag;
|
||
|
uint32_t sign;
|
||
|
|
||
|
sign = (a >> 15) & 0x01;
|
||
|
mag = a & 0x7FFF;
|
||
|
|
||
|
if (sign == 0) {
|
||
|
if (mag > 0x7F80) {
|
||
|
set_DSPControl_overflow_flag(1, 22, env);
|
||
|
return 0xFF;
|
||
|
} else {
|
||
|
return (mag >> 7) & 0xFFFF;
|
||
|
}
|
||
|
} else {
|
||
|
set_DSPControl_overflow_flag(1, 22, env);
|
||
|
return 0x00;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
static inline uint8_t mipsdsp_lshift8(uint8_t a, uint8_t s, CPUMIPSState *env)
|
||
|
{
|
||
|
uint8_t sign;
|
||
|
uint8_t discard;
|
||
|
|
||
|
if (s == 0) {
|
||
|
return a;
|
||
|
} else {
|
||
|
sign = (a >> 7) & 0x01;
|
||
|
if (sign != 0) {
|
||
|
discard = (((0x01 << (8 - s)) - 1) << s) |
|
||
|
((a >> (6 - (s - 1))) & ((0x01 << s) - 1));
|
||
|
} else {
|
||
|
discard = a >> (6 - (s - 1));
|
||
|
}
|
||
|
|
||
|
if (discard != 0x00) {
|
||
|
set_DSPControl_overflow_flag(1, 22, env);
|
||
|
}
|
||
|
return a << s;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
static inline uint16_t mipsdsp_lshift16(uint16_t a, uint8_t s,
|
||
|
CPUMIPSState *env)
|
||
|
{
|
||
|
uint8_t sign;
|
||
|
uint16_t discard;
|
||
|
|
||
|
if (s == 0) {
|
||
|
return a;
|
||
|
} else {
|
||
|
sign = (a >> 15) & 0x01;
|
||
|
if (sign != 0) {
|
||
|
discard = (((0x01 << (16 - s)) - 1) << s) |
|
||
|
((a >> (14 - (s - 1))) & ((0x01 << s) - 1));
|
||
|
} else {
|
||
|
discard = a >> (14 - (s - 1));
|
||
|
}
|
||
|
|
||
|
if ((discard != 0x0000) && (discard != 0xFFFF)) {
|
||
|
set_DSPControl_overflow_flag(1, 22, env);
|
||
|
}
|
||
|
return a << s;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
|
||
|
static inline uint32_t mipsdsp_lshift32(uint32_t a, uint8_t s,
|
||
|
CPUMIPSState *env)
|
||
|
{
|
||
|
uint32_t discard;
|
||
|
|
||
|
if (s == 0) {
|
||
|
return a;
|
||
|
} else {
|
||
|
discard = (int32_t)a >> (31 - (s - 1));
|
||
|
|
||
|
if ((discard != 0x00000000) && (discard != 0xFFFFFFFF)) {
|
||
|
set_DSPControl_overflow_flag(1, 22, env);
|
||
|
}
|
||
|
return a << s;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
static inline uint16_t mipsdsp_sat16_lshift(uint16_t a, uint8_t s,
|
||
|
CPUMIPSState *env)
|
||
|
{
|
||
|
uint8_t sign;
|
||
|
uint16_t discard;
|
||
|
|
||
|
if (s == 0) {
|
||
|
return a;
|
||
|
} else {
|
||
|
sign = (a >> 15) & 0x01;
|
||
|
if (sign != 0) {
|
||
|
discard = (((0x01 << (16 - s)) - 1) << s) |
|
||
|
((a >> (14 - (s - 1))) & ((0x01 << s) - 1));
|
||
|
} else {
|
||
|
discard = a >> (14 - (s - 1));
|
||
|
}
|
||
|
|
||
|
if ((discard != 0x0000) && (discard != 0xFFFF)) {
|
||
|
set_DSPControl_overflow_flag(1, 22, env);
|
||
|
return (sign == 0) ? 0x7FFF : 0x8000;
|
||
|
} else {
|
||
|
return a << s;
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
|
||
|
static inline uint32_t mipsdsp_sat32_lshift(uint32_t a, uint8_t s,
|
||
|
CPUMIPSState *env)
|
||
|
{
|
||
|
uint8_t sign;
|
||
|
uint32_t discard;
|
||
|
|
||
|
if (s == 0) {
|
||
|
return a;
|
||
|
} else {
|
||
|
sign = (a >> 31) & 0x01;
|
||
|
if (sign != 0) {
|
||
|
discard = (((0x01 << (32 - s)) - 1) << s) |
|
||
|
((a >> (30 - (s - 1))) & ((0x01 << s) - 1));
|
||
|
} else {
|
||
|
discard = a >> (30 - (s - 1));
|
||
|
}
|
||
|
|
||
|
if ((discard != 0x00000000) && (discard != 0xFFFFFFFF)) {
|
||
|
set_DSPControl_overflow_flag(1, 22, env);
|
||
|
return (sign == 0) ? 0x7FFFFFFF : 0x80000000;
|
||
|
} else {
|
||
|
return a << s;
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
|
||
|
static inline uint8_t mipsdsp_rnd8_rashift(uint8_t a, uint8_t s)
|
||
|
{
|
||
|
uint32_t temp;
|
||
|
|
||
|
if (s == 0) {
|
||
|
temp = (uint32_t)a << 1;
|
||
|
} else {
|
||
|
temp = (int32_t)(int8_t)a >> (s - 1);
|
||
|
}
|
||
|
|
||
|
return (temp + 1) >> 1;
|
||
|
}
|
||
|
|
||
|
static inline uint16_t mipsdsp_rnd16_rashift(uint16_t a, uint8_t s)
|
||
|
{
|
||
|
uint32_t temp;
|
||
|
|
||
|
if (s == 0) {
|
||
|
temp = (uint32_t)a << 1;
|
||
|
} else {
|
||
|
temp = (int32_t)(int16_t)a >> (s - 1);
|
||
|
}
|
||
|
|
||
|
return (temp + 1) >> 1;
|
||
|
}
|
||
|
|
||
|
static inline uint32_t mipsdsp_rnd32_rashift(uint32_t a, uint8_t s)
|
||
|
{
|
||
|
int64_t temp;
|
||
|
|
||
|
if (s == 0) {
|
||
|
temp = (uint64_t)a << 1;
|
||
|
} else {
|
||
|
temp = (int64_t)(int32_t)a >> (s - 1);
|
||
|
}
|
||
|
temp += 1;
|
||
|
|
||
|
return (temp >> 1) & 0xFFFFFFFFull;
|
||
|
}
|
||
|
|
||
|
static inline uint16_t mipsdsp_sub_i16(int16_t a, int16_t b, CPUMIPSState *env)
|
||
|
{
|
||
|
int16_t temp;
|
||
|
|
||
|
temp = a - b;
|
||
|
if (MIPSDSP_OVERFLOW(a, -b, temp, 0x8000)) {
|
||
|
set_DSPControl_overflow_flag(1, 20, env);
|
||
|
}
|
||
|
|
||
|
return temp;
|
||
|
}
|
||
|
|
||
|
static inline uint16_t mipsdsp_sat16_sub(int16_t a, int16_t b,
|
||
|
CPUMIPSState *env)
|
||
|
{
|
||
|
int16_t temp;
|
||
|
|
||
|
temp = a - b;
|
||
|
if (MIPSDSP_OVERFLOW(a, -b, temp, 0x8000)) {
|
||
|
if (a > 0) {
|
||
|
temp = 0x7FFF;
|
||
|
} else {
|
||
|
temp = 0x8000;
|
||
|
}
|
||
|
set_DSPControl_overflow_flag(1, 20, env);
|
||
|
}
|
||
|
|
||
|
return temp;
|
||
|
}
|
||
|
|
||
|
static inline uint32_t mipsdsp_sat32_sub(int32_t a, int32_t b,
|
||
|
CPUMIPSState *env)
|
||
|
{
|
||
|
int32_t temp;
|
||
|
|
||
|
temp = a - b;
|
||
|
if (MIPSDSP_OVERFLOW(a, -b, temp, 0x80000000)) {
|
||
|
if (a > 0) {
|
||
|
temp = 0x7FFFFFFF;
|
||
|
} else {
|
||
|
temp = 0x80000000;
|
||
|
}
|
||
|
set_DSPControl_overflow_flag(1, 20, env);
|
||
|
}
|
||
|
|
||
|
return temp & 0xFFFFFFFFull;
|
||
|
}
|
||
|
|
||
|
static inline uint16_t mipsdsp_rshift1_sub_q16(int16_t a, int16_t b)
|
||
|
{
|
||
|
int32_t temp;
|
||
|
|
||
|
temp = (int32_t)a - (int32_t)b;
|
||
|
|
||
|
return (temp >> 1) & 0x0000FFFF;
|
||
|
}
|
||
|
|
||
|
static inline uint16_t mipsdsp_rrshift1_sub_q16(int16_t a, int16_t b)
|
||
|
{
|
||
|
int32_t temp;
|
||
|
|
||
|
temp = (int32_t)a - (int32_t)b;
|
||
|
temp += 1;
|
||
|
|
||
|
return (temp >> 1) & 0x0000FFFF;
|
||
|
}
|
||
|
|
||
|
static inline uint32_t mipsdsp_rshift1_sub_q32(int32_t a, int32_t b)
|
||
|
{
|
||
|
int64_t temp;
|
||
|
|
||
|
temp = (int64_t)a - (int64_t)b;
|
||
|
|
||
|
return (temp >> 1) & 0xFFFFFFFFull;
|
||
|
}
|
||
|
|
||
|
static inline uint32_t mipsdsp_rrshift1_sub_q32(int32_t a, int32_t b)
|
||
|
{
|
||
|
int64_t temp;
|
||
|
|
||
|
temp = (int64_t)a - (int64_t)b;
|
||
|
temp += 1;
|
||
|
|
||
|
return (temp >> 1) & 0xFFFFFFFFull;
|
||
|
}
|
||
|
|
||
|
static inline uint16_t mipsdsp_sub_u16_u16(uint16_t a, uint16_t b,
|
||
|
CPUMIPSState *env)
|
||
|
{
|
||
|
uint8_t temp16;
|
||
|
uint32_t temp;
|
||
|
|
||
|
temp = (uint32_t)a - (uint32_t)b;
|
||
|
temp16 = (temp >> 16) & 0x01;
|
||
|
if (temp16 == 1) {
|
||
|
set_DSPControl_overflow_flag(1, 20, env);
|
||
|
}
|
||
|
return temp & 0x0000FFFF;
|
||
|
}
|
||
|
|
||
|
static inline uint16_t mipsdsp_satu16_sub_u16_u16(uint16_t a, uint16_t b,
|
||
|
CPUMIPSState *env)
|
||
|
{
|
||
|
uint8_t temp16;
|
||
|
uint32_t temp;
|
||
|
|
||
|
temp = (uint32_t)a - (uint32_t)b;
|
||
|
temp16 = (temp >> 16) & 0x01;
|
||
|
|
||
|
if (temp16 == 1) {
|
||
|
temp = 0x0000;
|
||
|
set_DSPControl_overflow_flag(1, 20, env);
|
||
|
}
|
||
|
|
||
|
return temp & 0x0000FFFF;
|
||
|
}
|
||
|
|
||
|
static inline uint8_t mipsdsp_sub_u8(uint8_t a, uint8_t b, CPUMIPSState *env)
|
||
|
{
|
||
|
uint8_t temp8;
|
||
|
uint16_t temp;
|
||
|
|
||
|
temp = (uint16_t)a - (uint16_t)b;
|
||
|
temp8 = (temp >> 8) & 0x01;
|
||
|
if (temp8 == 1) {
|
||
|
set_DSPControl_overflow_flag(1, 20, env);
|
||
|
}
|
||
|
|
||
|
return temp & 0x00FF;
|
||
|
}
|
||
|
|
||
|
static inline uint8_t mipsdsp_satu8_sub(uint8_t a, uint8_t b, CPUMIPSState *env)
|
||
|
{
|
||
|
uint8_t temp8;
|
||
|
uint16_t temp;
|
||
|
|
||
|
temp = (uint16_t)a - (uint16_t)b;
|
||
|
temp8 = (temp >> 8) & 0x01;
|
||
|
if (temp8 == 1) {
|
||
|
temp = 0x00;
|
||
|
set_DSPControl_overflow_flag(1, 20, env);
|
||
|
}
|
||
|
|
||
|
return temp & 0x00FF;
|
||
|
}
|
||
|
|
||
|
static inline uint32_t mipsdsp_sub32(int32_t a, int32_t b, CPUMIPSState *env)
|
||
|
{
|
||
|
int32_t temp;
|
||
|
|
||
|
temp = a - b;
|
||
|
if (MIPSDSP_OVERFLOW(a, -b, temp, 0x80000000)) {
|
||
|
set_DSPControl_overflow_flag(1, 20, env);
|
||
|
}
|
||
|
|
||
|
return temp;
|
||
|
}
|
||
|
|
||
|
static inline int32_t mipsdsp_add_i32(int32_t a, int32_t b, CPUMIPSState *env)
|
||
|
{
|
||
|
int32_t temp;
|
||
|
|
||
|
temp = a + b;
|
||
|
|
||
|
if (MIPSDSP_OVERFLOW(a, b, temp, 0x80000000)) {
|
||
|
set_DSPControl_overflow_flag(1, 20, env);
|
||
|
}
|
||
|
|
||
|
return temp;
|
||
|
}
|
||
|
|
||
|
static inline int32_t mipsdsp_cmp_eq(int32_t a, int32_t b)
|
||
|
{
|
||
|
return a == b;
|
||
|
}
|
||
|
|
||
|
static inline int32_t mipsdsp_cmp_le(int32_t a, int32_t b)
|
||
|
{
|
||
|
return a <= b;
|
||
|
}
|
||
|
|
||
|
static inline int32_t mipsdsp_cmp_lt(int32_t a, int32_t b)
|
||
|
{
|
||
|
return a < b;
|
||
|
}
|
||
|
|
||
|
static inline int32_t mipsdsp_cmpu_eq(uint32_t a, uint32_t b)
|
||
|
{
|
||
|
return a == b;
|
||
|
}
|
||
|
|
||
|
static inline int32_t mipsdsp_cmpu_le(uint32_t a, uint32_t b)
|
||
|
{
|
||
|
return a <= b;
|
||
|
}
|
||
|
|
||
|
static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b)
|
||
|
{
|
||
|
return a < b;
|
||
|
}
|
||
|
/*** MIPS DSP internal functions end ***/
|