2011-10-16 11:16:36 +02:00
|
|
|
/*
|
|
|
|
* APIC support - common bits of emulated and KVM kernel model
|
|
|
|
*
|
|
|
|
* Copyright (c) 2004-2005 Fabrice Bellard
|
|
|
|
* Copyright (c) 2011 Jan Kiszka, Siemens AG
|
|
|
|
*
|
|
|
|
* This library is free software; you can redistribute it and/or
|
|
|
|
* modify it under the terms of the GNU Lesser General Public
|
|
|
|
* License as published by the Free Software Foundation; either
|
|
|
|
* version 2 of the License, or (at your option) any later version.
|
|
|
|
*
|
|
|
|
* This library is distributed in the hope that it will be useful,
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
|
|
* Lesser General Public License for more details.
|
|
|
|
*
|
|
|
|
* You should have received a copy of the GNU Lesser General Public
|
|
|
|
* License along with this library; if not, see <http://www.gnu.org/licenses/>
|
|
|
|
*/
|
2016-01-26 19:17:03 +01:00
|
|
|
#include "qemu/osdep.h"
|
2013-02-05 17:06:20 +01:00
|
|
|
#include "hw/i386/apic.h"
|
|
|
|
#include "hw/i386/apic_internal.h"
|
2011-10-16 11:16:36 +02:00
|
|
|
#include "trace.h"
|
2012-12-17 18:20:04 +01:00
|
|
|
#include "sysemu/kvm.h"
|
2013-04-29 19:03:01 +02:00
|
|
|
#include "hw/qdev.h"
|
|
|
|
#include "hw/sysbus.h"
|
2011-10-16 11:16:36 +02:00
|
|
|
|
|
|
|
static int apic_irq_delivered;
|
2012-02-17 18:31:19 +01:00
|
|
|
bool apic_report_tpr_access;
|
2011-10-16 11:16:36 +02:00
|
|
|
|
2013-11-05 11:16:02 +01:00
|
|
|
void cpu_set_apic_base(DeviceState *dev, uint64_t val)
|
2011-10-16 11:16:36 +02:00
|
|
|
{
|
|
|
|
trace_cpu_set_apic_base(val);
|
|
|
|
|
2013-11-05 11:16:02 +01:00
|
|
|
if (dev) {
|
|
|
|
APICCommonState *s = APIC_COMMON(dev);
|
2012-01-24 20:12:29 +01:00
|
|
|
APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
|
2011-10-16 11:16:36 +02:00
|
|
|
info->set_base(s, val);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-11-05 11:16:02 +01:00
|
|
|
uint64_t cpu_get_apic_base(DeviceState *dev)
|
2011-10-16 11:16:36 +02:00
|
|
|
{
|
2013-11-05 11:16:02 +01:00
|
|
|
if (dev) {
|
|
|
|
APICCommonState *s = APIC_COMMON(dev);
|
2012-01-24 20:12:29 +01:00
|
|
|
trace_cpu_get_apic_base((uint64_t)s->apicbase);
|
|
|
|
return s->apicbase;
|
|
|
|
} else {
|
2012-07-23 15:22:27 +02:00
|
|
|
trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP);
|
|
|
|
return MSR_IA32_APICBASE_BSP;
|
2012-01-24 20:12:29 +01:00
|
|
|
}
|
2011-10-16 11:16:36 +02:00
|
|
|
}
|
|
|
|
|
2013-11-05 11:16:02 +01:00
|
|
|
void cpu_set_apic_tpr(DeviceState *dev, uint8_t val)
|
2011-10-16 11:16:36 +02:00
|
|
|
{
|
2012-01-24 20:12:29 +01:00
|
|
|
APICCommonState *s;
|
|
|
|
APICCommonClass *info;
|
2011-10-16 11:16:36 +02:00
|
|
|
|
2013-11-05 11:16:02 +01:00
|
|
|
if (!dev) {
|
2012-01-24 20:12:29 +01:00
|
|
|
return;
|
2011-10-16 11:16:36 +02:00
|
|
|
}
|
2012-01-24 20:12:29 +01:00
|
|
|
|
2013-11-05 11:16:02 +01:00
|
|
|
s = APIC_COMMON(dev);
|
2012-01-24 20:12:29 +01:00
|
|
|
info = APIC_COMMON_GET_CLASS(s);
|
|
|
|
|
|
|
|
info->set_tpr(s, val);
|
2011-10-16 11:16:36 +02:00
|
|
|
}
|
|
|
|
|
2013-11-05 11:16:02 +01:00
|
|
|
uint8_t cpu_get_apic_tpr(DeviceState *dev)
|
2012-02-17 18:31:19 +01:00
|
|
|
{
|
|
|
|
APICCommonState *s;
|
|
|
|
APICCommonClass *info;
|
|
|
|
|
2013-11-05 11:16:02 +01:00
|
|
|
if (!dev) {
|
2012-02-17 18:31:19 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-11-05 11:16:02 +01:00
|
|
|
s = APIC_COMMON(dev);
|
2012-02-17 18:31:19 +01:00
|
|
|
info = APIC_COMMON_GET_CLASS(s);
|
|
|
|
|
|
|
|
return info->get_tpr(s);
|
|
|
|
}
|
|
|
|
|
2013-11-05 11:16:02 +01:00
|
|
|
void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable)
|
2012-02-17 18:31:19 +01:00
|
|
|
{
|
2013-11-05 11:16:02 +01:00
|
|
|
APICCommonState *s = APIC_COMMON(dev);
|
2012-02-17 18:31:19 +01:00
|
|
|
APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
|
|
|
|
|
|
|
|
apic_report_tpr_access = enable;
|
|
|
|
if (info->enable_tpr_reporting) {
|
|
|
|
info->enable_tpr_reporting(s, enable);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-11-05 11:16:02 +01:00
|
|
|
void apic_enable_vapic(DeviceState *dev, hwaddr paddr)
|
2011-10-16 11:16:36 +02:00
|
|
|
{
|
2013-11-05 11:16:02 +01:00
|
|
|
APICCommonState *s = APIC_COMMON(dev);
|
2012-02-17 18:31:19 +01:00
|
|
|
APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
|
2011-10-16 11:16:36 +02:00
|
|
|
|
2012-02-17 18:31:19 +01:00
|
|
|
s->vapic_paddr = paddr;
|
|
|
|
info->vapic_base_update(s);
|
2011-10-16 11:16:36 +02:00
|
|
|
}
|
|
|
|
|
2013-11-05 11:16:02 +01:00
|
|
|
void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip,
|
2012-02-17 18:31:17 +01:00
|
|
|
TPRAccess access)
|
|
|
|
{
|
2013-11-05 11:16:02 +01:00
|
|
|
APICCommonState *s = APIC_COMMON(dev);
|
2012-02-17 18:31:19 +01:00
|
|
|
|
2013-01-16 19:29:31 +01:00
|
|
|
vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access);
|
2012-02-17 18:31:17 +01:00
|
|
|
}
|
|
|
|
|
2011-10-16 11:16:36 +02:00
|
|
|
void apic_report_irq_delivered(int delivered)
|
|
|
|
{
|
|
|
|
apic_irq_delivered += delivered;
|
|
|
|
|
|
|
|
trace_apic_report_irq_delivered(apic_irq_delivered);
|
|
|
|
}
|
|
|
|
|
|
|
|
void apic_reset_irq_delivered(void)
|
|
|
|
{
|
2014-03-25 13:08:30 +01:00
|
|
|
/* Copy this into a local variable to encourage gcc to emit a plain
|
|
|
|
* register for a sys/sdt.h marker. For details on this workaround, see:
|
|
|
|
* https://sourceware.org/bugzilla/show_bug.cgi?id=13296
|
|
|
|
*/
|
|
|
|
volatile int a_i_d = apic_irq_delivered;
|
|
|
|
trace_apic_reset_irq_delivered(a_i_d);
|
2011-10-16 11:16:36 +02:00
|
|
|
|
|
|
|
apic_irq_delivered = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int apic_get_irq_delivered(void)
|
|
|
|
{
|
|
|
|
trace_apic_get_irq_delivered(apic_irq_delivered);
|
|
|
|
|
|
|
|
return apic_irq_delivered;
|
|
|
|
}
|
|
|
|
|
2013-11-05 11:16:02 +01:00
|
|
|
void apic_deliver_nmi(DeviceState *dev)
|
2011-10-16 11:16:36 +02:00
|
|
|
{
|
2013-11-05 11:16:02 +01:00
|
|
|
APICCommonState *s = APIC_COMMON(dev);
|
2012-01-24 20:12:29 +01:00
|
|
|
APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
|
2011-10-16 11:16:36 +02:00
|
|
|
|
|
|
|
info->external_nmi(s);
|
|
|
|
}
|
|
|
|
|
2011-10-16 12:19:12 +02:00
|
|
|
bool apic_next_timer(APICCommonState *s, int64_t current_time)
|
|
|
|
{
|
|
|
|
int64_t d;
|
|
|
|
|
|
|
|
/* We need to store the timer state separately to support APIC
|
|
|
|
* implementations that maintain a non-QEMU timer, e.g. inside the
|
|
|
|
* host kernel. This open-coded state allows us to migrate between
|
|
|
|
* both models. */
|
|
|
|
s->timer_expiry = -1;
|
|
|
|
|
|
|
|
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
d = (current_time - s->initial_count_load_time) >> s->count_shift;
|
|
|
|
|
|
|
|
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
|
|
|
if (!s->initial_count) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
|
|
|
|
((uint64_t)s->initial_count + 1);
|
|
|
|
} else {
|
|
|
|
if (d >= s->initial_count) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
d = (uint64_t)s->initial_count + 1;
|
|
|
|
}
|
|
|
|
s->next_time = s->initial_count_load_time + (d << s->count_shift);
|
|
|
|
s->timer_expiry = s->next_time;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-11-05 11:16:02 +01:00
|
|
|
void apic_init_reset(DeviceState *dev)
|
2011-10-16 11:16:36 +02:00
|
|
|
{
|
2015-01-20 11:07:09 +01:00
|
|
|
APICCommonState *s;
|
|
|
|
APICCommonClass *info;
|
2011-10-16 11:16:36 +02:00
|
|
|
int i;
|
|
|
|
|
2015-01-20 11:07:09 +01:00
|
|
|
if (!dev) {
|
2011-10-16 11:16:36 +02:00
|
|
|
return;
|
|
|
|
}
|
2015-01-20 11:07:09 +01:00
|
|
|
s = APIC_COMMON(dev);
|
2011-10-16 11:16:36 +02:00
|
|
|
s->tpr = 0;
|
|
|
|
s->spurious_vec = 0xff;
|
|
|
|
s->log_dest = 0;
|
|
|
|
s->dest_mode = 0xf;
|
|
|
|
memset(s->isr, 0, sizeof(s->isr));
|
|
|
|
memset(s->tmr, 0, sizeof(s->tmr));
|
|
|
|
memset(s->irr, 0, sizeof(s->irr));
|
|
|
|
for (i = 0; i < APIC_LVT_NB; i++) {
|
|
|
|
s->lvt[i] = APIC_LVT_MASKED;
|
|
|
|
}
|
|
|
|
s->esr = 0;
|
|
|
|
memset(s->icr, 0, sizeof(s->icr));
|
|
|
|
s->divide_conf = 0;
|
|
|
|
s->count_shift = 0;
|
|
|
|
s->initial_count = 0;
|
|
|
|
s->initial_count_load_time = 0;
|
|
|
|
s->next_time = 0;
|
2013-03-19 14:17:18 +01:00
|
|
|
s->wait_for_sipi = !cpu_is_bsp(s->cpu);
|
2011-10-16 11:16:36 +02:00
|
|
|
|
2011-10-16 12:19:12 +02:00
|
|
|
if (s->timer) {
|
2013-08-21 17:03:08 +02:00
|
|
|
timer_del(s->timer);
|
2011-10-16 12:19:12 +02:00
|
|
|
}
|
|
|
|
s->timer_expiry = -1;
|
2014-12-10 16:56:46 +01:00
|
|
|
|
2015-01-20 11:07:09 +01:00
|
|
|
info = APIC_COMMON_GET_CLASS(s);
|
2014-12-10 16:56:46 +01:00
|
|
|
if (info->reset) {
|
|
|
|
info->reset(s);
|
|
|
|
}
|
2011-10-16 11:16:36 +02:00
|
|
|
}
|
|
|
|
|
2015-04-02 01:58:36 +02:00
|
|
|
void apic_designate_bsp(DeviceState *dev, bool bsp)
|
2012-07-23 15:22:27 +02:00
|
|
|
{
|
2013-11-05 11:16:02 +01:00
|
|
|
if (dev == NULL) {
|
2012-07-23 15:22:27 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2013-11-05 11:16:02 +01:00
|
|
|
APICCommonState *s = APIC_COMMON(dev);
|
2015-04-02 01:58:36 +02:00
|
|
|
if (bsp) {
|
|
|
|
s->apicbase |= MSR_IA32_APICBASE_BSP;
|
|
|
|
} else {
|
|
|
|
s->apicbase &= ~MSR_IA32_APICBASE_BSP;
|
|
|
|
}
|
2012-07-23 15:22:27 +02:00
|
|
|
}
|
|
|
|
|
2013-11-05 11:16:02 +01:00
|
|
|
static void apic_reset_common(DeviceState *dev)
|
2011-10-16 11:16:36 +02:00
|
|
|
{
|
2013-11-05 11:16:02 +01:00
|
|
|
APICCommonState *s = APIC_COMMON(dev);
|
2012-02-17 18:31:19 +01:00
|
|
|
APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
|
2015-04-07 15:53:52 +02:00
|
|
|
uint32_t bsp;
|
2011-10-16 11:16:36 +02:00
|
|
|
|
2015-04-07 15:53:52 +02:00
|
|
|
bsp = s->apicbase & MSR_IA32_APICBASE_BSP;
|
|
|
|
s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE;
|
2011-10-16 11:16:36 +02:00
|
|
|
|
2012-02-17 18:31:19 +01:00
|
|
|
s->vapic_paddr = 0;
|
|
|
|
info->vapic_base_update(s);
|
|
|
|
|
2013-11-05 11:16:02 +01:00
|
|
|
apic_init_reset(dev);
|
2011-10-16 11:16:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* This function is only used for old state version 1 and 2 */
|
|
|
|
static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
|
|
|
|
{
|
|
|
|
APICCommonState *s = opaque;
|
2012-02-05 12:45:20 +01:00
|
|
|
APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
|
2011-10-16 11:16:36 +02:00
|
|
|
int i;
|
|
|
|
|
|
|
|
if (version_id > 2) {
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* XXX: what if the base changes? (registered memory regions) */
|
|
|
|
qemu_get_be32s(f, &s->apicbase);
|
|
|
|
qemu_get_8s(f, &s->id);
|
|
|
|
qemu_get_8s(f, &s->arb_id);
|
|
|
|
qemu_get_8s(f, &s->tpr);
|
|
|
|
qemu_get_be32s(f, &s->spurious_vec);
|
|
|
|
qemu_get_8s(f, &s->log_dest);
|
|
|
|
qemu_get_8s(f, &s->dest_mode);
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
qemu_get_be32s(f, &s->isr[i]);
|
|
|
|
qemu_get_be32s(f, &s->tmr[i]);
|
|
|
|
qemu_get_be32s(f, &s->irr[i]);
|
|
|
|
}
|
|
|
|
for (i = 0; i < APIC_LVT_NB; i++) {
|
|
|
|
qemu_get_be32s(f, &s->lvt[i]);
|
|
|
|
}
|
|
|
|
qemu_get_be32s(f, &s->esr);
|
|
|
|
qemu_get_be32s(f, &s->icr[0]);
|
|
|
|
qemu_get_be32s(f, &s->icr[1]);
|
|
|
|
qemu_get_be32s(f, &s->divide_conf);
|
|
|
|
s->count_shift = qemu_get_be32(f);
|
|
|
|
qemu_get_be32s(f, &s->initial_count);
|
|
|
|
s->initial_count_load_time = qemu_get_be64(f);
|
|
|
|
s->next_time = qemu_get_be64(f);
|
|
|
|
|
|
|
|
if (version_id >= 2) {
|
2012-02-05 12:45:20 +01:00
|
|
|
s->timer_expiry = qemu_get_be64(f);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (info->post_load) {
|
|
|
|
info->post_load(s);
|
2011-10-16 11:16:36 +02:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-12-18 18:21:46 +01:00
|
|
|
static void apic_common_realize(DeviceState *dev, Error **errp)
|
2011-10-16 11:16:36 +02:00
|
|
|
{
|
2012-01-24 20:12:29 +01:00
|
|
|
APICCommonState *s = APIC_COMMON(dev);
|
|
|
|
APICCommonClass *info;
|
2012-02-17 18:31:19 +01:00
|
|
|
static DeviceState *vapic;
|
2011-10-16 11:16:36 +02:00
|
|
|
static int apic_no;
|
|
|
|
|
|
|
|
if (apic_no >= MAX_APICS) {
|
2013-12-18 18:21:46 +01:00
|
|
|
error_setg(errp, "%s initialization failed.",
|
|
|
|
object_get_typename(OBJECT(dev)));
|
|
|
|
return;
|
2011-10-16 11:16:36 +02:00
|
|
|
}
|
|
|
|
s->idx = apic_no++;
|
|
|
|
|
2012-01-24 20:12:29 +01:00
|
|
|
info = APIC_COMMON_GET_CLASS(s);
|
2013-12-18 18:21:46 +01:00
|
|
|
info->realize(dev, errp);
|
2012-02-17 18:31:19 +01:00
|
|
|
|
2012-08-14 13:43:12 +02:00
|
|
|
/* Note: We need at least 1M to map the VAPIC option ROM */
|
|
|
|
if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
|
|
|
|
ram_size >= 1024 * 1024) {
|
2012-02-17 18:31:19 +01:00
|
|
|
vapic = sysbus_create_simple("kvmvapic", -1, NULL);
|
|
|
|
}
|
|
|
|
s->vapic = vapic;
|
|
|
|
if (apic_report_tpr_access && info->enable_tpr_reporting) {
|
|
|
|
info->enable_tpr_reporting(s, true);
|
|
|
|
}
|
|
|
|
|
2011-10-16 11:16:36 +02:00
|
|
|
}
|
|
|
|
|
2014-08-28 13:18:57 +02:00
|
|
|
static int apic_pre_load(void *opaque)
|
|
|
|
{
|
|
|
|
APICCommonState *s = APIC_COMMON(opaque);
|
|
|
|
|
|
|
|
/* The default is !cpu_is_bsp(s->cpu), but the common value is 0
|
|
|
|
* so that's what apic_common_sipi_needed checks for. Reset to
|
|
|
|
* the value that is assumed when the apic_sipi subsection is
|
|
|
|
* absent.
|
|
|
|
*/
|
|
|
|
s->wait_for_sipi = 0;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-02-17 18:31:19 +01:00
|
|
|
static void apic_dispatch_pre_save(void *opaque)
|
|
|
|
{
|
|
|
|
APICCommonState *s = APIC_COMMON(opaque);
|
|
|
|
APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
|
|
|
|
|
|
|
|
if (info->pre_save) {
|
|
|
|
info->pre_save(s);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-10-16 12:19:12 +02:00
|
|
|
static int apic_dispatch_post_load(void *opaque, int version_id)
|
|
|
|
{
|
2012-01-24 20:12:29 +01:00
|
|
|
APICCommonState *s = APIC_COMMON(opaque);
|
|
|
|
APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
|
2011-10-16 12:19:12 +02:00
|
|
|
|
|
|
|
if (info->post_load) {
|
|
|
|
info->post_load(s);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-08-28 13:18:57 +02:00
|
|
|
static bool apic_common_sipi_needed(void *opaque)
|
|
|
|
{
|
|
|
|
APICCommonState *s = APIC_COMMON(opaque);
|
|
|
|
return s->wait_for_sipi != 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const VMStateDescription vmstate_apic_common_sipi = {
|
|
|
|
.name = "apic_sipi",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
2014-09-23 14:09:54 +02:00
|
|
|
.needed = apic_common_sipi_needed,
|
2014-08-28 13:18:57 +02:00
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_INT32(sipi_vector, APICCommonState),
|
|
|
|
VMSTATE_INT32(wait_for_sipi, APICCommonState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2011-10-16 11:16:36 +02:00
|
|
|
static const VMStateDescription vmstate_apic_common = {
|
|
|
|
.name = "apic",
|
|
|
|
.version_id = 3,
|
|
|
|
.minimum_version_id = 3,
|
|
|
|
.minimum_version_id_old = 1,
|
|
|
|
.load_state_old = apic_load_old,
|
2014-08-28 13:18:57 +02:00
|
|
|
.pre_load = apic_pre_load,
|
2012-02-17 18:31:19 +01:00
|
|
|
.pre_save = apic_dispatch_pre_save,
|
2011-10-16 12:19:12 +02:00
|
|
|
.post_load = apic_dispatch_post_load,
|
2011-10-16 11:16:36 +02:00
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_UINT32(apicbase, APICCommonState),
|
|
|
|
VMSTATE_UINT8(id, APICCommonState),
|
|
|
|
VMSTATE_UINT8(arb_id, APICCommonState),
|
|
|
|
VMSTATE_UINT8(tpr, APICCommonState),
|
|
|
|
VMSTATE_UINT32(spurious_vec, APICCommonState),
|
|
|
|
VMSTATE_UINT8(log_dest, APICCommonState),
|
|
|
|
VMSTATE_UINT8(dest_mode, APICCommonState),
|
|
|
|
VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
|
|
|
|
VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
|
|
|
|
VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
|
|
|
|
VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
|
|
|
|
VMSTATE_UINT32(esr, APICCommonState),
|
|
|
|
VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
|
|
|
|
VMSTATE_UINT32(divide_conf, APICCommonState),
|
|
|
|
VMSTATE_INT32(count_shift, APICCommonState),
|
|
|
|
VMSTATE_UINT32(initial_count, APICCommonState),
|
|
|
|
VMSTATE_INT64(initial_count_load_time, APICCommonState),
|
|
|
|
VMSTATE_INT64(next_time, APICCommonState),
|
2011-10-16 12:19:12 +02:00
|
|
|
VMSTATE_INT64(timer_expiry,
|
|
|
|
APICCommonState), /* open-coded timer state */
|
2011-10-16 11:16:36 +02:00
|
|
|
VMSTATE_END_OF_LIST()
|
2014-08-28 13:18:57 +02:00
|
|
|
},
|
2014-09-23 14:09:54 +02:00
|
|
|
.subsections = (const VMStateDescription*[]) {
|
|
|
|
&vmstate_apic_common_sipi,
|
|
|
|
NULL
|
2011-10-16 11:16:36 +02:00
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static Property apic_properties_common[] = {
|
|
|
|
DEFINE_PROP_UINT8("id", APICCommonState, id, -1),
|
2014-05-05 16:52:51 +02:00
|
|
|
DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14),
|
2012-02-17 18:31:19 +01:00
|
|
|
DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
|
|
|
|
true),
|
2011-10-16 11:16:36 +02:00
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
2012-01-24 20:12:29 +01:00
|
|
|
static void apic_common_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-24 20:12:29 +01:00
|
|
|
|
2011-12-08 04:34:16 +01:00
|
|
|
dc->vmsd = &vmstate_apic_common;
|
|
|
|
dc->reset = apic_reset_common;
|
|
|
|
dc->props = apic_properties_common;
|
2015-09-16 11:19:14 +02:00
|
|
|
dc->realize = apic_common_realize;
|
2013-11-28 17:26:57 +01:00
|
|
|
/*
|
|
|
|
* Reason: APIC and CPU need to be wired up by
|
|
|
|
* x86_cpu_apic_create()
|
|
|
|
*/
|
|
|
|
dc->cannot_instantiate_with_device_add_yet = true;
|
2012-01-24 20:12:29 +01:00
|
|
|
}
|
2011-10-16 11:16:36 +02:00
|
|
|
|
2013-01-10 16:19:07 +01:00
|
|
|
static const TypeInfo apic_common_type = {
|
2012-01-24 20:12:29 +01:00
|
|
|
.name = TYPE_APIC_COMMON,
|
2015-09-16 11:19:14 +02:00
|
|
|
.parent = TYPE_DEVICE,
|
2012-01-24 20:12:29 +01:00
|
|
|
.instance_size = sizeof(APICCommonState),
|
|
|
|
.class_size = sizeof(APICCommonClass),
|
|
|
|
.class_init = apic_common_class_init,
|
|
|
|
.abstract = true,
|
|
|
|
};
|
|
|
|
|
2013-11-05 11:16:02 +01:00
|
|
|
static void apic_common_register_types(void)
|
2012-01-24 20:12:29 +01:00
|
|
|
{
|
|
|
|
type_register_static(&apic_common_type);
|
|
|
|
}
|
|
|
|
|
2013-11-05 11:16:02 +01:00
|
|
|
type_init(apic_common_register_types)
|