2015-06-02 15:56:23 +02:00
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/*
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* GICv2m extension for MSI/MSI-x support with a GICv2-based system
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*
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* Copyright (C) 2015 Linaro, All rights reserved.
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*
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* Author: Christoffer Dall <christoffer.dall@linaro.org>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/* This file implements an emulated GICv2m widget as described in the ARM
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* Server Base System Architecture (SBSA) specification Version 2.2
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* (ARM-DEN-0029 v2.2) pages 35-39 without any optional implementation defined
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* identification registers and with a single non-secure MSI register frame.
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*/
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2016-01-26 19:17:05 +01:00
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#include "qemu/osdep.h"
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2015-06-02 15:56:23 +02:00
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#include "hw/sysbus.h"
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#include "hw/pci/msi.h"
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#define TYPE_ARM_GICV2M "arm-gicv2m"
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#define ARM_GICV2M(obj) OBJECT_CHECK(ARMGICv2mState, (obj), TYPE_ARM_GICV2M)
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#define GICV2M_NUM_SPI_MAX 128
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#define V2M_MSI_TYPER 0x008
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#define V2M_MSI_SETSPI_NS 0x040
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#define V2M_MSI_IIDR 0xFCC
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#define V2M_IIDR0 0xFD0
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#define V2M_IIDR11 0xFFC
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#define PRODUCT_ID_QEMU 0x51 /* ASCII code Q */
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typedef struct ARMGICv2mState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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qemu_irq spi[GICV2M_NUM_SPI_MAX];
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uint32_t base_spi;
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uint32_t num_spi;
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} ARMGICv2mState;
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static void gicv2m_set_irq(void *opaque, int irq)
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{
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ARMGICv2mState *s = (ARMGICv2mState *)opaque;
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qemu_irq_pulse(s->spi[irq]);
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}
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static uint64_t gicv2m_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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ARMGICv2mState *s = (ARMGICv2mState *)opaque;
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uint32_t val;
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if (size != 4) {
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qemu_log_mask(LOG_GUEST_ERROR, "gicv2m_read: bad size %u\n", size);
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return 0;
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}
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switch (offset) {
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case V2M_MSI_TYPER:
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val = (s->base_spi + 32) << 16;
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val |= s->num_spi;
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return val;
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case V2M_MSI_IIDR:
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/* We don't have any valid implementor so we leave that field as zero
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* and we return 0 in the arch revision as per the spec.
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*/
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return (PRODUCT_ID_QEMU << 20);
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case V2M_IIDR0 ... V2M_IIDR11:
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/* We do not implement any optional identification registers and the
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* mandatory MSI_PIDR2 register reads as 0x0, so we capture all
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* implementation defined registers here.
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*/
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return 0;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"gicv2m_read: Bad offset %x\n", (int)offset);
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return 0;
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}
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}
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static void gicv2m_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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ARMGICv2mState *s = (ARMGICv2mState *)opaque;
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if (size != 2 && size != 4) {
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qemu_log_mask(LOG_GUEST_ERROR, "gicv2m_write: bad size %u\n", size);
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return;
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}
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switch (offset) {
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case V2M_MSI_SETSPI_NS: {
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int spi;
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spi = (value & 0x3ff) - (s->base_spi + 32);
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if (spi >= 0 && spi < s->num_spi) {
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gicv2m_set_irq(s, spi);
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}
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return;
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}
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"gicv2m_write: Bad offset %x\n", (int)offset);
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}
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}
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static const MemoryRegionOps gicv2m_ops = {
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.read = gicv2m_read,
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.write = gicv2m_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void gicv2m_realize(DeviceState *dev, Error **errp)
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{
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ARMGICv2mState *s = ARM_GICV2M(dev);
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int i;
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if (s->num_spi > GICV2M_NUM_SPI_MAX) {
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error_setg(errp,
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"requested %u SPIs exceeds GICv2m frame maximum %d",
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s->num_spi, GICV2M_NUM_SPI_MAX);
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return;
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}
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if (s->base_spi + 32 > 1020 - s->num_spi) {
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error_setg(errp,
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"requested base SPI %u+%u exceeds max. number 1020",
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s->base_spi + 32, s->num_spi);
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return;
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}
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for (i = 0; i < s->num_spi; i++) {
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sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->spi[i]);
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}
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2016-03-04 10:24:28 +01:00
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msi_nonbroken = true;
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2015-06-02 15:56:23 +02:00
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kvm_gsi_direct_mapping = true;
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kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
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2015-06-02 15:56:23 +02:00
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}
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static void gicv2m_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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ARMGICv2mState *s = ARM_GICV2M(obj);
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memory_region_init_io(&s->iomem, OBJECT(s), &gicv2m_ops, s,
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"gicv2m", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static Property gicv2m_properties[] = {
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DEFINE_PROP_UINT32("base-spi", ARMGICv2mState, base_spi, 0),
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DEFINE_PROP_UINT32("num-spi", ARMGICv2mState, num_spi, 64),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void gicv2m_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->props = gicv2m_properties;
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dc->realize = gicv2m_realize;
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}
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static const TypeInfo gicv2m_info = {
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.name = TYPE_ARM_GICV2M,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(ARMGICv2mState),
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.instance_init = gicv2m_init,
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.class_init = gicv2m_class_init,
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};
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static void gicv2m_register_types(void)
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{
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type_register_static(&gicv2m_info);
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}
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type_init(gicv2m_register_types)
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