2004-05-27 00:55:16 +02:00
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/*
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2007-10-29 00:42:18 +01:00
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* QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator
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2007-09-16 23:08:06 +02:00
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*
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2007-03-30 11:38:04 +02:00
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* Copyright (c) 2004-2007 Fabrice Bellard
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2007-10-29 00:42:18 +01:00
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* Copyright (c) 2007 Jocelyn Mayer
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2007-09-16 23:08:06 +02:00
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*
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2004-05-27 00:55:16 +02:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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2010-02-09 17:37:03 +01:00
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*
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* PCI bus layout on a real G5 (U3 based):
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*
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* 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b]
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* 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150]
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* 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a]
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* 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
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* 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
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* 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045]
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* 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046]
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* 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047]
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* 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048]
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* 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049]
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* 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20)
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* 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
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* 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
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* 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
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* 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
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* 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04)
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* 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043]
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* 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042]
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* 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c]
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* 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240]
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*
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2004-05-27 00:55:16 +02:00
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*/
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2013-01-24 00:03:54 +01:00
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#include "hw/hw.h"
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2013-02-05 17:06:20 +01:00
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#include "hw/ppc/ppc.h"
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2013-01-24 00:03:54 +01:00
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#include "hw/ppc/mac.h"
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2013-02-05 17:06:20 +01:00
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#include "hw/input/adb.h"
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#include "hw/ppc/mac_dbdma.h"
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#include "hw/timer/m48t59.h"
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2013-01-24 00:03:54 +01:00
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#include "hw/pci/pci.h"
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2012-10-24 08:43:34 +02:00
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#include "net/net.h"
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2012-12-17 18:20:04 +01:00
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#include "sysemu/sysemu.h"
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2013-01-24 00:03:54 +01:00
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#include "hw/boards.h"
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2013-02-05 17:06:20 +01:00
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#include "hw/nvram/fw_cfg.h"
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#include "hw/char/escc.h"
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#include "hw/ppc/openpic.h"
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2013-01-24 00:03:54 +01:00
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#include "hw/ide.h"
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#include "hw/loader.h"
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2009-09-20 16:58:02 +02:00
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#include "elf.h"
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2012-12-17 18:20:04 +01:00
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#include "sysemu/kvm.h"
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2010-02-09 17:37:05 +01:00
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#include "kvm_ppc.h"
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2010-02-09 17:37:08 +01:00
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#include "hw/usb.h"
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2014-10-07 13:59:18 +02:00
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#include "sysemu/block-backend.h"
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2012-12-17 18:19:49 +01:00
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#include "exec/address-spaces.h"
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2013-01-24 00:03:54 +01:00
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#include "hw/sysbus.h"
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2004-06-03 20:46:20 +02:00
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2007-12-02 05:51:10 +01:00
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#define MAX_IDE_BUS 2
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2009-02-08 16:59:36 +01:00
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#define CFG_ADDR 0xf0000510
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2013-06-29 17:34:58 +02:00
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#define TBFREQ (100UL * 1000UL * 1000UL)
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2014-04-17 19:04:44 +02:00
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#define CLOCKFREQ (266UL * 1000UL * 1000UL)
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#define BUSFREQ (100UL * 1000UL * 1000UL)
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2007-12-02 05:51:10 +01:00
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2009-02-05 21:22:07 +01:00
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/* debug UniNorth */
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//#define DEBUG_UNIN
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#ifdef DEBUG_UNIN
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2009-05-13 19:53:17 +02:00
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#define UNIN_DPRINTF(fmt, ...) \
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do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
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2009-02-05 21:22:07 +01:00
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#else
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2009-05-13 19:53:17 +02:00
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#define UNIN_DPRINTF(fmt, ...)
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2009-02-05 21:22:07 +01:00
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#endif
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2005-06-05 17:11:17 +02:00
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/* UniN device */
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2012-10-23 12:30:10 +02:00
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static void unin_write(void *opaque, hwaddr addr, uint64_t value,
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2011-09-13 15:30:29 +02:00
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unsigned size)
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2005-06-05 17:11:17 +02:00
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{
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2011-09-13 15:30:29 +02:00
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UNIN_DPRINTF("write addr " TARGET_FMT_plx " val %"PRIx64"\n", addr, value);
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2013-06-25 03:39:21 +02:00
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if (addr == 0x0) {
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*(int*)opaque = value;
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}
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2005-06-05 17:11:17 +02:00
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}
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2012-10-23 12:30:10 +02:00
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static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size)
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2005-06-05 17:11:17 +02:00
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{
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2009-02-05 21:22:07 +01:00
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uint32_t value;
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value = 0;
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2013-06-25 03:39:21 +02:00
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switch (addr) {
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case 0:
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value = *(int*)opaque;
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}
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2009-02-05 21:22:07 +01:00
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UNIN_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n", addr, value);
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return value;
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2005-06-05 17:11:17 +02:00
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}
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2011-09-13 15:30:29 +02:00
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static const MemoryRegionOps unin_ops = {
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.read = unin_read,
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.write = unin_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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2005-06-05 17:11:17 +02:00
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};
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2014-12-03 20:04:02 +01:00
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static void fw_cfg_boot_set(void *opaque, const char *boot_device,
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Error **errp)
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2009-03-08 10:51:29 +01:00
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{
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2015-06-08 20:10:45 +02:00
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fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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2009-03-08 10:51:29 +01:00
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}
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2010-03-14 21:20:59 +01:00
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static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
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{
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return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
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}
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2012-10-23 12:30:10 +02:00
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static hwaddr round_page(hwaddr addr)
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2011-06-15 23:27:19 +02:00
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{
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return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
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}
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2012-02-08 03:03:33 +01:00
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static void ppc_core99_reset(void *opaque)
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{
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2012-05-04 17:30:25 +02:00
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PowerPCCPU *cpu = opaque;
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2012-02-08 03:03:33 +01:00
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2012-05-04 17:30:25 +02:00
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cpu_reset(CPU(cpu));
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2013-04-04 18:45:07 +02:00
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/* 970 CPUs want to get their initial IP as part of their boot protocol */
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cpu->env.nip = PROM_ADDR + 0x100;
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2012-02-08 03:03:33 +01:00
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}
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2007-10-29 00:42:18 +01:00
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/* PowerPC Mac99 hardware initialisation */
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2014-05-07 16:42:57 +02:00
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static void ppc_core99_init(MachineState *machine)
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2004-05-27 00:55:16 +02:00
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{
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2014-05-07 16:42:57 +02:00
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ram_addr_t ram_size = machine->ram_size;
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const char *kernel_filename = machine->kernel_filename;
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const char *kernel_cmdline = machine->kernel_cmdline;
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const char *initrd_filename = machine->initrd_filename;
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const char *boot_device = machine->boot_order;
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2012-05-04 17:29:07 +02:00
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PowerPCCPU *cpu = NULL;
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2012-03-14 01:38:23 +01:00
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CPUPPCState *env = NULL;
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2009-05-30 01:52:44 +02:00
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char *filename;
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2007-04-10 00:45:36 +02:00
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qemu_irq *pic, **openpic_irqs;
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2013-07-22 15:54:13 +02:00
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MemoryRegion *isa = g_new(MemoryRegion, 1);
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2011-09-13 15:30:29 +02:00
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MemoryRegion *unin_memory = g_new(MemoryRegion, 1);
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2013-06-25 03:46:33 +02:00
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MemoryRegion *unin2_memory = g_new(MemoryRegion, 1);
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2012-12-08 05:17:14 +01:00
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int linux_boot, i, j, k;
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2011-09-13 15:30:29 +02:00
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MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
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2012-10-23 12:30:10 +02:00
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hwaddr kernel_base, initrd_base, cmdline_base = 0;
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2010-09-18 07:53:14 +02:00
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long kernel_size, initrd_size;
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2004-06-21 21:43:00 +02:00
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PCIBus *pci_bus;
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2013-01-24 00:03:57 +01:00
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PCIDevice *macio;
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2013-01-24 00:04:01 +01:00
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MACIOIDEState *macio_ide;
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2013-01-24 00:04:05 +01:00
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BusState *adb_bus;
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2007-10-29 00:42:18 +01:00
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MacIONVRAMState *nvr;
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2010-10-13 20:38:07 +02:00
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int bios_size;
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2013-01-24 00:04:02 +01:00
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MemoryRegion *pic_mem, *escc_mem;
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2011-08-24 20:37:05 +02:00
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MemoryRegion *escc_bar = g_new(MemoryRegion, 1);
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2007-11-11 02:50:45 +01:00
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int ppc_boot_device;
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2009-08-28 15:47:03 +02:00
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DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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2009-02-08 16:59:36 +01:00
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void *fw_cfg;
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2010-02-09 17:37:02 +01:00
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int machine_arch;
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2012-12-08 05:17:14 +01:00
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SysBusDevice *s;
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DeviceState *dev;
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2013-06-25 03:39:21 +02:00
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int *token = g_new(int, 1);
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2014-07-11 03:24:39 +02:00
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hwaddr nvram_addr = 0xFFF04000;
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2014-07-13 22:29:02 +02:00
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uint64_t tbfreq;
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2004-06-21 21:43:00 +02:00
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2004-05-27 00:55:16 +02:00
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linux_boot = (kernel_filename != NULL);
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2005-11-22 00:33:12 +01:00
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/* init CPUs */
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2015-07-02 08:23:19 +02:00
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if (machine->cpu_model == NULL) {
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2009-12-20 00:22:26 +01:00
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#ifdef TARGET_PPC64
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2015-07-02 08:23:19 +02:00
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machine->cpu_model = "970fx";
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2009-12-20 00:22:26 +01:00
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#else
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2015-07-02 08:23:19 +02:00
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machine->cpu_model = "G4";
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2009-12-20 00:22:26 +01:00
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#endif
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2015-07-02 08:23:19 +02:00
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}
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2007-04-10 00:45:36 +02:00
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for (i = 0; i < smp_cpus; i++) {
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2015-07-02 08:23:19 +02:00
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cpu = cpu_ppc_init(machine->cpu_model);
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2012-05-04 17:29:07 +02:00
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if (cpu == NULL) {
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2007-11-10 16:15:54 +01:00
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fprintf(stderr, "Unable to find PowerPC CPU definition\n");
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exit(1);
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}
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2012-05-04 17:29:07 +02:00
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env = &cpu->env;
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2007-04-10 00:45:36 +02:00
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/* Set time-base frequency to 100 Mhz */
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2013-06-29 17:34:58 +02:00
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cpu_ppc_tb_init(env, TBFREQ);
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2012-05-04 17:30:25 +02:00
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qemu_register_reset(ppc_core99_reset, cpu);
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2007-04-10 00:45:36 +02:00
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}
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2005-11-22 00:33:12 +01:00
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2004-05-27 00:55:16 +02:00
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/* allocate RAM */
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2014-07-10 14:01:03 +02:00
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memory_region_allocate_system_memory(ram, NULL, "ppc_core99.ram", ram_size);
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2011-09-13 15:30:29 +02:00
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memory_region_add_subregion(get_system_memory(), 0, ram);
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2009-02-05 21:20:29 +01:00
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2004-05-27 00:55:16 +02:00
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/* allocate and load BIOS */
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2014-09-09 07:27:55 +02:00
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memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE,
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Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
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err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 16:51:43 +02:00
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&error_fatal);
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ppc: fix -mem-path failure
commit e938ba0c tried to enable -mem-path for ppc but breaked some ppc
boards.
The problems are:
1. it fails when allocating memory for rom, sram whose sizes are less
than huge page size:
./ppc-softmmu/qemu-system-ppc -m 512 -mem-path /hugepages/ \
-kernel /home/hutao/Downloads/vmlinux-ppc -initrd \
/home/hutao/Downloads/initrd-ppc.gz
qemu-system-ppc: /mnt/data/projects/qemu/exec.c:1184: qemu_ram_set_idstr: Assertion `new_block' failed.
2. if there is a numa node backed by memory backend object, qemu fails
with message:
./ppc-softmmu/qemu-system-ppc -m 512 \
-object memory-backend-file,size=512M,mem-path=/hugepages,id=f0 \
-numa node,nodeid=0,memdev=f0 \
-kernel /home/hutao/Downloads/vmlinux-ppc \
-initrd /home/hutao/Downloads/initrd-ppc.gz
qemu-system-ppc: memory backend f0 is used multiple times. Each -numa option must use a different memdev value.
This patch does following:
1. replaces memory_region_allocate_system_memory() with
memory_region_init_ram() for rom, sram. Then only system memory
is backed by hugepages when specifying mem-path.
2. for memory banks, allocates all ram with
one memory_region_allocate_system_memory(), and use
memory_region_init_alias() to initialize memory banks.
Tested machines: default(g3beige), mac99, taihu, bamboo, ref405ep.
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2014-07-21 11:30:17 +02:00
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vmstate_register_ram_global(bios);
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2007-10-05 15:08:35 +02:00
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if (bios_name == NULL)
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2009-02-08 16:59:36 +01:00
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bios_name = PROM_FILENAME;
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2009-05-30 01:52:44 +02:00
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
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2011-09-13 15:30:29 +02:00
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memory_region_set_readonly(bios, true);
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memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios);
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2009-02-08 16:59:36 +01:00
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/* Load OpenBIOS (ELF) */
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2009-05-30 01:52:44 +02:00
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if (filename) {
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2010-03-14 21:20:59 +01:00
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bios_size = load_elf(filename, NULL, NULL, NULL,
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NULL, NULL, 1, ELF_MACHINE, 0);
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2009-09-20 16:58:02 +02:00
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2011-08-21 05:09:37 +02:00
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g_free(filename);
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2009-05-30 01:52:44 +02:00
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} else {
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bios_size = -1;
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}
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2005-07-03 16:00:51 +02:00
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if (bios_size < 0 || bios_size > BIOS_SIZE) {
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2009-05-30 01:52:44 +02:00
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hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
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2004-05-27 00:55:16 +02:00
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exit(1);
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}
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2007-09-17 10:09:54 +02:00
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2004-06-21 18:55:53 +02:00
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if (linux_boot) {
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2009-03-08 10:51:29 +01:00
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uint64_t lowaddr = 0;
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2009-09-20 16:58:02 +02:00
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int bswap_needed;
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#ifdef BSWAP_NEEDED
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bswap_needed = 1;
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#else
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bswap_needed = 0;
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#endif
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2004-06-21 18:55:53 +02:00
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kernel_base = KERNEL_LOAD_ADDR;
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2009-03-08 10:51:29 +01:00
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2010-03-14 21:20:59 +01:00
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kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
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NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
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2009-03-08 10:51:29 +01:00
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if (kernel_size < 0)
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kernel_size = load_aout(kernel_filename, kernel_base,
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2009-09-20 16:58:02 +02:00
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ram_size - kernel_base, bswap_needed,
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TARGET_PAGE_SIZE);
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2009-03-08 10:51:29 +01:00
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if (kernel_size < 0)
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kernel_size = load_image_targphys(kernel_filename,
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kernel_base,
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ram_size - kernel_base);
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2004-06-21 18:55:53 +02:00
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if (kernel_size < 0) {
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2009-05-08 03:35:15 +02:00
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hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
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2004-06-21 18:55:53 +02:00
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exit(1);
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}
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/* load initrd */
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if (initrd_filename) {
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2011-06-15 23:27:19 +02:00
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initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
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2009-04-10 02:26:15 +02:00
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initrd_size = load_image_targphys(initrd_filename, initrd_base,
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ram_size - initrd_base);
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2004-06-21 18:55:53 +02:00
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if (initrd_size < 0) {
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2009-05-08 03:35:15 +02:00
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hw_error("qemu: could not load initial ram disk '%s'\n",
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initrd_filename);
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2004-06-21 18:55:53 +02:00
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exit(1);
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}
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2011-06-15 23:27:19 +02:00
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cmdline_base = round_page(initrd_base + initrd_size);
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2004-06-21 18:55:53 +02:00
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} else {
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initrd_base = 0;
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initrd_size = 0;
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2011-06-15 23:27:19 +02:00
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cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
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2004-06-21 18:55:53 +02:00
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}
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2007-10-31 02:54:04 +01:00
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ppc_boot_device = 'm';
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2004-06-21 18:55:53 +02:00
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} else {
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kernel_base = 0;
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kernel_size = 0;
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initrd_base = 0;
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initrd_size = 0;
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2007-11-11 02:50:45 +01:00
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ppc_boot_device = '\0';
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/* We consider that NewWorld PowerMac never have any floppy drive
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* For now, OHW cannot boot from the network.
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*/
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2007-11-11 15:44:28 +01:00
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for (i = 0; boot_device[i] != '\0'; i++) {
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if (boot_device[i] >= 'c' && boot_device[i] <= 'f') {
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ppc_boot_device = boot_device[i];
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2007-11-11 02:50:45 +01:00
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break;
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2007-11-11 15:44:28 +01:00
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}
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2007-11-11 02:50:45 +01:00
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}
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if (ppc_boot_device == '\0') {
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fprintf(stderr, "No valid boot device for Mac99 machine\n");
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exit(1);
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}
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2004-06-21 18:55:53 +02:00
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}
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2005-06-05 17:11:17 +02:00
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2007-10-29 00:42:18 +01:00
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/* Register 8 MB of ISA IO space */
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2013-07-22 15:54:13 +02:00
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memory_region_init_alias(isa, NULL, "isa_mmio",
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get_system_io(), 0, 0x00800000);
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memory_region_add_subregion(get_system_memory(), 0xf2000000, isa);
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2007-09-17 10:09:54 +02:00
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2013-06-25 03:39:21 +02:00
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/* UniN init: XXX should be a real device */
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2013-06-06 11:41:28 +02:00
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memory_region_init_io(unin_memory, NULL, &unin_ops, token, "unin", 0x1000);
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2011-09-13 15:30:29 +02:00
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memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory);
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2007-03-30 11:38:04 +02:00
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2013-06-06 11:41:28 +02:00
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memory_region_init_io(unin2_memory, NULL, &unin_ops, token, "unin", 0x1000);
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2013-06-25 03:46:33 +02:00
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memory_region_add_subregion(get_system_memory(), 0xf3000000, unin2_memory);
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2011-08-21 05:09:37 +02:00
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openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
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2007-10-29 00:42:18 +01:00
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openpic_irqs[0] =
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2011-08-21 05:09:37 +02:00
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g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
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2007-10-29 00:42:18 +01:00
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for (i = 0; i < smp_cpus; i++) {
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/* Mac99 IRQ connection between OpenPIC outputs pins
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* and PowerPC input pins
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*/
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switch (PPC_INPUT(env)) {
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case PPC_FLAGS_INPUT_6xx:
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openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
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openpic_irqs[i][OPENPIC_OUTPUT_INT] =
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((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
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openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
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((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
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openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
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((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
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/* Not connected ? */
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openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
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/* Check this */
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openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
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((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
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break;
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2007-10-03 03:05:39 +02:00
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#if defined(TARGET_PPC64)
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2007-10-29 00:42:18 +01:00
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case PPC_FLAGS_INPUT_970:
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openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
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openpic_irqs[i][OPENPIC_OUTPUT_INT] =
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((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
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openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
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((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
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openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
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((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
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/* Not connected ? */
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openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
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/* Check this */
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openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
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((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
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break;
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2007-10-03 03:05:39 +02:00
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#endif /* defined(TARGET_PPC64) */
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2007-10-29 00:42:18 +01:00
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default:
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2009-05-08 03:35:15 +02:00
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hw_error("Bus model not supported on mac99 machine\n");
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2007-10-29 00:42:18 +01:00
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exit(1);
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2005-06-05 17:11:17 +02:00
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}
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2007-10-29 00:42:18 +01:00
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}
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2012-12-08 05:17:14 +01:00
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2014-08-15 10:15:10 +02:00
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pic = g_new0(qemu_irq, 64);
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2012-12-08 05:17:14 +01:00
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2013-06-18 03:58:07 +02:00
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dev = qdev_create(NULL, TYPE_OPENPIC);
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2012-12-08 05:17:14 +01:00
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qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_RAVEN);
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qdev_init_nofail(dev);
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2013-01-20 02:47:33 +01:00
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s = SYS_BUS_DEVICE(dev);
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2012-12-08 05:17:14 +01:00
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pic_mem = s->mmio[0].memory;
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k = 0;
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for (i = 0; i < smp_cpus; i++) {
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for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
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sysbus_connect_irq(s, k++, openpic_irqs[i][j]);
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}
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}
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for (i = 0; i < 64; i++) {
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pic[i] = qdev_get_gpio_in(dev, i);
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}
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2010-02-09 17:37:02 +01:00
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if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
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/* 970 gets a U3 bus */
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2011-08-08 15:09:04 +02:00
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pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io());
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2010-02-09 17:37:02 +01:00
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machine_arch = ARCH_MAC99_U3;
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2015-03-23 18:05:28 +01:00
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machine->usb |= defaults_enabled() && !machine->usb_disabled;
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2010-02-09 17:37:02 +01:00
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} else {
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2011-08-08 15:09:04 +02:00
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pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io());
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2010-02-09 17:37:02 +01:00
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machine_arch = ARCH_MAC99;
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}
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2014-07-13 22:29:02 +02:00
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/* Timebase Frequency */
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if (kvm_enabled()) {
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tbfreq = kvmppc_get_tbfreq();
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} else {
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tbfreq = TBFREQ;
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}
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2007-10-29 00:42:18 +01:00
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/* init basic PC hardware */
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2011-09-30 15:29:12 +02:00
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escc_mem = escc_init(0, pic[0x25], pic[0x24],
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2011-08-08 15:09:17 +02:00
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serial_hds[0], serial_hds[1], ESCC_CLOCK, 4);
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2013-06-06 11:41:28 +02:00
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memory_region_init_alias(escc_bar, NULL, "escc-bar",
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2011-08-24 20:37:05 +02:00
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escc_mem, 0, memory_region_size(escc_mem));
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2009-01-13 20:47:10 +01:00
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2013-01-24 00:03:57 +01:00
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macio = pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO);
|
2013-01-24 00:04:01 +01:00
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dev = DEVICE(macio);
|
2013-01-24 00:04:02 +01:00
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qdev_connect_gpio_out(dev, 0, pic[0x19]); /* CUDA */
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qdev_connect_gpio_out(dev, 1, pic[0x0d]); /* IDE */
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qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE DMA */
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qdev_connect_gpio_out(dev, 3, pic[0x0e]); /* IDE */
|
2013-02-21 08:34:10 +01:00
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qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE DMA */
|
2014-07-13 22:31:53 +02:00
|
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qdev_prop_set_uint64(dev, "frequency", tbfreq);
|
2013-01-24 00:04:02 +01:00
|
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macio_init(macio, pic_mem, escc_bar);
|
2013-01-24 00:04:01 +01:00
|
|
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|
|
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/* We only emulate 2 out of 3 IDE controllers for now */
|
2014-10-01 20:19:27 +02:00
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ide_drive_get(hd, ARRAY_SIZE(hd));
|
2014-06-24 00:03:48 +02:00
|
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|
|
2013-01-24 00:04:01 +01:00
|
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macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
|
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|
|
"ide[0]"));
|
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|
|
macio_ide_init_drives(macio_ide, hd);
|
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|
|
|
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|
macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
|
|
|
|
"ide[1]"));
|
|
|
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macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
|
2006-05-21 18:30:15 +02:00
|
|
|
|
2013-01-24 00:04:05 +01:00
|
|
|
dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
|
|
|
|
adb_bus = qdev_get_child_bus(dev, "adb.0");
|
|
|
|
dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
|
2013-01-24 00:04:04 +01:00
|
|
|
qdev_init_nofail(dev);
|
2013-01-24 00:04:05 +01:00
|
|
|
dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
|
2013-01-24 00:04:04 +01:00
|
|
|
qdev_init_nofail(dev);
|
2013-01-24 00:04:02 +01:00
|
|
|
|
2015-01-06 14:29:17 +01:00
|
|
|
if (machine->usb) {
|
2012-03-07 15:06:32 +01:00
|
|
|
pci_create_simple(pci_bus, -1, "pci-ohci");
|
2015-02-04 13:28:14 +01:00
|
|
|
|
2012-09-02 21:25:28 +02:00
|
|
|
/* U3 needs to use USB for input because Linux doesn't support via-cuda
|
|
|
|
on PPC64 */
|
|
|
|
if (machine_arch == ARCH_MAC99_U3) {
|
2015-02-04 13:28:14 +01:00
|
|
|
USBBus *usb_bus = usb_bus_find(-1);
|
|
|
|
|
|
|
|
usb_create_simple(usb_bus, "usb-kbd");
|
|
|
|
usb_create_simple(usb_bus, "usb-mouse");
|
2012-09-02 21:25:28 +02:00
|
|
|
}
|
2010-02-09 17:37:08 +01:00
|
|
|
}
|
|
|
|
|
2014-06-24 00:03:48 +02:00
|
|
|
pci_vga_init(pci_bus);
|
|
|
|
|
|
|
|
if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) {
|
2004-06-21 18:55:53 +02:00
|
|
|
graphic_depth = 15;
|
2014-06-24 00:03:48 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < nb_nics; i++) {
|
|
|
|
pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
|
|
|
|
}
|
2009-02-08 17:01:01 +01:00
|
|
|
|
2007-10-29 00:42:18 +01:00
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/* The NewWorld NVRAM is not located in the MacIO device */
|
2014-07-11 03:24:39 +02:00
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#ifdef CONFIG_KVM
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if (kvm_enabled() && getpagesize() > 4096) {
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/* We can't combine read-write and read-only in a single page, so
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move the NVRAM out of ROM again for KVM */
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nvram_addr = 0xFFE00000;
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}
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#endif
|
2013-01-24 00:04:00 +01:00
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dev = qdev_create(NULL, TYPE_MACIO_NVRAM);
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qdev_prop_set_uint32(dev, "size", 0x2000);
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qdev_prop_set_uint32(dev, "it_shift", 1);
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qdev_init_nofail(dev);
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2014-07-11 03:24:39 +02:00
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr);
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2013-01-24 00:04:00 +01:00
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nvr = MACIO_NVRAM(dev);
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2007-10-29 00:42:18 +01:00
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pmac_format_nvram_partition(nvr, 0x2000);
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2004-06-21 18:55:53 +02:00
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/* No PCI init: the BIOS will do it */
|
2005-06-05 17:11:17 +02:00
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|
2014-12-22 13:11:36 +01:00
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fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
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2013-01-22 21:25:03 +01:00
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fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
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2009-02-08 16:59:36 +01:00
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|
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
|
2010-02-09 17:37:02 +01:00
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|
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch);
|
2009-03-08 10:51:29 +01:00
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|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
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|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
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|
|
|
if (kernel_cmdline) {
|
2011-06-15 23:27:19 +02:00
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|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
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|
pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
|
2009-03-08 10:51:29 +01:00
|
|
|
} else {
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|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
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|
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|
}
|
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|
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
|
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|
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
|
2009-08-08 12:47:15 +02:00
|
|
|
|
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
|
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
|
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
|
|
|
|
|
2010-08-03 15:22:42 +02:00
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
|
2010-02-09 17:37:05 +01:00
|
|
|
if (kvm_enabled()) {
|
|
|
|
#ifdef CONFIG_KVM
|
2010-08-03 15:22:42 +02:00
|
|
|
uint8_t *hypercall;
|
|
|
|
|
2011-08-21 05:09:37 +02:00
|
|
|
hypercall = g_malloc(16);
|
2010-08-03 15:22:42 +02:00
|
|
|
kvmppc_get_hypercall(env, hypercall, 16);
|
|
|
|
fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
|
2010-02-09 17:37:05 +01:00
|
|
|
#endif
|
|
|
|
}
|
2014-07-13 22:29:02 +02:00
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
|
2013-06-23 00:22:50 +02:00
|
|
|
/* Mac OS X requires a "known good" clock-frequency value; pass it one. */
|
2014-04-17 19:04:44 +02:00
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
|
2014-07-11 03:24:39 +02:00
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr);
|
2010-02-09 17:37:05 +01:00
|
|
|
|
2009-03-08 10:51:29 +01:00
|
|
|
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
|
2007-11-24 03:56:36 +01:00
|
|
|
}
|
2005-06-05 17:11:17 +02:00
|
|
|
|
2014-07-24 10:46:47 +02:00
|
|
|
static int core99_kvm_type(const char *arg)
|
|
|
|
{
|
|
|
|
/* Always force PR KVM */
|
|
|
|
return 2;
|
|
|
|
}
|
|
|
|
|
2015-01-06 14:29:15 +01:00
|
|
|
static void core99_machine_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->name = "mac99";
|
|
|
|
mc->desc = "Mac99 based PowerMAC";
|
|
|
|
mc->init = ppc_core99_init;
|
|
|
|
mc->max_cpus = MAX_CPUS;
|
|
|
|
mc->default_boot_order = "cd";
|
|
|
|
mc->kvm_type = core99_kvm_type;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo core99_machine_info = {
|
|
|
|
.name = "mac99-machine",
|
|
|
|
.parent = TYPE_MACHINE,
|
|
|
|
.class_init = core99_machine_class_init,
|
2005-06-05 17:11:17 +02:00
|
|
|
};
|
2009-05-21 01:38:09 +02:00
|
|
|
|
2015-01-06 14:29:15 +01:00
|
|
|
static void mac_machine_register_types(void)
|
2009-05-21 01:38:09 +02:00
|
|
|
{
|
2015-01-06 14:29:15 +01:00
|
|
|
type_register_static(&core99_machine_info);
|
2009-05-21 01:38:09 +02:00
|
|
|
}
|
|
|
|
|
2015-01-06 14:29:15 +01:00
|
|
|
type_init(mac_machine_register_types)
|