2018-01-06 16:37:26 +01:00
|
|
|
/*
|
|
|
|
* QEMU PIIX South Bridge Emulation
|
|
|
|
*
|
|
|
|
* Copyright (c) 2006 Fabrice Bellard
|
2019-02-02 01:13:12 +01:00
|
|
|
* Copyright (c) 2018 Hervé Poussineau
|
2018-01-06 16:37:26 +01:00
|
|
|
*
|
|
|
|
* This work is licensed under the terms of the GNU GPL, version 2 or later.
|
|
|
|
* See the COPYING file in the top-level directory.
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef HW_SOUTHBRIDGE_PIIX_H
|
|
|
|
#define HW_SOUTHBRIDGE_PIIX_H
|
|
|
|
|
2019-10-28 16:12:18 +01:00
|
|
|
#include "hw/pci/pci.h"
|
|
|
|
|
2018-01-06 16:37:26 +01:00
|
|
|
#define TYPE_PIIX4_PM "PIIX4_PM"
|
|
|
|
|
|
|
|
I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
|
|
|
|
qemu_irq sci_irq, qemu_irq smi_irq,
|
|
|
|
int smm_enabled, DeviceState **piix4_pm);
|
|
|
|
|
2019-10-15 14:05:42 +02:00
|
|
|
/* PIRQRC[A:D]: PIRQx Route Control Registers */
|
|
|
|
#define PIIX_PIRQCA 0x60
|
|
|
|
#define PIIX_PIRQCB 0x61
|
|
|
|
#define PIIX_PIRQCC 0x62
|
|
|
|
#define PIIX_PIRQCD 0x63
|
|
|
|
|
2019-02-02 20:48:46 +01:00
|
|
|
/*
|
|
|
|
* Reset Control Register: PCI-accessible ISA-Compatible Register at address
|
|
|
|
* 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
|
|
|
|
*/
|
|
|
|
#define PIIX_RCR_IOPORT 0xcf9
|
|
|
|
|
2019-10-28 16:12:18 +01:00
|
|
|
#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
|
|
|
|
#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
|
|
|
|
|
|
|
|
typedef struct PIIXState {
|
|
|
|
PCIDevice dev;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* bitmap to track pic levels.
|
|
|
|
* The pic level is the logical OR of all the PCI irqs mapped to it
|
|
|
|
* So one PIC level is tracked by PIIX_NUM_PIRQS bits.
|
|
|
|
*
|
|
|
|
* PIRQ is mapped to PIC pins, we track it by
|
|
|
|
* PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
|
|
|
|
* pic_irq * PIIX_NUM_PIRQS + pirq
|
|
|
|
*/
|
|
|
|
#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
|
|
|
|
#error "unable to encode pic state in 64bit in pic_levels."
|
|
|
|
#endif
|
|
|
|
uint64_t pic_levels;
|
|
|
|
|
|
|
|
qemu_irq *pic;
|
|
|
|
|
|
|
|
/* This member isn't used. Just for save/load compatibility */
|
|
|
|
int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
|
|
|
|
|
|
|
|
/* Reset Control Register contents */
|
|
|
|
uint8_t rcr;
|
|
|
|
|
|
|
|
/* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
|
|
|
|
MemoryRegion rcr_mem;
|
|
|
|
} PIIX3State;
|
|
|
|
|
2019-02-02 01:13:12 +01:00
|
|
|
extern PCIDevice *piix4_dev;
|
|
|
|
|
2019-10-28 16:12:18 +01:00
|
|
|
PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus);
|
|
|
|
|
2020-03-17 16:05:37 +01:00
|
|
|
DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus);
|
2019-02-02 01:13:12 +01:00
|
|
|
|
2018-01-06 16:37:26 +01:00
|
|
|
#endif
|