2003-06-15 22:02:25 +02:00
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/*
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* defines common to all virtual CPUs
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2007-09-16 23:08:06 +02:00
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*
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2003-06-15 22:02:25 +02:00
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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2009-07-16 22:47:01 +02:00
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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2003-06-15 22:02:25 +02:00
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*/
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#ifndef CPU_ALL_H
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#define CPU_ALL_H
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2009-01-14 20:00:36 +01:00
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#include "qemu-common.h"
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2012-12-17 18:20:00 +01:00
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#include "qemu/tls.h"
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2012-12-17 18:19:49 +01:00
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#include "exec/cpu-common.h"
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2011-08-17 09:01:33 +02:00
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#include "qemu/thread.h"
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2004-01-04 16:44:17 +01:00
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2007-09-16 23:08:06 +02:00
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/* some important defines:
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*
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2004-01-04 16:44:17 +01:00
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* WORDS_ALIGNED : if defined, the host cpu can only make word aligned
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* memory accesses.
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2007-09-16 23:08:06 +02:00
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*
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2009-07-27 16:13:06 +02:00
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* HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and
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2004-01-04 16:44:17 +01:00
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* otherwise little endian.
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2007-09-16 23:08:06 +02:00
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*
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2004-01-04 16:44:17 +01:00
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* (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
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2007-09-16 23:08:06 +02:00
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*
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2004-01-04 16:44:17 +01:00
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* TARGET_WORDS_BIGENDIAN : same for target cpu
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*/
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2009-07-27 16:13:06 +02:00
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#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
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2004-03-21 18:06:25 +01:00
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#define BSWAP_NEEDED
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#endif
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#ifdef BSWAP_NEEDED
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static inline uint16_t tswap16(uint16_t s)
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{
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return bswap16(s);
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}
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static inline uint32_t tswap32(uint32_t s)
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{
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return bswap32(s);
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}
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static inline uint64_t tswap64(uint64_t s)
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{
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return bswap64(s);
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}
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static inline void tswap16s(uint16_t *s)
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{
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*s = bswap16(*s);
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}
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static inline void tswap32s(uint32_t *s)
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{
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*s = bswap32(*s);
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}
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static inline void tswap64s(uint64_t *s)
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{
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*s = bswap64(*s);
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}
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#else
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static inline uint16_t tswap16(uint16_t s)
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{
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return s;
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}
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static inline uint32_t tswap32(uint32_t s)
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{
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return s;
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}
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static inline uint64_t tswap64(uint64_t s)
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{
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return s;
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}
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static inline void tswap16s(uint16_t *s)
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{
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}
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static inline void tswap32s(uint32_t *s)
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{
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}
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static inline void tswap64s(uint64_t *s)
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{
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}
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#endif
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#if TARGET_LONG_SIZE == 4
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#define tswapl(s) tswap32(s)
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#define tswapls(s) tswap32s((uint32_t *)(s))
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2005-02-10 23:00:27 +01:00
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#define bswaptls(s) bswap32s(s)
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2004-03-21 18:06:25 +01:00
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#else
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#define tswapl(s) tswap64(s)
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#define tswapls(s) tswap64s((uint64_t *)(s))
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2005-02-10 23:00:27 +01:00
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#define bswaptls(s) bswap64s(s)
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2004-03-21 18:06:25 +01:00
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#endif
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2003-10-27 22:22:23 +01:00
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/* CPU memory access without any memory or io remapping */
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2004-02-22 12:53:50 +01:00
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/*
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* the generic syntax for the memory accesses is:
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*
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* load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
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*
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* store: st{type}{size}{endian}_{access_type}(ptr, val)
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*
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* type is:
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* (empty): integer access
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* f : float access
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2007-09-16 23:08:06 +02:00
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*
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2004-02-22 12:53:50 +01:00
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* sign is:
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* (empty): for floats or 32 bit size
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* u : unsigned
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* s : signed
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*
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* size is:
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* b: 8 bits
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* w: 16 bits
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* l: 32 bits
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* q: 64 bits
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2007-09-16 23:08:06 +02:00
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*
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2004-02-22 12:53:50 +01:00
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* endian is:
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* (empty): target cpu endianness or 8 bit access
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* r : reversed target cpu endianness (not implemented yet)
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* be : big endian (not implemented yet)
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* le : little endian (not implemented yet)
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*
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* access_type is:
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* raw : host memory access
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* user : user mode access using soft MMU
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* kernel : kernel mode access using soft MMU
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*/
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2005-11-19 18:47:39 +01:00
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2011-07-28 12:10:30 +02:00
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/* target-endianness CPU memory access functions */
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2005-11-19 18:47:39 +01:00
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#if defined(TARGET_WORDS_BIGENDIAN)
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#define lduw_p(p) lduw_be_p(p)
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#define ldsw_p(p) ldsw_be_p(p)
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#define ldl_p(p) ldl_be_p(p)
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#define ldq_p(p) ldq_be_p(p)
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#define ldfl_p(p) ldfl_be_p(p)
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#define ldfq_p(p) ldfq_be_p(p)
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#define stw_p(p, v) stw_be_p(p, v)
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#define stl_p(p, v) stl_be_p(p, v)
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#define stq_p(p, v) stq_be_p(p, v)
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#define stfl_p(p, v) stfl_be_p(p, v)
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#define stfq_p(p, v) stfq_be_p(p, v)
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#else
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#define lduw_p(p) lduw_le_p(p)
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#define ldsw_p(p) ldsw_le_p(p)
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#define ldl_p(p) ldl_le_p(p)
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#define ldq_p(p) ldq_le_p(p)
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#define ldfl_p(p) ldfl_le_p(p)
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#define ldfq_p(p) ldfq_le_p(p)
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#define stw_p(p, v) stw_le_p(p, v)
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#define stl_p(p, v) stl_le_p(p, v)
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#define stq_p(p, v) stq_le_p(p, v)
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#define stfl_p(p, v) stfl_le_p(p, v)
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#define stfq_p(p, v) stfq_le_p(p, v)
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2003-06-15 22:02:25 +02:00
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#endif
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2003-10-27 22:22:23 +01:00
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/* MMU memory access macros */
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2006-03-25 20:31:22 +01:00
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#if defined(CONFIG_USER_ONLY)
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2008-12-08 19:12:11 +01:00
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#include <assert.h>
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2012-12-17 18:19:49 +01:00
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#include "exec/user/abitypes.h"
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2008-12-08 19:12:11 +01:00
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2006-03-25 20:31:22 +01:00
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/* On some host systems the guest address space is reserved on the host.
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* This allows the guest address space to be offset to a convenient location.
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*/
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2009-07-17 13:48:08 +02:00
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#if defined(CONFIG_USE_GUEST_BASE)
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extern unsigned long guest_base;
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extern int have_guest_base;
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2010-05-29 03:27:35 +02:00
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extern unsigned long reserved_va;
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2009-07-17 13:48:08 +02:00
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#define GUEST_BASE guest_base
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2010-07-30 21:09:10 +02:00
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#define RESERVED_VA reserved_va
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2009-07-17 13:48:08 +02:00
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#else
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#define GUEST_BASE 0ul
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2010-07-30 21:09:10 +02:00
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#define RESERVED_VA 0ul
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2009-07-17 13:48:08 +02:00
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#endif
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2006-03-25 20:31:22 +01:00
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/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
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2012-03-09 15:33:20 +01:00
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#define g2h(x) ((void *)((unsigned long)(target_ulong)(x) + GUEST_BASE))
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2010-03-10 23:36:58 +01:00
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#if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
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#define h2g_valid(x) 1
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#else
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#define h2g_valid(x) ({ \
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unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \
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2012-02-02 03:14:18 +01:00
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(__guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) && \
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(!RESERVED_VA || (__guest < RESERVED_VA)); \
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2010-03-10 23:36:58 +01:00
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})
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#endif
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2008-12-08 19:12:11 +01:00
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#define h2g(x) ({ \
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unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \
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/* Check if given address fits target address space */ \
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2010-03-10 23:36:58 +01:00
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assert(h2g_valid(x)); \
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2008-12-08 19:12:11 +01:00
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(abi_ulong)__ret; \
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})
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2006-03-25 20:31:22 +01:00
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#define saddr(x) g2h(x)
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#define laddr(x) g2h(x)
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#else /* !CONFIG_USER_ONLY */
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2005-01-04 00:35:10 +01:00
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/* NOTE: we use double casts if pointers and target_ulong have
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different sizes */
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2012-04-15 15:18:29 +02:00
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#define saddr(x) (uint8_t *)(intptr_t)(x)
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#define laddr(x) (uint8_t *)(intptr_t)(x)
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2006-03-25 20:31:22 +01:00
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#endif
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#define ldub_raw(p) ldub_p(laddr((p)))
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#define ldsb_raw(p) ldsb_p(laddr((p)))
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#define lduw_raw(p) lduw_p(laddr((p)))
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#define ldsw_raw(p) ldsw_p(laddr((p)))
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#define ldl_raw(p) ldl_p(laddr((p)))
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#define ldq_raw(p) ldq_p(laddr((p)))
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#define ldfl_raw(p) ldfl_p(laddr((p)))
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#define ldfq_raw(p) ldfq_p(laddr((p)))
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#define stb_raw(p, v) stb_p(saddr((p)), v)
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#define stw_raw(p, v) stw_p(saddr((p)), v)
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#define stl_raw(p, v) stl_p(saddr((p)), v)
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#define stq_raw(p, v) stq_p(saddr((p)), v)
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#define stfl_raw(p, v) stfl_p(saddr((p)), v)
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#define stfq_raw(p, v) stfq_p(saddr((p)), v)
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2005-01-04 00:35:10 +01:00
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2007-09-16 23:08:06 +02:00
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#if defined(CONFIG_USER_ONLY)
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2003-10-27 22:22:23 +01:00
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/* if user mode, no other memory access functions */
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#define ldub(p) ldub_raw(p)
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#define ldsb(p) ldsb_raw(p)
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#define lduw(p) lduw_raw(p)
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#define ldsw(p) ldsw_raw(p)
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#define ldl(p) ldl_raw(p)
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#define ldq(p) ldq_raw(p)
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#define ldfl(p) ldfl_raw(p)
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#define ldfq(p) ldfq_raw(p)
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#define stb(p, v) stb_raw(p, v)
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#define stw(p, v) stw_raw(p, v)
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#define stl(p, v) stl_raw(p, v)
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#define stq(p, v) stq_raw(p, v)
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#define stfl(p, v) stfl_raw(p, v)
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#define stfq(p, v) stfq_raw(p, v)
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2011-09-18 16:55:46 +02:00
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#define cpu_ldub_code(env1, p) ldub_raw(p)
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#define cpu_ldsb_code(env1, p) ldsb_raw(p)
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#define cpu_lduw_code(env1, p) lduw_raw(p)
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#define cpu_ldsw_code(env1, p) ldsw_raw(p)
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#define cpu_ldl_code(env1, p) ldl_raw(p)
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#define cpu_ldq_code(env1, p) ldq_raw(p)
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2012-04-29 22:35:48 +02:00
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#define cpu_ldub_data(env, addr) ldub_raw(addr)
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#define cpu_lduw_data(env, addr) lduw_raw(addr)
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#define cpu_ldsw_data(env, addr) ldsw_raw(addr)
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#define cpu_ldl_data(env, addr) ldl_raw(addr)
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#define cpu_ldq_data(env, addr) ldq_raw(addr)
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#define cpu_stb_data(env, addr, data) stb_raw(addr, data)
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#define cpu_stw_data(env, addr, data) stw_raw(addr, data)
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#define cpu_stl_data(env, addr, data) stl_raw(addr, data)
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#define cpu_stq_data(env, addr, data) stq_raw(addr, data)
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#define cpu_ldub_kernel(env, addr) ldub_raw(addr)
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#define cpu_lduw_kernel(env, addr) lduw_raw(addr)
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#define cpu_ldsw_kernel(env, addr) ldsw_raw(addr)
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#define cpu_ldl_kernel(env, addr) ldl_raw(addr)
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#define cpu_ldq_kernel(env, addr) ldq_raw(addr)
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#define cpu_stb_kernel(env, addr, data) stb_raw(addr, data)
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#define cpu_stw_kernel(env, addr, data) stw_raw(addr, data)
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#define cpu_stl_kernel(env, addr, data) stl_raw(addr, data)
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#define cpu_stq_kernel(env, addr, data) stq_raw(addr, data)
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2003-10-27 22:22:23 +01:00
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#define ldub_kernel(p) ldub_raw(p)
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#define ldsb_kernel(p) ldsb_raw(p)
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#define lduw_kernel(p) lduw_raw(p)
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#define ldsw_kernel(p) ldsw_raw(p)
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|
|
|
#define ldl_kernel(p) ldl_raw(p)
|
2007-04-04 09:55:12 +02:00
|
|
|
#define ldq_kernel(p) ldq_raw(p)
|
2004-01-04 16:44:17 +01:00
|
|
|
#define ldfl_kernel(p) ldfl_raw(p)
|
|
|
|
#define ldfq_kernel(p) ldfq_raw(p)
|
2003-10-27 22:22:23 +01:00
|
|
|
#define stb_kernel(p, v) stb_raw(p, v)
|
|
|
|
#define stw_kernel(p, v) stw_raw(p, v)
|
|
|
|
#define stl_kernel(p, v) stl_raw(p, v)
|
|
|
|
#define stq_kernel(p, v) stq_raw(p, v)
|
2004-01-04 16:44:17 +01:00
|
|
|
#define stfl_kernel(p, v) stfl_raw(p, v)
|
|
|
|
#define stfq_kernel(p, vt) stfq_raw(p, v)
|
2003-10-27 22:22:23 +01:00
|
|
|
|
2012-05-30 06:23:40 +02:00
|
|
|
#define cpu_ldub_data(env, addr) ldub_raw(addr)
|
|
|
|
#define cpu_lduw_data(env, addr) lduw_raw(addr)
|
|
|
|
#define cpu_ldl_data(env, addr) ldl_raw(addr)
|
|
|
|
|
|
|
|
#define cpu_stb_data(env, addr, data) stb_raw(addr, data)
|
|
|
|
#define cpu_stw_data(env, addr, data) stw_raw(addr, data)
|
|
|
|
#define cpu_stl_data(env, addr, data) stl_raw(addr, data)
|
2003-10-27 22:22:23 +01:00
|
|
|
#endif /* defined(CONFIG_USER_ONLY) */
|
|
|
|
|
2003-06-15 22:02:25 +02:00
|
|
|
/* page related stuff */
|
|
|
|
|
2008-04-22 22:45:18 +02:00
|
|
|
#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
|
2003-06-15 22:02:25 +02:00
|
|
|
#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
|
|
|
|
#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
|
|
|
|
|
2012-03-16 20:23:49 +01:00
|
|
|
/* ??? These should be the larger of uintptr_t and target_ulong. */
|
|
|
|
extern uintptr_t qemu_real_host_page_size;
|
|
|
|
extern uintptr_t qemu_host_page_size;
|
|
|
|
extern uintptr_t qemu_host_page_mask;
|
2003-06-15 22:02:25 +02:00
|
|
|
|
2004-07-05 23:25:26 +02:00
|
|
|
#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
|
2003-06-15 22:02:25 +02:00
|
|
|
|
|
|
|
/* same as PROT_xxx */
|
|
|
|
#define PAGE_READ 0x0001
|
|
|
|
#define PAGE_WRITE 0x0002
|
|
|
|
#define PAGE_EXEC 0x0004
|
|
|
|
#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
|
|
|
|
#define PAGE_VALID 0x0008
|
|
|
|
/* original state of the write flag (used when tracking self-modifying
|
|
|
|
code */
|
2007-09-16 23:08:06 +02:00
|
|
|
#define PAGE_WRITE_ORG 0x0010
|
2010-05-05 17:32:59 +02:00
|
|
|
#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
|
|
|
|
/* FIXME: Code that sets/uses this is broken and needs to go away. */
|
2007-12-12 02:16:23 +01:00
|
|
|
#define PAGE_RESERVED 0x0020
|
2010-05-05 17:32:59 +02:00
|
|
|
#endif
|
2003-06-15 22:02:25 +02:00
|
|
|
|
2010-03-13 00:23:29 +01:00
|
|
|
#if defined(CONFIG_USER_ONLY)
|
2003-06-15 22:02:25 +02:00
|
|
|
void page_dump(FILE *f);
|
2010-03-11 00:53:37 +01:00
|
|
|
|
2010-03-13 00:23:29 +01:00
|
|
|
typedef int (*walk_memory_regions_fn)(void *, abi_ulong,
|
|
|
|
abi_ulong, unsigned long);
|
2010-03-11 00:53:37 +01:00
|
|
|
int walk_memory_regions(void *, walk_memory_regions_fn);
|
|
|
|
|
2006-03-25 20:31:22 +01:00
|
|
|
int page_get_flags(target_ulong address);
|
|
|
|
void page_set_flags(target_ulong start, target_ulong end, int flags);
|
2007-11-02 20:02:07 +01:00
|
|
|
int page_check_range(target_ulong start, target_ulong len, int flags);
|
2010-03-13 00:23:29 +01:00
|
|
|
#endif
|
2003-06-15 22:02:25 +02:00
|
|
|
|
2012-03-14 01:38:32 +01:00
|
|
|
CPUArchState *cpu_copy(CPUArchState *env);
|
2007-02-28 21:20:53 +01:00
|
|
|
|
2011-01-21 21:48:08 +01:00
|
|
|
#define CPU_DUMP_CODE 0x00010000
|
2012-10-05 16:04:43 +02:00
|
|
|
#define CPU_DUMP_FPU 0x00020000 /* dump FPU register state, not just integer */
|
|
|
|
/* dump info about TCG QEMU's condition code optimization state */
|
|
|
|
#define CPU_DUMP_CCOP 0x00040000
|
2011-01-21 21:48:08 +01:00
|
|
|
|
2012-03-14 01:38:32 +01:00
|
|
|
void cpu_dump_state(CPUArchState *env, FILE *f, fprintf_function cpu_fprintf,
|
2004-10-09 20:08:01 +02:00
|
|
|
int flags);
|
2012-03-14 01:38:32 +01:00
|
|
|
void cpu_dump_statistics(CPUArchState *env, FILE *f, fprintf_function cpu_fprintf,
|
2010-10-22 23:03:33 +02:00
|
|
|
int flags);
|
2004-10-09 20:08:01 +02:00
|
|
|
|
2012-03-14 01:38:32 +01:00
|
|
|
void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...)
|
2010-10-13 20:54:27 +02:00
|
|
|
GCC_FMT_ATTR(2, 3);
|
2012-03-14 01:38:32 +01:00
|
|
|
extern CPUArchState *first_cpu;
|
|
|
|
DECLARE_TLS(CPUArchState *,cpu_single_env);
|
2011-12-05 15:18:54 +01:00
|
|
|
#define cpu_single_env tls_var(cpu_single_env)
|
2010-03-10 11:38:55 +01:00
|
|
|
|
2011-05-04 22:34:24 +02:00
|
|
|
/* Flags for use in ENV->INTERRUPT_PENDING.
|
|
|
|
|
|
|
|
The numbers assigned here are non-sequential in order to preserve
|
|
|
|
binary compatibility with the vmstate dump. Bit 0 (0x0001) was
|
|
|
|
previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
|
|
|
|
the vmstate dump. */
|
|
|
|
|
|
|
|
/* External hardware interrupt pending. This is typically used for
|
|
|
|
interrupts from devices. */
|
|
|
|
#define CPU_INTERRUPT_HARD 0x0002
|
|
|
|
|
|
|
|
/* Exit the current TB. This is typically used when some system-level device
|
|
|
|
makes some change to the memory mapping. E.g. the a20 line change. */
|
|
|
|
#define CPU_INTERRUPT_EXITTB 0x0004
|
|
|
|
|
|
|
|
/* Halt the CPU. */
|
|
|
|
#define CPU_INTERRUPT_HALT 0x0020
|
|
|
|
|
|
|
|
/* Debug event pending. */
|
|
|
|
#define CPU_INTERRUPT_DEBUG 0x0080
|
|
|
|
|
|
|
|
/* Several target-specific external hardware interrupts. Each target/cpu.h
|
|
|
|
should define proper names based on these defines. */
|
|
|
|
#define CPU_INTERRUPT_TGT_EXT_0 0x0008
|
|
|
|
#define CPU_INTERRUPT_TGT_EXT_1 0x0010
|
|
|
|
#define CPU_INTERRUPT_TGT_EXT_2 0x0040
|
|
|
|
#define CPU_INTERRUPT_TGT_EXT_3 0x0200
|
|
|
|
#define CPU_INTERRUPT_TGT_EXT_4 0x1000
|
|
|
|
|
|
|
|
/* Several target-specific internal interrupts. These differ from the
|
2011-11-22 11:06:26 +01:00
|
|
|
preceding target-specific interrupts in that they are intended to
|
2011-05-04 22:34:24 +02:00
|
|
|
originate from within the cpu itself, typically in response to some
|
|
|
|
instruction being executed. These, therefore, are not masked while
|
|
|
|
single-stepping within the debugger. */
|
|
|
|
#define CPU_INTERRUPT_TGT_INT_0 0x0100
|
|
|
|
#define CPU_INTERRUPT_TGT_INT_1 0x0400
|
|
|
|
#define CPU_INTERRUPT_TGT_INT_2 0x0800
|
2012-02-17 18:31:17 +01:00
|
|
|
#define CPU_INTERRUPT_TGT_INT_3 0x2000
|
2011-05-04 22:34:24 +02:00
|
|
|
|
2012-02-17 18:31:17 +01:00
|
|
|
/* First unused bit: 0x4000. */
|
2011-05-04 22:34:24 +02:00
|
|
|
|
2011-05-04 22:34:25 +02:00
|
|
|
/* The set of all bits that should be masked when single-stepping. */
|
|
|
|
#define CPU_INTERRUPT_SSTEP_MASK \
|
|
|
|
(CPU_INTERRUPT_HARD \
|
|
|
|
| CPU_INTERRUPT_TGT_EXT_0 \
|
|
|
|
| CPU_INTERRUPT_TGT_EXT_1 \
|
|
|
|
| CPU_INTERRUPT_TGT_EXT_2 \
|
|
|
|
| CPU_INTERRUPT_TGT_EXT_3 \
|
|
|
|
| CPU_INTERRUPT_TGT_EXT_4)
|
2005-11-26 11:29:22 +01:00
|
|
|
|
2011-04-13 01:32:56 +02:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
2012-03-14 01:38:32 +01:00
|
|
|
typedef void (*CPUInterruptHandler)(CPUArchState *, int);
|
2011-04-13 01:32:56 +02:00
|
|
|
|
|
|
|
extern CPUInterruptHandler cpu_interrupt_handler;
|
|
|
|
|
2012-03-14 01:38:32 +01:00
|
|
|
static inline void cpu_interrupt(CPUArchState *s, int mask)
|
2011-04-13 01:32:56 +02:00
|
|
|
{
|
|
|
|
cpu_interrupt_handler(s, mask);
|
|
|
|
}
|
|
|
|
#else /* USER_ONLY */
|
2012-03-14 01:38:32 +01:00
|
|
|
void cpu_interrupt(CPUArchState *env, int mask);
|
2011-04-13 01:32:56 +02:00
|
|
|
#endif /* USER_ONLY */
|
|
|
|
|
2012-03-14 01:38:32 +01:00
|
|
|
void cpu_reset_interrupt(CPUArchState *env, int mask);
|
2003-06-30 15:12:32 +02:00
|
|
|
|
2012-03-14 01:38:32 +01:00
|
|
|
void cpu_exit(CPUArchState *s);
|
2009-03-07 22:28:24 +01:00
|
|
|
|
2008-11-18 21:07:32 +01:00
|
|
|
/* Breakpoint/watchpoint flags */
|
|
|
|
#define BP_MEM_READ 0x01
|
|
|
|
#define BP_MEM_WRITE 0x02
|
|
|
|
#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
|
2008-11-18 21:24:06 +01:00
|
|
|
#define BP_STOP_BEFORE_ACCESS 0x04
|
2008-11-18 21:37:55 +01:00
|
|
|
#define BP_WATCHPOINT_HIT 0x08
|
2008-11-18 21:07:32 +01:00
|
|
|
#define BP_GDB 0x10
|
2008-11-18 21:56:59 +01:00
|
|
|
#define BP_CPU 0x20
|
2008-11-18 21:07:32 +01:00
|
|
|
|
2012-03-14 01:38:32 +01:00
|
|
|
int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
|
2008-11-18 21:07:32 +01:00
|
|
|
CPUBreakpoint **breakpoint);
|
2012-03-14 01:38:32 +01:00
|
|
|
int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags);
|
|
|
|
void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint);
|
|
|
|
void cpu_breakpoint_remove_all(CPUArchState *env, int mask);
|
|
|
|
int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
|
2008-11-18 21:07:32 +01:00
|
|
|
int flags, CPUWatchpoint **watchpoint);
|
2012-03-14 01:38:32 +01:00
|
|
|
int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr,
|
2008-11-18 21:07:32 +01:00
|
|
|
target_ulong len, int flags);
|
2012-03-14 01:38:32 +01:00
|
|
|
void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint);
|
|
|
|
void cpu_watchpoint_remove_all(CPUArchState *env, int mask);
|
2008-05-09 10:25:14 +02:00
|
|
|
|
|
|
|
#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
|
|
|
|
#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
|
|
|
|
#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
|
|
|
|
|
2012-03-14 01:38:32 +01:00
|
|
|
void cpu_single_step(CPUArchState *env, int enabled);
|
2003-07-26 14:06:08 +02:00
|
|
|
|
2010-03-12 17:54:58 +01:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
|
2010-03-01 04:46:18 +01:00
|
|
|
/* Return the physical page corresponding to a virtual one. Use it
|
|
|
|
only for debugging because no protection checks are done. Return -1
|
|
|
|
if no page found. */
|
2012-10-23 12:30:10 +02:00
|
|
|
hwaddr cpu_get_phys_page_debug(CPUArchState *env, target_ulong addr);
|
2010-03-01 04:46:18 +01:00
|
|
|
|
2003-08-10 23:47:01 +02:00
|
|
|
/* memory API */
|
|
|
|
|
2004-01-04 18:43:30 +01:00
|
|
|
extern int phys_ram_fd;
|
2009-10-01 23:12:16 +02:00
|
|
|
extern ram_addr_t ram_size;
|
2010-06-11 19:11:42 +02:00
|
|
|
|
2011-03-02 08:56:19 +01:00
|
|
|
/* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
|
|
|
|
#define RAM_PREALLOC_MASK (1 << 0)
|
|
|
|
|
2010-06-11 19:11:42 +02:00
|
|
|
typedef struct RAMBlock {
|
2011-12-21 12:09:49 +01:00
|
|
|
struct MemoryRegion *mr;
|
2010-06-11 19:11:42 +02:00
|
|
|
uint8_t *host;
|
|
|
|
ram_addr_t offset;
|
|
|
|
ram_addr_t length;
|
2011-03-02 08:56:19 +01:00
|
|
|
uint32_t flags;
|
2010-06-25 19:09:43 +02:00
|
|
|
char idstr[256];
|
2011-08-17 09:01:33 +02:00
|
|
|
/* Reads can take either the iothread or the ramlist lock.
|
|
|
|
* Writes must take both locks.
|
|
|
|
*/
|
2012-11-14 15:54:48 +01:00
|
|
|
QTAILQ_ENTRY(RAMBlock) next;
|
2010-07-02 19:13:17 +02:00
|
|
|
#if defined(__linux__) && !defined(TARGET_S390X)
|
|
|
|
int fd;
|
|
|
|
#endif
|
2010-06-11 19:11:42 +02:00
|
|
|
} RAMBlock;
|
|
|
|
|
|
|
|
typedef struct RAMList {
|
2011-08-17 09:01:33 +02:00
|
|
|
QemuMutex mutex;
|
|
|
|
/* Protected by the iothread lock. */
|
2010-06-11 19:11:42 +02:00
|
|
|
uint8_t *phys_dirty;
|
2012-11-14 15:45:02 +01:00
|
|
|
RAMBlock *mru_block;
|
2011-08-17 09:01:33 +02:00
|
|
|
/* Protected by the ramlist lock. */
|
2012-11-14 15:54:48 +01:00
|
|
|
QTAILQ_HEAD(, RAMBlock) blocks;
|
2011-08-18 20:41:17 +02:00
|
|
|
uint32_t version;
|
2010-06-11 19:11:42 +02:00
|
|
|
} RAMList;
|
|
|
|
extern RAMList ram_list;
|
2004-01-04 18:43:30 +01:00
|
|
|
|
2010-03-02 00:25:08 +01:00
|
|
|
extern const char *mem_path;
|
|
|
|
extern int mem_prealloc;
|
|
|
|
|
2008-06-09 02:20:13 +02:00
|
|
|
/* Flags stored in the low bits of the TLB virtual address. These are
|
|
|
|
defined so that fast path ram access is all zeros. */
|
|
|
|
/* Zero if TLB entry is valid. */
|
|
|
|
#define TLB_INVALID_MASK (1 << 3)
|
|
|
|
/* Set if TLB entry references a clean RAM page. The iotlb entry will
|
|
|
|
contain the page physical address. */
|
|
|
|
#define TLB_NOTDIRTY (1 << 4)
|
|
|
|
/* Set if TLB entry is an IO callback. */
|
|
|
|
#define TLB_MMIO (1 << 5)
|
|
|
|
|
2010-10-22 23:03:32 +02:00
|
|
|
void dump_exec_info(FILE *f, fprintf_function cpu_fprintf);
|
2012-07-20 10:37:54 +02:00
|
|
|
ram_addr_t last_ram_offset(void);
|
2011-08-17 09:01:33 +02:00
|
|
|
void qemu_mutex_lock_ramlist(void);
|
|
|
|
void qemu_mutex_unlock_ramlist(void);
|
2010-03-12 17:54:58 +01:00
|
|
|
#endif /* !CONFIG_USER_ONLY */
|
|
|
|
|
2012-03-14 01:38:32 +01:00
|
|
|
int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
|
2010-03-12 17:54:58 +01:00
|
|
|
uint8_t *buf, int len, int is_write);
|
|
|
|
|
2003-06-15 22:02:25 +02:00
|
|
|
#endif /* CPU_ALL_H */
|