2004-10-01 00:13:50 +02:00
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|
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/*
|
2005-03-13 10:43:36 +01:00
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* QEMU TCX Frame buffer
|
2007-09-16 23:08:06 +02:00
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*
|
2005-03-13 10:43:36 +01:00
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* Copyright (c) 2003-2005 Fabrice Bellard
|
2007-09-16 23:08:06 +02:00
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*
|
2004-10-01 00:13:50 +02:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2009-07-12 21:21:36 +02:00
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2016-01-26 19:17:13 +01:00
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#include "qemu/osdep.h"
|
2019-05-23 16:35:08 +02:00
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|
#include "qemu-common.h"
|
include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 09:01:28 +01:00
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|
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#include "qapi/error.h"
|
2012-11-28 12:06:30 +01:00
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|
|
#include "ui/console.h"
|
|
|
|
#include "ui/pixel_ops.h"
|
2013-11-02 17:03:50 +01:00
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|
|
#include "hw/loader.h"
|
2019-08-12 07:23:51 +02:00
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|
#include "hw/qdev-properties.h"
|
2013-02-04 15:40:22 +01:00
|
|
|
#include "hw/sysbus.h"
|
2019-08-12 07:23:45 +02:00
|
|
|
#include "migration/vmstate.h"
|
2015-03-17 18:29:20 +01:00
|
|
|
#include "qemu/error-report.h"
|
2019-05-23 16:35:07 +02:00
|
|
|
#include "qemu/module.h"
|
2004-10-01 00:13:50 +02:00
|
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|
|
2013-11-02 17:03:50 +01:00
|
|
|
#define TCX_ROM_FILE "QEMU,tcx.bin"
|
|
|
|
#define FCODE_MAX_ROM_SIZE 0x10000
|
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|
2004-10-01 00:13:50 +02:00
|
|
|
#define MAXX 1024
|
|
|
|
#define MAXY 768
|
2014-09-13 11:44:07 +02:00
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|
|
#define TCX_DAC_NREGS 16
|
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|
#define TCX_THC_NREGS 0x1000
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|
|
#define TCX_DHC_NREGS 0x4000
|
2007-05-06 19:39:55 +02:00
|
|
|
#define TCX_TEC_NREGS 0x1000
|
2014-09-13 11:44:07 +02:00
|
|
|
#define TCX_ALT_NREGS 0x8000
|
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|
#define TCX_STIP_NREGS 0x800000
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|
#define TCX_BLIT_NREGS 0x800000
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#define TCX_RSTIP_NREGS 0x800000
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|
#define TCX_RBLIT_NREGS 0x800000
|
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|
#define TCX_THC_MISC 0x818
|
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|
|
#define TCX_THC_CURSXY 0x8fc
|
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|
#define TCX_THC_CURSMASK 0x900
|
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|
|
#define TCX_THC_CURSBITS 0x980
|
2004-10-01 00:13:50 +02:00
|
|
|
|
2013-07-25 01:13:54 +02:00
|
|
|
#define TYPE_TCX "SUNW,tcx"
|
|
|
|
#define TCX(obj) OBJECT_CHECK(TCXState, (obj), TYPE_TCX)
|
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|
|
|
2004-10-01 00:13:50 +02:00
|
|
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typedef struct TCXState {
|
2013-07-25 01:13:54 +02:00
|
|
|
SysBusDevice parent_obj;
|
|
|
|
|
2013-03-05 15:24:14 +01:00
|
|
|
QemuConsole *con;
|
2014-09-13 11:44:07 +02:00
|
|
|
qemu_irq irq;
|
2004-10-04 23:23:09 +02:00
|
|
|
uint8_t *vram;
|
2007-04-21 21:45:49 +02:00
|
|
|
uint32_t *vram24, *cplane;
|
2013-11-02 17:03:50 +01:00
|
|
|
hwaddr prom_addr;
|
|
|
|
MemoryRegion rom;
|
2011-10-05 18:26:24 +02:00
|
|
|
MemoryRegion vram_mem;
|
|
|
|
MemoryRegion vram_8bit;
|
|
|
|
MemoryRegion vram_24bit;
|
2014-09-13 11:44:07 +02:00
|
|
|
MemoryRegion stip;
|
|
|
|
MemoryRegion blit;
|
2011-10-05 18:26:24 +02:00
|
|
|
MemoryRegion vram_cplane;
|
2014-09-13 11:44:07 +02:00
|
|
|
MemoryRegion rstip;
|
|
|
|
MemoryRegion rblit;
|
2011-10-05 18:26:24 +02:00
|
|
|
MemoryRegion tec;
|
2014-09-13 11:44:07 +02:00
|
|
|
MemoryRegion dac;
|
|
|
|
MemoryRegion thc;
|
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|
MemoryRegion dhc;
|
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|
MemoryRegion alt;
|
2011-10-05 18:26:24 +02:00
|
|
|
MemoryRegion thc24;
|
2014-09-13 11:44:07 +02:00
|
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|
2011-10-05 18:26:24 +02:00
|
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|
ram_addr_t vram24_offset, cplane_offset;
|
2014-09-13 11:44:07 +02:00
|
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uint32_t tmpblit;
|
2009-07-15 13:43:31 +02:00
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uint32_t vram_size;
|
2014-09-13 11:44:07 +02:00
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uint32_t palette[260];
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uint8_t r[260], g[260], b[260];
|
2011-08-07 21:13:24 +02:00
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uint16_t width, height, depth;
|
2005-03-13 10:43:36 +01:00
|
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|
uint8_t dac_index, dac_state;
|
2014-09-13 11:44:07 +02:00
|
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|
uint32_t thcmisc;
|
|
|
|
uint32_t cursmask[32];
|
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|
|
uint32_t cursbits[32];
|
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|
|
uint16_t cursx;
|
|
|
|
uint16_t cursy;
|
2004-10-01 00:13:50 +02:00
|
|
|
} TCXState;
|
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|
2017-04-05 10:02:46 +02:00
|
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|
static void tcx_set_dirty(TCXState *s, ram_addr_t addr, int len)
|
2009-07-16 15:45:57 +02:00
|
|
|
{
|
2017-04-05 10:02:46 +02:00
|
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memory_region_set_dirty(&s->vram_mem, addr, len);
|
2017-04-05 10:02:46 +02:00
|
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|
|
|
|
if (s->depth == 24) {
|
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memory_region_set_dirty(&s->vram_mem, s->vram24_offset + addr * 4,
|
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|
|
len * 4);
|
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|
memory_region_set_dirty(&s->vram_mem, s->cplane_offset + addr * 4,
|
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|
|
len * 4);
|
|
|
|
}
|
2009-07-16 15:45:57 +02:00
|
|
|
}
|
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|
|
|
2017-05-10 22:52:31 +02:00
|
|
|
static int tcx_check_dirty(TCXState *s, DirtyBitmapSnapshot *snap,
|
|
|
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ram_addr_t addr, int len)
|
2009-07-16 15:45:57 +02:00
|
|
|
{
|
2014-09-13 11:44:07 +02:00
|
|
|
int ret;
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|
2017-05-10 22:52:31 +02:00
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ret = memory_region_snapshot_get_dirty(&s->vram_mem, snap, addr, len);
|
2017-04-05 10:02:46 +02:00
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|
if (s->depth == 24) {
|
2017-05-10 22:52:31 +02:00
|
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|
ret |= memory_region_snapshot_get_dirty(&s->vram_mem, snap,
|
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s->vram24_offset + addr * 4, len * 4);
|
|
|
|
ret |= memory_region_snapshot_get_dirty(&s->vram_mem, snap,
|
|
|
|
s->cplane_offset + addr * 4, len * 4);
|
2017-04-05 10:02:46 +02:00
|
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|
}
|
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|
2014-09-13 11:44:07 +02:00
|
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return ret;
|
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|
}
|
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|
2006-09-09 13:31:34 +02:00
|
|
|
static void update_palette_entries(TCXState *s, int start, int end)
|
|
|
|
{
|
2013-03-05 15:24:14 +01:00
|
|
|
DisplaySurface *surface = qemu_console_surface(s->con);
|
2006-09-09 13:31:34 +02:00
|
|
|
int i;
|
2013-03-05 15:24:14 +01:00
|
|
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|
for (i = start; i < end; i++) {
|
2017-04-05 10:02:47 +02:00
|
|
|
if (is_surface_bgr(surface)) {
|
|
|
|
s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]);
|
|
|
|
} else {
|
|
|
|
s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
|
2006-09-09 13:31:34 +02:00
|
|
|
}
|
|
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|
}
|
2017-04-05 10:02:46 +02:00
|
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|
tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
|
2006-09-09 13:31:34 +02:00
|
|
|
}
|
|
|
|
|
2007-09-16 23:08:06 +02:00
|
|
|
static void tcx_draw_line32(TCXState *s1, uint8_t *d,
|
2007-10-06 13:28:21 +02:00
|
|
|
const uint8_t *s, int width)
|
2004-10-01 00:13:50 +02:00
|
|
|
{
|
2004-12-20 00:18:01 +01:00
|
|
|
int x;
|
|
|
|
uint8_t val;
|
2006-12-21 18:24:45 +01:00
|
|
|
uint32_t *p = (uint32_t *)d;
|
2004-12-20 00:18:01 +01:00
|
|
|
|
2014-09-13 11:44:07 +02:00
|
|
|
for (x = 0; x < width; x++) {
|
2007-10-06 13:28:21 +02:00
|
|
|
val = *s++;
|
2006-12-21 18:24:45 +01:00
|
|
|
*p++ = s1->palette[val];
|
2004-12-20 00:18:01 +01:00
|
|
|
}
|
2004-10-01 00:13:50 +02:00
|
|
|
}
|
|
|
|
|
2014-09-13 11:44:07 +02:00
|
|
|
static void tcx_draw_cursor32(TCXState *s1, uint8_t *d,
|
|
|
|
int y, int width)
|
|
|
|
{
|
|
|
|
int x, len;
|
|
|
|
uint32_t mask, bits;
|
|
|
|
uint32_t *p = (uint32_t *)d;
|
|
|
|
|
|
|
|
y = y - s1->cursy;
|
|
|
|
mask = s1->cursmask[y];
|
|
|
|
bits = s1->cursbits[y];
|
|
|
|
len = MIN(width - s1->cursx, 32);
|
|
|
|
p = &p[s1->cursx];
|
|
|
|
for (x = 0; x < len; x++) {
|
|
|
|
if (mask & 0x80000000) {
|
|
|
|
if (bits & 0x80000000) {
|
|
|
|
*p = s1->palette[259];
|
|
|
|
} else {
|
|
|
|
*p = s1->palette[258];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
p++;
|
|
|
|
mask <<= 1;
|
|
|
|
bits <<= 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-07-24 13:26:38 +02:00
|
|
|
/*
|
|
|
|
XXX Could be much more optimal:
|
|
|
|
* detect if line/page/whole screen is in 24 bit mode
|
|
|
|
* if destination is also BGR, use memcpy
|
|
|
|
*/
|
2007-04-21 21:45:49 +02:00
|
|
|
static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
|
|
|
|
const uint8_t *s, int width,
|
|
|
|
const uint32_t *cplane,
|
|
|
|
const uint32_t *s24)
|
|
|
|
{
|
2013-03-05 15:24:14 +01:00
|
|
|
DisplaySurface *surface = qemu_console_surface(s1->con);
|
2009-03-13 16:02:13 +01:00
|
|
|
int x, bgr, r, g, b;
|
2008-07-24 13:26:38 +02:00
|
|
|
uint8_t val, *p8;
|
2007-04-21 21:45:49 +02:00
|
|
|
uint32_t *p = (uint32_t *)d;
|
|
|
|
uint32_t dval;
|
2013-03-05 15:24:14 +01:00
|
|
|
bgr = is_surface_bgr(surface);
|
2007-04-21 21:45:49 +02:00
|
|
|
for(x = 0; x < width; x++, s++, s24++) {
|
2014-09-13 11:44:07 +02:00
|
|
|
if (be32_to_cpu(*cplane) & 0x03000000) {
|
|
|
|
/* 24-bit direct, BGR order */
|
2008-07-24 13:26:38 +02:00
|
|
|
p8 = (uint8_t *)s24;
|
|
|
|
p8++;
|
|
|
|
b = *p8++;
|
|
|
|
g = *p8++;
|
2010-01-13 19:58:51 +01:00
|
|
|
r = *p8;
|
2009-03-13 16:02:13 +01:00
|
|
|
if (bgr)
|
|
|
|
dval = rgb_to_pixel32bgr(r, g, b);
|
|
|
|
else
|
|
|
|
dval = rgb_to_pixel32(r, g, b);
|
2007-04-21 21:45:49 +02:00
|
|
|
} else {
|
2014-09-13 11:44:07 +02:00
|
|
|
/* 8-bit pseudocolor */
|
2007-04-21 21:45:49 +02:00
|
|
|
val = *s;
|
|
|
|
dval = s1->palette[val];
|
|
|
|
}
|
|
|
|
*p++ = dval;
|
2014-09-13 11:44:07 +02:00
|
|
|
cplane++;
|
2007-04-21 21:45:49 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2004-12-20 00:18:01 +01:00
|
|
|
/* Fixed line length 1024 allows us to do nice tricks not possible on
|
|
|
|
VGA... */
|
2014-09-13 11:44:07 +02:00
|
|
|
|
2006-04-09 03:06:34 +02:00
|
|
|
static void tcx_update_display(void *opaque)
|
2004-10-01 00:13:50 +02:00
|
|
|
{
|
2004-12-20 00:18:01 +01:00
|
|
|
TCXState *ts = opaque;
|
2013-03-05 15:24:14 +01:00
|
|
|
DisplaySurface *surface = qemu_console_surface(ts->con);
|
2017-05-10 22:52:31 +02:00
|
|
|
ram_addr_t page;
|
|
|
|
DirtyBitmapSnapshot *snap = NULL;
|
2006-08-03 00:19:33 +02:00
|
|
|
int y, y_start, dd, ds;
|
2004-12-20 00:18:01 +01:00
|
|
|
uint8_t *d, *s;
|
|
|
|
|
2017-04-05 10:02:47 +02:00
|
|
|
if (surface_bits_per_pixel(surface) != 32) {
|
2007-10-06 13:28:21 +02:00
|
|
|
return;
|
2013-03-05 15:24:14 +01:00
|
|
|
}
|
|
|
|
|
2011-10-05 18:26:24 +02:00
|
|
|
page = 0;
|
2004-12-20 00:18:01 +01:00
|
|
|
y_start = -1;
|
2013-03-05 15:24:14 +01:00
|
|
|
d = surface_data(surface);
|
2005-03-13 10:43:36 +01:00
|
|
|
s = ts->vram;
|
2013-03-05 15:24:14 +01:00
|
|
|
dd = surface_stride(surface);
|
2004-12-20 00:18:01 +01:00
|
|
|
ds = 1024;
|
|
|
|
|
2017-05-10 22:52:31 +02:00
|
|
|
snap = memory_region_snapshot_and_clear_dirty(&ts->vram_mem, 0x0,
|
|
|
|
memory_region_size(&ts->vram_mem),
|
|
|
|
DIRTY_MEMORY_VGA);
|
|
|
|
|
2017-04-05 10:02:47 +02:00
|
|
|
for (y = 0; y < ts->height; y++, page += ds) {
|
2017-05-10 22:52:31 +02:00
|
|
|
if (tcx_check_dirty(ts, snap, page, ds)) {
|
2007-10-06 13:28:21 +02:00
|
|
|
if (y_start < 0)
|
2004-12-20 00:18:01 +01:00
|
|
|
y_start = y;
|
2014-09-13 11:44:07 +02:00
|
|
|
|
2017-04-05 10:02:47 +02:00
|
|
|
tcx_draw_line32(ts, d, s, ts->width);
|
2014-09-13 11:44:07 +02:00
|
|
|
if (y >= ts->cursy && y < ts->cursy + 32 && ts->cursx < ts->width) {
|
2017-04-05 10:02:47 +02:00
|
|
|
tcx_draw_cursor32(ts, d, y, ts->width);
|
2014-09-13 11:44:07 +02:00
|
|
|
}
|
2007-10-06 13:28:21 +02:00
|
|
|
} else {
|
2004-12-20 00:18:01 +01:00
|
|
|
if (y_start >= 0) {
|
|
|
|
/* flush to display */
|
2013-03-05 15:24:14 +01:00
|
|
|
dpy_gfx_update(ts->con, 0, y_start,
|
2012-09-28 15:02:08 +02:00
|
|
|
ts->width, y - y_start);
|
2004-12-20 00:18:01 +01:00
|
|
|
y_start = -1;
|
|
|
|
}
|
2007-10-06 13:28:21 +02:00
|
|
|
}
|
2017-04-05 10:02:47 +02:00
|
|
|
s += ds;
|
|
|
|
d += dd;
|
2004-12-20 00:18:01 +01:00
|
|
|
}
|
|
|
|
if (y_start >= 0) {
|
2007-10-06 13:28:21 +02:00
|
|
|
/* flush to display */
|
2013-03-05 15:24:14 +01:00
|
|
|
dpy_gfx_update(ts->con, 0, y_start,
|
2012-09-28 15:02:08 +02:00
|
|
|
ts->width, y - y_start);
|
2004-12-20 00:18:01 +01:00
|
|
|
}
|
2017-05-10 22:52:31 +02:00
|
|
|
g_free(snap);
|
2004-10-01 00:13:50 +02:00
|
|
|
}
|
|
|
|
|
2007-04-21 21:45:49 +02:00
|
|
|
static void tcx24_update_display(void *opaque)
|
|
|
|
{
|
|
|
|
TCXState *ts = opaque;
|
2013-03-05 15:24:14 +01:00
|
|
|
DisplaySurface *surface = qemu_console_surface(ts->con);
|
2017-05-10 22:52:31 +02:00
|
|
|
ram_addr_t page;
|
|
|
|
DirtyBitmapSnapshot *snap = NULL;
|
2007-04-21 21:45:49 +02:00
|
|
|
int y, y_start, dd, ds;
|
|
|
|
uint8_t *d, *s;
|
|
|
|
uint32_t *cptr, *s24;
|
|
|
|
|
2013-03-05 15:24:14 +01:00
|
|
|
if (surface_bits_per_pixel(surface) != 32) {
|
2007-04-21 21:45:49 +02:00
|
|
|
return;
|
2013-03-05 15:24:14 +01:00
|
|
|
}
|
|
|
|
|
2011-10-05 18:26:24 +02:00
|
|
|
page = 0;
|
2007-04-21 21:45:49 +02:00
|
|
|
y_start = -1;
|
2013-03-05 15:24:14 +01:00
|
|
|
d = surface_data(surface);
|
2007-04-21 21:45:49 +02:00
|
|
|
s = ts->vram;
|
|
|
|
s24 = ts->vram24;
|
|
|
|
cptr = ts->cplane;
|
2013-03-05 15:24:14 +01:00
|
|
|
dd = surface_stride(surface);
|
2007-04-21 21:45:49 +02:00
|
|
|
ds = 1024;
|
|
|
|
|
2017-05-10 22:52:31 +02:00
|
|
|
snap = memory_region_snapshot_and_clear_dirty(&ts->vram_mem, 0x0,
|
|
|
|
memory_region_size(&ts->vram_mem),
|
|
|
|
DIRTY_MEMORY_VGA);
|
|
|
|
|
2017-04-05 10:02:47 +02:00
|
|
|
for (y = 0; y < ts->height; y++, page += ds) {
|
2017-05-10 22:52:31 +02:00
|
|
|
if (tcx_check_dirty(ts, snap, page, ds)) {
|
2007-04-21 21:45:49 +02:00
|
|
|
if (y_start < 0)
|
|
|
|
y_start = y;
|
2017-05-10 22:52:31 +02:00
|
|
|
|
2007-04-21 21:45:49 +02:00
|
|
|
tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
|
2014-09-13 11:44:07 +02:00
|
|
|
if (y >= ts->cursy && y < ts->cursy+32 && ts->cursx < ts->width) {
|
|
|
|
tcx_draw_cursor32(ts, d, y, ts->width);
|
|
|
|
}
|
2007-04-21 21:45:49 +02:00
|
|
|
} else {
|
|
|
|
if (y_start >= 0) {
|
|
|
|
/* flush to display */
|
2013-03-05 15:24:14 +01:00
|
|
|
dpy_gfx_update(ts->con, 0, y_start,
|
2012-09-28 15:02:08 +02:00
|
|
|
ts->width, y - y_start);
|
2007-04-21 21:45:49 +02:00
|
|
|
y_start = -1;
|
|
|
|
}
|
|
|
|
}
|
2017-04-05 10:02:47 +02:00
|
|
|
d += dd;
|
|
|
|
s += ds;
|
|
|
|
cptr += ds;
|
|
|
|
s24 += ds;
|
2007-04-21 21:45:49 +02:00
|
|
|
}
|
|
|
|
if (y_start >= 0) {
|
|
|
|
/* flush to display */
|
2013-03-05 15:24:14 +01:00
|
|
|
dpy_gfx_update(ts->con, 0, y_start,
|
2012-09-28 15:02:08 +02:00
|
|
|
ts->width, y - y_start);
|
2007-04-21 21:45:49 +02:00
|
|
|
}
|
2017-05-10 22:52:31 +02:00
|
|
|
g_free(snap);
|
2007-04-21 21:45:49 +02:00
|
|
|
}
|
|
|
|
|
2006-04-09 03:06:34 +02:00
|
|
|
static void tcx_invalidate_display(void *opaque)
|
2004-10-01 00:13:50 +02:00
|
|
|
{
|
2004-12-20 00:18:01 +01:00
|
|
|
TCXState *s = opaque;
|
|
|
|
|
2017-04-05 10:02:46 +02:00
|
|
|
tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
|
2013-03-05 15:24:14 +01:00
|
|
|
qemu_console_resize(s->con, s->width, s->height);
|
2004-10-01 00:13:50 +02:00
|
|
|
}
|
|
|
|
|
2007-04-21 21:45:49 +02:00
|
|
|
static void tcx24_invalidate_display(void *opaque)
|
|
|
|
{
|
|
|
|
TCXState *s = opaque;
|
|
|
|
|
2017-04-05 10:02:46 +02:00
|
|
|
tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
|
2013-03-05 15:24:14 +01:00
|
|
|
qemu_console_resize(s->con, s->width, s->height);
|
2007-04-21 21:45:49 +02:00
|
|
|
}
|
|
|
|
|
2009-09-29 22:48:21 +02:00
|
|
|
static int vmstate_tcx_post_load(void *opaque, int version_id)
|
2004-10-01 00:13:50 +02:00
|
|
|
{
|
|
|
|
TCXState *s = opaque;
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2006-09-09 13:31:34 +02:00
|
|
|
update_palette_entries(s, 0, 256);
|
2017-04-05 10:02:46 +02:00
|
|
|
tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem));
|
2004-12-20 00:18:01 +01:00
|
|
|
return 0;
|
2004-10-01 00:13:50 +02:00
|
|
|
}
|
|
|
|
|
2009-08-28 22:43:01 +02:00
|
|
|
static const VMStateDescription vmstate_tcx = {
|
|
|
|
.name ="tcx",
|
|
|
|
.version_id = 4,
|
|
|
|
.minimum_version_id = 4,
|
2009-09-10 03:04:30 +02:00
|
|
|
.post_load = vmstate_tcx_post_load,
|
2014-04-16 16:01:33 +02:00
|
|
|
.fields = (VMStateField[]) {
|
2009-08-28 22:43:01 +02:00
|
|
|
VMSTATE_UINT16(height, TCXState),
|
|
|
|
VMSTATE_UINT16(width, TCXState),
|
|
|
|
VMSTATE_UINT16(depth, TCXState),
|
|
|
|
VMSTATE_BUFFER(r, TCXState),
|
|
|
|
VMSTATE_BUFFER(g, TCXState),
|
|
|
|
VMSTATE_BUFFER(b, TCXState),
|
|
|
|
VMSTATE_UINT8(dac_index, TCXState),
|
|
|
|
VMSTATE_UINT8(dac_state, TCXState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2009-09-16 12:40:27 +02:00
|
|
|
static void tcx_reset(DeviceState *d)
|
2004-10-01 00:13:50 +02:00
|
|
|
{
|
2013-07-25 01:13:54 +02:00
|
|
|
TCXState *s = TCX(d);
|
2004-12-20 00:18:01 +01:00
|
|
|
|
|
|
|
/* Initialize palette */
|
2014-09-13 11:44:07 +02:00
|
|
|
memset(s->r, 0, 260);
|
|
|
|
memset(s->g, 0, 260);
|
|
|
|
memset(s->b, 0, 260);
|
2004-12-20 00:18:01 +01:00
|
|
|
s->r[255] = s->g[255] = s->b[255] = 255;
|
2014-09-13 11:44:07 +02:00
|
|
|
s->r[256] = s->g[256] = s->b[256] = 255;
|
|
|
|
s->r[258] = s->g[258] = s->b[258] = 255;
|
|
|
|
update_palette_entries(s, 0, 260);
|
2004-12-20 00:18:01 +01:00
|
|
|
memset(s->vram, 0, MAXX*MAXY);
|
2011-10-05 18:26:24 +02:00
|
|
|
memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4),
|
|
|
|
DIRTY_MEMORY_VGA);
|
2005-03-13 10:43:36 +01:00
|
|
|
s->dac_index = 0;
|
|
|
|
s->dac_state = 0;
|
2014-09-13 11:44:07 +02:00
|
|
|
s->cursx = 0xf000; /* Put cursor off screen */
|
|
|
|
s->cursy = 0xf000;
|
2005-03-13 10:43:36 +01:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint64_t tcx_dac_readl(void *opaque, hwaddr addr,
|
2011-10-05 18:26:24 +02:00
|
|
|
unsigned size)
|
2005-03-13 10:43:36 +01:00
|
|
|
{
|
2014-09-13 11:44:07 +02:00
|
|
|
TCXState *s = opaque;
|
|
|
|
uint32_t val = 0;
|
|
|
|
|
|
|
|
switch (s->dac_state) {
|
|
|
|
case 0:
|
|
|
|
val = s->r[s->dac_index] << 24;
|
|
|
|
s->dac_state++;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
val = s->g[s->dac_index] << 24;
|
|
|
|
s->dac_state++;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
val = s->b[s->dac_index] << 24;
|
|
|
|
s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */
|
2019-12-18 20:25:22 +01:00
|
|
|
/* fall through */
|
2014-09-13 11:44:07 +02:00
|
|
|
default:
|
|
|
|
s->dac_state = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return val;
|
2005-03-13 10:43:36 +01:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val,
|
2011-10-05 18:26:24 +02:00
|
|
|
unsigned size)
|
2005-03-13 10:43:36 +01:00
|
|
|
{
|
|
|
|
TCXState *s = opaque;
|
2014-09-13 11:44:07 +02:00
|
|
|
unsigned index;
|
2005-03-13 10:43:36 +01:00
|
|
|
|
2008-12-02 18:47:02 +01:00
|
|
|
switch (addr) {
|
2014-09-13 11:44:07 +02:00
|
|
|
case 0: /* Address */
|
2007-10-06 13:28:21 +02:00
|
|
|
s->dac_index = val >> 24;
|
|
|
|
s->dac_state = 0;
|
|
|
|
break;
|
2014-09-13 11:44:07 +02:00
|
|
|
case 4: /* Pixel colours */
|
|
|
|
case 12: /* Overlay (cursor) colours */
|
|
|
|
if (addr & 8) {
|
|
|
|
index = (s->dac_index & 3) + 256;
|
|
|
|
} else {
|
|
|
|
index = s->dac_index;
|
|
|
|
}
|
2007-10-06 13:28:21 +02:00
|
|
|
switch (s->dac_state) {
|
|
|
|
case 0:
|
2014-09-13 11:44:07 +02:00
|
|
|
s->r[index] = val >> 24;
|
|
|
|
update_palette_entries(s, index, index + 1);
|
2007-10-06 13:28:21 +02:00
|
|
|
s->dac_state++;
|
|
|
|
break;
|
|
|
|
case 1:
|
2014-09-13 11:44:07 +02:00
|
|
|
s->g[index] = val >> 24;
|
|
|
|
update_palette_entries(s, index, index + 1);
|
2007-10-06 13:28:21 +02:00
|
|
|
s->dac_state++;
|
|
|
|
break;
|
|
|
|
case 2:
|
2014-09-13 11:44:07 +02:00
|
|
|
s->b[index] = val >> 24;
|
|
|
|
update_palette_entries(s, index, index + 1);
|
|
|
|
s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */
|
2019-12-18 20:25:22 +01:00
|
|
|
/* fall through */
|
2007-10-06 13:28:21 +02:00
|
|
|
default:
|
|
|
|
s->dac_state = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
2014-09-13 11:44:07 +02:00
|
|
|
default: /* Control registers */
|
2007-10-06 13:28:21 +02:00
|
|
|
break;
|
2005-03-13 10:43:36 +01:00
|
|
|
}
|
2004-10-01 00:13:50 +02:00
|
|
|
}
|
|
|
|
|
2011-10-05 18:26:24 +02:00
|
|
|
static const MemoryRegionOps tcx_dac_ops = {
|
|
|
|
.read = tcx_dac_readl,
|
|
|
|
.write = tcx_dac_writel,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
2005-03-13 10:43:36 +01:00
|
|
|
};
|
|
|
|
|
2014-09-13 11:44:07 +02:00
|
|
|
static uint64_t tcx_stip_readl(void *opaque, hwaddr addr,
|
|
|
|
unsigned size)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tcx_stip_writel(void *opaque, hwaddr addr,
|
|
|
|
uint64_t val, unsigned size)
|
|
|
|
{
|
|
|
|
TCXState *s = opaque;
|
|
|
|
int i;
|
|
|
|
uint32_t col;
|
|
|
|
|
|
|
|
if (!(addr & 4)) {
|
|
|
|
s->tmpblit = val;
|
|
|
|
} else {
|
|
|
|
addr = (addr >> 3) & 0xfffff;
|
|
|
|
col = cpu_to_be32(s->tmpblit);
|
|
|
|
if (s->depth == 24) {
|
|
|
|
for (i = 0; i < 32; i++) {
|
|
|
|
if (val & 0x80000000) {
|
|
|
|
s->vram[addr + i] = s->tmpblit;
|
|
|
|
s->vram24[addr + i] = col;
|
|
|
|
}
|
|
|
|
val <<= 1;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
for (i = 0; i < 32; i++) {
|
|
|
|
if (val & 0x80000000) {
|
|
|
|
s->vram[addr + i] = s->tmpblit;
|
|
|
|
}
|
|
|
|
val <<= 1;
|
|
|
|
}
|
|
|
|
}
|
2017-04-05 10:02:47 +02:00
|
|
|
tcx_set_dirty(s, addr, 32);
|
2014-09-13 11:44:07 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tcx_rstip_writel(void *opaque, hwaddr addr,
|
|
|
|
uint64_t val, unsigned size)
|
|
|
|
{
|
|
|
|
TCXState *s = opaque;
|
|
|
|
int i;
|
|
|
|
uint32_t col;
|
|
|
|
|
|
|
|
if (!(addr & 4)) {
|
|
|
|
s->tmpblit = val;
|
|
|
|
} else {
|
|
|
|
addr = (addr >> 3) & 0xfffff;
|
|
|
|
col = cpu_to_be32(s->tmpblit);
|
|
|
|
if (s->depth == 24) {
|
|
|
|
for (i = 0; i < 32; i++) {
|
|
|
|
if (val & 0x80000000) {
|
|
|
|
s->vram[addr + i] = s->tmpblit;
|
|
|
|
s->vram24[addr + i] = col;
|
|
|
|
s->cplane[addr + i] = col;
|
|
|
|
}
|
|
|
|
val <<= 1;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
for (i = 0; i < 32; i++) {
|
|
|
|
if (val & 0x80000000) {
|
|
|
|
s->vram[addr + i] = s->tmpblit;
|
|
|
|
}
|
|
|
|
val <<= 1;
|
|
|
|
}
|
|
|
|
}
|
2017-04-05 10:02:47 +02:00
|
|
|
tcx_set_dirty(s, addr, 32);
|
2014-09-13 11:44:07 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps tcx_stip_ops = {
|
|
|
|
.read = tcx_stip_readl,
|
|
|
|
.write = tcx_stip_writel,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static const MemoryRegionOps tcx_rstip_ops = {
|
|
|
|
.read = tcx_stip_readl,
|
|
|
|
.write = tcx_rstip_writel,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static uint64_t tcx_blit_readl(void *opaque, hwaddr addr,
|
|
|
|
unsigned size)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tcx_blit_writel(void *opaque, hwaddr addr,
|
|
|
|
uint64_t val, unsigned size)
|
|
|
|
{
|
|
|
|
TCXState *s = opaque;
|
|
|
|
uint32_t adsr, len;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (!(addr & 4)) {
|
|
|
|
s->tmpblit = val;
|
|
|
|
} else {
|
|
|
|
addr = (addr >> 3) & 0xfffff;
|
|
|
|
adsr = val & 0xffffff;
|
|
|
|
len = ((val >> 24) & 0x1f) + 1;
|
|
|
|
if (adsr == 0xffffff) {
|
|
|
|
memset(&s->vram[addr], s->tmpblit, len);
|
|
|
|
if (s->depth == 24) {
|
|
|
|
val = s->tmpblit & 0xffffff;
|
|
|
|
val = cpu_to_be32(val);
|
|
|
|
for (i = 0; i < len; i++) {
|
|
|
|
s->vram24[addr + i] = val;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
memcpy(&s->vram[addr], &s->vram[adsr], len);
|
|
|
|
if (s->depth == 24) {
|
|
|
|
memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4);
|
|
|
|
}
|
|
|
|
}
|
2017-04-05 10:02:47 +02:00
|
|
|
tcx_set_dirty(s, addr, len);
|
2014-09-13 11:44:07 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tcx_rblit_writel(void *opaque, hwaddr addr,
|
|
|
|
uint64_t val, unsigned size)
|
|
|
|
{
|
|
|
|
TCXState *s = opaque;
|
|
|
|
uint32_t adsr, len;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (!(addr & 4)) {
|
|
|
|
s->tmpblit = val;
|
|
|
|
} else {
|
|
|
|
addr = (addr >> 3) & 0xfffff;
|
|
|
|
adsr = val & 0xffffff;
|
|
|
|
len = ((val >> 24) & 0x1f) + 1;
|
|
|
|
if (adsr == 0xffffff) {
|
|
|
|
memset(&s->vram[addr], s->tmpblit, len);
|
|
|
|
if (s->depth == 24) {
|
|
|
|
val = s->tmpblit & 0xffffff;
|
|
|
|
val = cpu_to_be32(val);
|
|
|
|
for (i = 0; i < len; i++) {
|
|
|
|
s->vram24[addr + i] = val;
|
|
|
|
s->cplane[addr + i] = val;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
memcpy(&s->vram[addr], &s->vram[adsr], len);
|
|
|
|
if (s->depth == 24) {
|
|
|
|
memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4);
|
|
|
|
memcpy(&s->cplane[addr], &s->cplane[adsr], len * 4);
|
|
|
|
}
|
|
|
|
}
|
2017-04-05 10:02:47 +02:00
|
|
|
tcx_set_dirty(s, addr, len);
|
2014-09-13 11:44:07 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps tcx_blit_ops = {
|
|
|
|
.read = tcx_blit_readl,
|
|
|
|
.write = tcx_blit_writel,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static const MemoryRegionOps tcx_rblit_ops = {
|
|
|
|
.read = tcx_blit_readl,
|
|
|
|
.write = tcx_rblit_writel,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static void tcx_invalidate_cursor_position(TCXState *s)
|
|
|
|
{
|
|
|
|
int ymin, ymax, start, end;
|
|
|
|
|
|
|
|
/* invalidate only near the cursor */
|
|
|
|
ymin = s->cursy;
|
|
|
|
if (ymin >= s->height) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
ymax = MIN(s->height, ymin + 32);
|
|
|
|
start = ymin * 1024;
|
|
|
|
end = ymax * 1024;
|
|
|
|
|
2017-04-05 10:02:47 +02:00
|
|
|
tcx_set_dirty(s, start, end - start);
|
2014-09-13 11:44:07 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static uint64_t tcx_thc_readl(void *opaque, hwaddr addr,
|
|
|
|
unsigned size)
|
|
|
|
{
|
|
|
|
TCXState *s = opaque;
|
|
|
|
uint64_t val;
|
|
|
|
|
|
|
|
if (addr == TCX_THC_MISC) {
|
|
|
|
val = s->thcmisc | 0x02000000;
|
|
|
|
} else {
|
|
|
|
val = 0;
|
|
|
|
}
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tcx_thc_writel(void *opaque, hwaddr addr,
|
|
|
|
uint64_t val, unsigned size)
|
|
|
|
{
|
|
|
|
TCXState *s = opaque;
|
|
|
|
|
|
|
|
if (addr == TCX_THC_CURSXY) {
|
|
|
|
tcx_invalidate_cursor_position(s);
|
|
|
|
s->cursx = val >> 16;
|
|
|
|
s->cursy = val;
|
|
|
|
tcx_invalidate_cursor_position(s);
|
|
|
|
} else if (addr >= TCX_THC_CURSMASK && addr < TCX_THC_CURSMASK + 128) {
|
|
|
|
s->cursmask[(addr - TCX_THC_CURSMASK) >> 2] = val;
|
|
|
|
tcx_invalidate_cursor_position(s);
|
|
|
|
} else if (addr >= TCX_THC_CURSBITS && addr < TCX_THC_CURSBITS + 128) {
|
|
|
|
s->cursbits[(addr - TCX_THC_CURSBITS) >> 2] = val;
|
|
|
|
tcx_invalidate_cursor_position(s);
|
|
|
|
} else if (addr == TCX_THC_MISC) {
|
|
|
|
s->thcmisc = val;
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps tcx_thc_ops = {
|
|
|
|
.read = tcx_thc_readl,
|
|
|
|
.write = tcx_thc_writel,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static uint64_t tcx_dummy_readl(void *opaque, hwaddr addr,
|
2011-10-05 18:26:24 +02:00
|
|
|
unsigned size)
|
2007-05-06 19:39:55 +02:00
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-09-13 11:44:07 +02:00
|
|
|
static void tcx_dummy_writel(void *opaque, hwaddr addr,
|
2011-10-05 18:26:24 +02:00
|
|
|
uint64_t val, unsigned size)
|
2007-05-06 19:39:55 +02:00
|
|
|
{
|
2014-09-13 11:44:07 +02:00
|
|
|
return;
|
2007-05-06 19:39:55 +02:00
|
|
|
}
|
|
|
|
|
2014-09-13 11:44:07 +02:00
|
|
|
static const MemoryRegionOps tcx_dummy_ops = {
|
|
|
|
.read = tcx_dummy_readl,
|
|
|
|
.write = tcx_dummy_writel,
|
2011-10-05 18:26:24 +02:00
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
2007-05-06 19:39:55 +02:00
|
|
|
};
|
|
|
|
|
2013-03-13 14:04:18 +01:00
|
|
|
static const GraphicHwOps tcx_ops = {
|
|
|
|
.invalidate = tcx_invalidate_display,
|
|
|
|
.gfx_update = tcx_update_display,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const GraphicHwOps tcx24_ops = {
|
|
|
|
.invalidate = tcx24_invalidate_display,
|
|
|
|
.gfx_update = tcx24_update_display,
|
|
|
|
};
|
|
|
|
|
2014-05-24 13:44:53 +02:00
|
|
|
static void tcx_initfn(Object *obj)
|
|
|
|
{
|
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
|
|
|
TCXState *s = TCX(obj);
|
|
|
|
|
2020-02-24 19:50:29 +01:00
|
|
|
memory_region_init_rom_nomigrate(&s->rom, obj, "tcx.prom",
|
|
|
|
FCODE_MAX_ROM_SIZE, &error_fatal);
|
2014-05-24 13:44:53 +02:00
|
|
|
sysbus_init_mmio(sbd, &s->rom);
|
|
|
|
|
2014-09-13 11:44:07 +02:00
|
|
|
/* 2/STIP : Stippler */
|
2015-10-15 10:54:15 +02:00
|
|
|
memory_region_init_io(&s->stip, obj, &tcx_stip_ops, s, "tcx.stip",
|
2014-09-13 11:44:07 +02:00
|
|
|
TCX_STIP_NREGS);
|
|
|
|
sysbus_init_mmio(sbd, &s->stip);
|
|
|
|
|
|
|
|
/* 3/BLIT : Blitter */
|
2015-10-15 10:54:15 +02:00
|
|
|
memory_region_init_io(&s->blit, obj, &tcx_blit_ops, s, "tcx.blit",
|
2014-09-13 11:44:07 +02:00
|
|
|
TCX_BLIT_NREGS);
|
|
|
|
sysbus_init_mmio(sbd, &s->blit);
|
|
|
|
|
|
|
|
/* 5/RSTIP : Raw Stippler */
|
2015-10-15 10:54:15 +02:00
|
|
|
memory_region_init_io(&s->rstip, obj, &tcx_rstip_ops, s, "tcx.rstip",
|
2014-09-13 11:44:07 +02:00
|
|
|
TCX_RSTIP_NREGS);
|
|
|
|
sysbus_init_mmio(sbd, &s->rstip);
|
|
|
|
|
|
|
|
/* 6/RBLIT : Raw Blitter */
|
2015-10-15 10:54:15 +02:00
|
|
|
memory_region_init_io(&s->rblit, obj, &tcx_rblit_ops, s, "tcx.rblit",
|
2014-09-13 11:44:07 +02:00
|
|
|
TCX_RBLIT_NREGS);
|
|
|
|
sysbus_init_mmio(sbd, &s->rblit);
|
|
|
|
|
|
|
|
/* 7/TEC : ??? */
|
2015-10-15 10:54:15 +02:00
|
|
|
memory_region_init_io(&s->tec, obj, &tcx_dummy_ops, s, "tcx.tec",
|
|
|
|
TCX_TEC_NREGS);
|
2014-09-13 11:44:07 +02:00
|
|
|
sysbus_init_mmio(sbd, &s->tec);
|
|
|
|
|
|
|
|
/* 8/CMAP : DAC */
|
2015-10-15 10:54:15 +02:00
|
|
|
memory_region_init_io(&s->dac, obj, &tcx_dac_ops, s, "tcx.dac",
|
|
|
|
TCX_DAC_NREGS);
|
2014-05-24 13:44:53 +02:00
|
|
|
sysbus_init_mmio(sbd, &s->dac);
|
|
|
|
|
2014-09-13 11:44:07 +02:00
|
|
|
/* 9/THC : Cursor */
|
2015-10-15 10:54:15 +02:00
|
|
|
memory_region_init_io(&s->thc, obj, &tcx_thc_ops, s, "tcx.thc",
|
2014-09-13 11:44:07 +02:00
|
|
|
TCX_THC_NREGS);
|
|
|
|
sysbus_init_mmio(sbd, &s->thc);
|
2014-05-24 13:44:53 +02:00
|
|
|
|
2014-09-13 11:44:07 +02:00
|
|
|
/* 11/DHC : ??? */
|
2015-10-15 10:54:15 +02:00
|
|
|
memory_region_init_io(&s->dhc, obj, &tcx_dummy_ops, s, "tcx.dhc",
|
2014-09-13 11:44:07 +02:00
|
|
|
TCX_DHC_NREGS);
|
|
|
|
sysbus_init_mmio(sbd, &s->dhc);
|
|
|
|
|
|
|
|
/* 12/ALT : ??? */
|
2015-10-15 10:54:15 +02:00
|
|
|
memory_region_init_io(&s->alt, obj, &tcx_dummy_ops, s, "tcx.alt",
|
2014-09-13 11:44:07 +02:00
|
|
|
TCX_ALT_NREGS);
|
|
|
|
sysbus_init_mmio(sbd, &s->alt);
|
2014-05-24 13:44:53 +02:00
|
|
|
}
|
|
|
|
|
2014-05-24 13:19:44 +02:00
|
|
|
static void tcx_realizefn(DeviceState *dev, Error **errp)
|
2009-07-12 21:21:36 +02:00
|
|
|
{
|
2014-05-24 13:19:44 +02:00
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
2013-07-25 01:13:54 +02:00
|
|
|
TCXState *s = TCX(dev);
|
2011-10-05 18:26:24 +02:00
|
|
|
ram_addr_t vram_offset = 0;
|
2013-11-02 17:03:50 +01:00
|
|
|
int size, ret;
|
2009-04-10 00:21:07 +02:00
|
|
|
uint8_t *vram_base;
|
2013-11-02 17:03:50 +01:00
|
|
|
char *fcode_filename;
|
2009-04-10 00:21:07 +02:00
|
|
|
|
2017-07-07 16:42:49 +02:00
|
|
|
memory_region_init_ram_nomigrate(&s->vram_mem, OBJECT(s), "tcx.vram",
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 16:51:43 +02:00
|
|
|
s->vram_size * (1 + 4 + 4), &error_fatal);
|
2011-12-20 14:59:12 +01:00
|
|
|
vmstate_register_ram_global(&s->vram_mem);
|
2015-03-23 10:47:45 +01:00
|
|
|
memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA);
|
2011-10-05 18:26:24 +02:00
|
|
|
vram_base = memory_region_get_ram_ptr(&s->vram_mem);
|
2007-04-21 21:45:49 +02:00
|
|
|
|
2014-09-13 11:44:07 +02:00
|
|
|
/* 10/ROM : FCode ROM */
|
2013-11-02 17:03:50 +01:00
|
|
|
vmstate_register_ram_global(&s->rom);
|
|
|
|
fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, TCX_ROM_FILE);
|
|
|
|
if (fcode_filename) {
|
2017-04-05 10:02:47 +02:00
|
|
|
ret = load_image_mr(fcode_filename, &s->rom);
|
2015-05-28 13:13:45 +02:00
|
|
|
g_free(fcode_filename);
|
2013-11-02 17:03:50 +01:00
|
|
|
if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) {
|
2018-10-17 10:26:28 +02:00
|
|
|
warn_report("tcx: could not load prom '%s'", TCX_ROM_FILE);
|
2013-11-02 17:03:50 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-09-13 11:44:07 +02:00
|
|
|
/* 0/DFB8 : 8-bit plane */
|
2007-04-21 21:45:49 +02:00
|
|
|
s->vram = vram_base;
|
2009-07-15 13:43:31 +02:00
|
|
|
size = s->vram_size;
|
2013-06-07 03:25:08 +02:00
|
|
|
memory_region_init_alias(&s->vram_8bit, OBJECT(s), "tcx.vram.8bit",
|
2011-10-05 18:26:24 +02:00
|
|
|
&s->vram_mem, vram_offset, size);
|
2014-05-24 13:19:44 +02:00
|
|
|
sysbus_init_mmio(sbd, &s->vram_8bit);
|
2007-04-21 21:45:49 +02:00
|
|
|
vram_offset += size;
|
|
|
|
vram_base += size;
|
2004-12-20 00:18:01 +01:00
|
|
|
|
2014-09-13 11:44:07 +02:00
|
|
|
/* 1/DFB24 : 24bit plane */
|
|
|
|
size = s->vram_size * 4;
|
|
|
|
s->vram24 = (uint32_t *)vram_base;
|
|
|
|
s->vram24_offset = vram_offset;
|
|
|
|
memory_region_init_alias(&s->vram_24bit, OBJECT(s), "tcx.vram.24bit",
|
|
|
|
&s->vram_mem, vram_offset, size);
|
|
|
|
sysbus_init_mmio(sbd, &s->vram_24bit);
|
|
|
|
vram_offset += size;
|
|
|
|
vram_base += size;
|
|
|
|
|
|
|
|
/* 4/RDFB32 : Raw Framebuffer */
|
|
|
|
size = s->vram_size * 4;
|
|
|
|
s->cplane = (uint32_t *)vram_base;
|
|
|
|
s->cplane_offset = vram_offset;
|
|
|
|
memory_region_init_alias(&s->vram_cplane, OBJECT(s), "tcx.vram.cplane",
|
|
|
|
&s->vram_mem, vram_offset, size);
|
|
|
|
sysbus_init_mmio(sbd, &s->vram_cplane);
|
2009-07-12 21:21:36 +02:00
|
|
|
|
2014-09-13 11:44:07 +02:00
|
|
|
/* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
|
|
|
|
if (s->depth == 8) {
|
|
|
|
memory_region_init_io(&s->thc24, OBJECT(s), &tcx_dummy_ops, s,
|
|
|
|
"tcx.thc24", TCX_THC_NREGS);
|
|
|
|
sysbus_init_mmio(sbd, &s->thc24);
|
|
|
|
}
|
|
|
|
|
|
|
|
sysbus_init_irq(sbd, &s->irq);
|
2009-07-12 21:21:36 +02:00
|
|
|
|
2014-09-13 11:44:07 +02:00
|
|
|
if (s->depth == 8) {
|
2014-01-24 15:35:21 +01:00
|
|
|
s->con = graphic_console_init(DEVICE(dev), 0, &tcx_ops, s);
|
2014-09-13 11:44:07 +02:00
|
|
|
} else {
|
|
|
|
s->con = graphic_console_init(DEVICE(dev), 0, &tcx24_ops, s);
|
2007-04-21 21:45:49 +02:00
|
|
|
}
|
2014-09-13 11:44:07 +02:00
|
|
|
s->thcmisc = 0;
|
2004-12-20 00:18:01 +01:00
|
|
|
|
2013-03-05 15:24:14 +01:00
|
|
|
qemu_console_resize(s->con, s->width, s->height);
|
2004-10-01 00:13:50 +02:00
|
|
|
}
|
|
|
|
|
2012-01-24 20:12:29 +01:00
|
|
|
static Property tcx_properties[] = {
|
2014-02-08 11:01:53 +01:00
|
|
|
DEFINE_PROP_UINT32("vram_size", TCXState, vram_size, -1),
|
2012-01-24 20:12:29 +01:00
|
|
|
DEFINE_PROP_UINT16("width", TCXState, width, -1),
|
|
|
|
DEFINE_PROP_UINT16("height", TCXState, height, -1),
|
|
|
|
DEFINE_PROP_UINT16("depth", TCXState, depth, -1),
|
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
|
|
|
static void tcx_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-24 20:12:29 +01:00
|
|
|
|
2014-05-24 13:19:44 +02:00
|
|
|
dc->realize = tcx_realizefn;
|
2011-12-08 04:34:16 +01:00
|
|
|
dc->reset = tcx_reset;
|
|
|
|
dc->vmsd = &vmstate_tcx;
|
2020-01-10 16:30:32 +01:00
|
|
|
device_class_set_props(dc, tcx_properties);
|
2012-01-24 20:12:29 +01:00
|
|
|
}
|
|
|
|
|
2013-01-10 16:19:07 +01:00
|
|
|
static const TypeInfo tcx_info = {
|
2013-07-25 01:13:54 +02:00
|
|
|
.name = TYPE_TCX,
|
2011-12-08 04:34:16 +01:00
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(TCXState),
|
2014-05-24 13:44:53 +02:00
|
|
|
.instance_init = tcx_initfn,
|
2011-12-08 04:34:16 +01:00
|
|
|
.class_init = tcx_class_init,
|
2009-07-15 13:43:31 +02:00
|
|
|
};
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
static void tcx_register_types(void)
|
2009-07-12 21:21:36 +02:00
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
type_register_static(&tcx_info);
|
2009-07-12 21:21:36 +02:00
|
|
|
}
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
type_init(tcx_register_types)
|