2009-08-31 16:07:15 +02:00
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/*
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* QEMU PCI VGA Emulator.
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*
|
2012-10-15 08:02:56 +02:00
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* see docs/specs/standard-vga.txt for virtual hardware specs.
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*
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2009-08-31 16:07:15 +02:00
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* Copyright (c) 2003 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2019-05-23 16:35:07 +02:00
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2016-01-26 19:17:13 +01:00
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#include "qemu/osdep.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/pci/pci.h"
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2019-08-12 07:23:51 +02:00
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#include "hw/qdev-properties.h"
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2019-08-12 07:23:45 +02:00
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#include "migration/vmstate.h"
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2013-03-18 17:36:02 +01:00
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#include "vga_int.h"
|
2012-11-28 12:06:30 +01:00
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#include "ui/pixel_ops.h"
|
2019-05-23 16:35:07 +02:00
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|
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#include "qemu/module.h"
|
2012-12-17 18:20:00 +01:00
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|
#include "qemu/timer.h"
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2013-02-04 15:40:22 +01:00
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|
#include "hw/loader.h"
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2018-09-25 09:56:46 +02:00
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#include "hw/display/edid.h"
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2009-08-31 16:07:15 +02:00
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|
2012-10-15 08:02:55 +02:00
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|
|
enum vga_pci_flags {
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PCI_VGA_FLAG_ENABLE_MMIO = 1,
|
2014-09-23 12:45:56 +02:00
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|
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PCI_VGA_FLAG_ENABLE_QEXT = 2,
|
2018-09-25 09:56:46 +02:00
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PCI_VGA_FLAG_ENABLE_EDID = 3,
|
2012-10-15 08:02:55 +02:00
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|
|
};
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2009-08-31 16:07:15 +02:00
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typedef struct PCIVGAState {
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PCIDevice dev;
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VGACommonState vga;
|
2012-10-15 08:02:55 +02:00
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uint32_t flags;
|
2018-09-25 09:56:46 +02:00
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|
|
qemu_edid_info edid_info;
|
2012-10-15 08:02:55 +02:00
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|
|
MemoryRegion mmio;
|
2018-09-25 09:56:46 +02:00
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MemoryRegion mrs[4];
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|
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uint8_t edid[256];
|
2009-08-31 16:07:15 +02:00
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|
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} PCIVGAState;
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|
2015-05-12 11:27:08 +02:00
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#define TYPE_PCI_VGA "pci-vga"
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|
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#define PCI_VGA(obj) OBJECT_CHECK(PCIVGAState, (obj), TYPE_PCI_VGA)
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2009-10-14 15:42:44 +02:00
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static const VMStateDescription vmstate_vga_pci = {
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|
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.name = "vga",
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|
|
.version_id = 2,
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|
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.minimum_version_id = 2,
|
2014-04-16 15:32:32 +02:00
|
|
|
.fields = (VMStateField[]) {
|
2009-10-14 15:42:44 +02:00
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|
|
VMSTATE_PCI_DEVICE(dev, PCIVGAState),
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|
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VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState),
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|
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VMSTATE_END_OF_LIST()
|
2009-08-31 16:07:15 +02:00
|
|
|
}
|
2009-10-14 15:42:44 +02:00
|
|
|
};
|
2009-08-31 16:07:15 +02:00
|
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|
|
2012-10-23 12:30:10 +02:00
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|
|
static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
|
2012-10-15 08:02:55 +02:00
|
|
|
unsigned size)
|
|
|
|
{
|
2015-04-08 09:09:49 +02:00
|
|
|
VGACommonState *s = ptr;
|
2012-10-15 08:02:55 +02:00
|
|
|
uint64_t ret = 0;
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|
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|
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|
|
switch (size) {
|
|
|
|
case 1:
|
2015-04-08 09:09:49 +02:00
|
|
|
ret = vga_ioport_read(s, addr + 0x3c0);
|
2012-10-15 08:02:55 +02:00
|
|
|
break;
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|
|
|
case 2:
|
2015-04-08 09:09:49 +02:00
|
|
|
ret = vga_ioport_read(s, addr + 0x3c0);
|
|
|
|
ret |= vga_ioport_read(s, addr + 0x3c1) << 8;
|
2012-10-15 08:02:55 +02:00
|
|
|
break;
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|
|
|
}
|
|
|
|
return ret;
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|
|
|
}
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|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void pci_vga_ioport_write(void *ptr, hwaddr addr,
|
2012-10-15 08:02:55 +02:00
|
|
|
uint64_t val, unsigned size)
|
|
|
|
{
|
2015-04-08 09:09:49 +02:00
|
|
|
VGACommonState *s = ptr;
|
2012-11-12 22:33:21 +01:00
|
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|
|
2012-10-15 08:02:55 +02:00
|
|
|
switch (size) {
|
|
|
|
case 1:
|
2015-04-08 09:09:49 +02:00
|
|
|
vga_ioport_write(s, addr + 0x3c0, val);
|
2012-10-15 08:02:55 +02:00
|
|
|
break;
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|
|
case 2:
|
|
|
|
/*
|
|
|
|
* Update bytes in little endian order. Allows to update
|
|
|
|
* indexed registers with a single word write because the
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|
|
|
* index byte is updated first.
|
|
|
|
*/
|
2015-04-08 09:09:49 +02:00
|
|
|
vga_ioport_write(s, addr + 0x3c0, val & 0xff);
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|
|
vga_ioport_write(s, addr + 0x3c1, (val >> 8) & 0xff);
|
2012-10-15 08:02:55 +02:00
|
|
|
break;
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|
}
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|
|
}
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|
|
static const MemoryRegionOps pci_vga_ioport_ops = {
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.read = pci_vga_ioport_read,
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|
.write = pci_vga_ioport_write,
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|
|
.valid.min_access_size = 1,
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|
|
.valid.max_access_size = 4,
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|
|
.impl.min_access_size = 1,
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|
|
.impl.max_access_size = 2,
|
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|
|
.endianness = DEVICE_LITTLE_ENDIAN,
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|
|
};
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|
2012-10-23 12:30:10 +02:00
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static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,
|
2012-10-15 08:02:55 +02:00
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unsigned size)
|
|
|
|
{
|
2015-04-08 09:09:49 +02:00
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|
|
VGACommonState *s = ptr;
|
2012-10-15 08:02:55 +02:00
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int index = addr >> 1;
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|
2015-04-08 09:09:49 +02:00
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vbe_ioport_write_index(s, 0, index);
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|
return vbe_ioport_read_data(s, 0);
|
2012-10-15 08:02:55 +02:00
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|
|
}
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|
2012-10-23 12:30:10 +02:00
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static void pci_vga_bochs_write(void *ptr, hwaddr addr,
|
2012-10-15 08:02:55 +02:00
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uint64_t val, unsigned size)
|
|
|
|
{
|
2015-04-08 09:09:49 +02:00
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VGACommonState *s = ptr;
|
2012-10-15 08:02:55 +02:00
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int index = addr >> 1;
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|
2015-04-08 09:09:49 +02:00
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vbe_ioport_write_index(s, 0, index);
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vbe_ioport_write_data(s, 0, val);
|
2012-10-15 08:02:55 +02:00
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|
}
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static const MemoryRegionOps pci_vga_bochs_ops = {
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.read = pci_vga_bochs_read,
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.write = pci_vga_bochs_write,
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|
|
|
.valid.min_access_size = 1,
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|
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.valid.max_access_size = 4,
|
|
|
|
.impl.min_access_size = 2,
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|
|
.impl.max_access_size = 2,
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
|
|
};
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|
|
|
|
2014-09-23 12:45:56 +02:00
|
|
|
static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size)
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|
|
|
{
|
2015-04-08 09:09:49 +02:00
|
|
|
VGACommonState *s = ptr;
|
2014-09-23 12:45:56 +02:00
|
|
|
|
|
|
|
switch (addr) {
|
|
|
|
case PCI_VGA_QEXT_REG_SIZE:
|
|
|
|
return PCI_VGA_QEXT_SIZE;
|
|
|
|
case PCI_VGA_QEXT_REG_BYTEORDER:
|
2015-04-08 09:09:49 +02:00
|
|
|
return s->big_endian_fb ?
|
2014-09-23 12:45:56 +02:00
|
|
|
PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pci_vga_qext_write(void *ptr, hwaddr addr,
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|
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uint64_t val, unsigned size)
|
|
|
|
{
|
2015-04-08 09:09:49 +02:00
|
|
|
VGACommonState *s = ptr;
|
2014-09-23 12:45:56 +02:00
|
|
|
|
|
|
|
switch (addr) {
|
|
|
|
case PCI_VGA_QEXT_REG_BYTEORDER:
|
|
|
|
if (val == PCI_VGA_QEXT_BIG_ENDIAN) {
|
2015-04-08 09:09:49 +02:00
|
|
|
s->big_endian_fb = true;
|
2014-09-23 12:45:56 +02:00
|
|
|
}
|
|
|
|
if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) {
|
2015-04-08 09:09:49 +02:00
|
|
|
s->big_endian_fb = false;
|
2014-09-23 12:45:56 +02:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-02-10 05:36:15 +01:00
|
|
|
static bool vga_get_big_endian_fb(Object *obj, Error **errp)
|
|
|
|
{
|
2015-05-12 11:27:08 +02:00
|
|
|
PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
|
2015-02-10 05:36:15 +01:00
|
|
|
|
|
|
|
return d->vga.big_endian_fb;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void vga_set_big_endian_fb(Object *obj, bool value, Error **errp)
|
|
|
|
{
|
2015-05-12 11:27:08 +02:00
|
|
|
PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
|
2015-02-10 05:36:15 +01:00
|
|
|
|
|
|
|
d->vga.big_endian_fb = value;
|
|
|
|
}
|
|
|
|
|
2014-09-23 12:45:56 +02:00
|
|
|
static const MemoryRegionOps pci_vga_qext_ops = {
|
|
|
|
.read = pci_vga_qext_read,
|
|
|
|
.write = pci_vga_qext_write,
|
|
|
|
.valid.min_access_size = 4,
|
|
|
|
.valid.max_access_size = 4,
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
|
|
};
|
|
|
|
|
2014-09-10 14:25:45 +02:00
|
|
|
void pci_std_vga_mmio_region_init(VGACommonState *s,
|
2018-06-26 08:09:41 +02:00
|
|
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Object *owner,
|
2014-09-10 14:25:45 +02:00
|
|
|
MemoryRegion *parent,
|
|
|
|
MemoryRegion *subs,
|
2018-09-25 09:56:46 +02:00
|
|
|
bool qext, bool edid)
|
2015-04-08 09:50:46 +02:00
|
|
|
{
|
2018-09-25 09:56:46 +02:00
|
|
|
PCIVGAState *d = container_of(s, PCIVGAState, vga);
|
|
|
|
|
2018-06-26 08:09:41 +02:00
|
|
|
memory_region_init_io(&subs[0], owner, &pci_vga_ioport_ops, s,
|
2015-04-08 09:50:46 +02:00
|
|
|
"vga ioports remapped", PCI_VGA_IOPORT_SIZE);
|
|
|
|
memory_region_add_subregion(parent, PCI_VGA_IOPORT_OFFSET,
|
|
|
|
&subs[0]);
|
|
|
|
|
2018-06-26 08:09:41 +02:00
|
|
|
memory_region_init_io(&subs[1], owner, &pci_vga_bochs_ops, s,
|
2015-04-08 09:50:46 +02:00
|
|
|
"bochs dispi interface", PCI_VGA_BOCHS_SIZE);
|
|
|
|
memory_region_add_subregion(parent, PCI_VGA_BOCHS_OFFSET,
|
|
|
|
&subs[1]);
|
|
|
|
|
|
|
|
if (qext) {
|
2018-06-26 08:09:41 +02:00
|
|
|
memory_region_init_io(&subs[2], owner, &pci_vga_qext_ops, s,
|
2015-04-08 09:50:46 +02:00
|
|
|
"qemu extended regs", PCI_VGA_QEXT_SIZE);
|
|
|
|
memory_region_add_subregion(parent, PCI_VGA_QEXT_OFFSET,
|
|
|
|
&subs[2]);
|
|
|
|
}
|
2018-09-25 09:56:46 +02:00
|
|
|
|
|
|
|
if (edid) {
|
|
|
|
qemu_edid_generate(d->edid, sizeof(d->edid), &d->edid_info);
|
|
|
|
qemu_edid_region_io(&subs[3], owner, d->edid, sizeof(d->edid));
|
|
|
|
memory_region_add_subregion(parent, 0, &subs[3]);
|
|
|
|
}
|
2015-04-08 09:50:46 +02:00
|
|
|
}
|
|
|
|
|
2015-01-19 15:52:30 +01:00
|
|
|
static void pci_std_vga_realize(PCIDevice *dev, Error **errp)
|
2009-08-31 16:07:15 +02:00
|
|
|
{
|
2015-05-12 11:27:08 +02:00
|
|
|
PCIVGAState *d = PCI_VGA(dev);
|
2012-10-15 08:02:54 +02:00
|
|
|
VGACommonState *s = &d->vga;
|
2015-04-08 09:50:46 +02:00
|
|
|
bool qext = false;
|
2018-09-25 09:56:46 +02:00
|
|
|
bool edid = false;
|
2009-08-31 16:07:15 +02:00
|
|
|
|
2012-10-15 08:02:54 +02:00
|
|
|
/* vga + console init */
|
2018-07-02 18:33:44 +02:00
|
|
|
vga_common_init(s, OBJECT(dev));
|
2013-06-07 03:21:13 +02:00
|
|
|
vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev),
|
|
|
|
true);
|
2009-08-31 16:07:15 +02:00
|
|
|
|
2014-01-24 15:35:21 +01:00
|
|
|
s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
|
2009-08-31 16:07:15 +02:00
|
|
|
|
2012-10-15 08:02:54 +02:00
|
|
|
/* XXX: VGA_RAM_SIZE must be a power of two */
|
|
|
|
pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
|
2009-08-31 16:07:15 +02:00
|
|
|
|
2012-10-15 08:02:55 +02:00
|
|
|
/* mmio bar for vga register access */
|
|
|
|
if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
|
2020-03-09 11:00:09 +01:00
|
|
|
memory_region_init_io(&d->mmio, OBJECT(dev), &unassigned_io_ops, NULL,
|
|
|
|
"vga.mmio", PCI_VGA_MMIO_SIZE);
|
2014-09-23 12:45:56 +02:00
|
|
|
|
|
|
|
if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
|
2015-04-08 09:50:46 +02:00
|
|
|
qext = true;
|
2014-09-23 12:45:56 +02:00
|
|
|
pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
|
|
|
|
}
|
2018-09-25 09:56:46 +02:00
|
|
|
if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
|
|
|
|
edid = true;
|
|
|
|
}
|
|
|
|
pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs,
|
|
|
|
qext, edid);
|
2014-09-23 12:45:56 +02:00
|
|
|
|
2012-10-15 08:02:55 +02:00
|
|
|
pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
|
|
|
|
}
|
2009-08-31 16:07:15 +02:00
|
|
|
}
|
|
|
|
|
2015-02-10 05:36:15 +01:00
|
|
|
static void pci_std_vga_init(Object *obj)
|
|
|
|
{
|
|
|
|
/* Expose framebuffer byteorder via QOM */
|
|
|
|
object_property_add_bool(obj, "big-endian-framebuffer",
|
|
|
|
vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
|
|
|
|
}
|
|
|
|
|
2015-01-19 15:52:30 +01:00
|
|
|
static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp)
|
2012-11-12 14:29:47 +01:00
|
|
|
{
|
2015-05-12 11:27:08 +02:00
|
|
|
PCIVGAState *d = PCI_VGA(dev);
|
2012-11-12 14:29:47 +01:00
|
|
|
VGACommonState *s = &d->vga;
|
2015-04-08 09:50:46 +02:00
|
|
|
bool qext = false;
|
2018-09-25 09:56:46 +02:00
|
|
|
bool edid = false;
|
2012-11-12 14:29:47 +01:00
|
|
|
|
|
|
|
/* vga + console init */
|
2018-07-02 18:33:44 +02:00
|
|
|
vga_common_init(s, OBJECT(dev));
|
2012-11-12 14:29:47 +01:00
|
|
|
s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
|
|
|
|
|
|
|
|
/* mmio bar */
|
2020-03-09 11:00:09 +01:00
|
|
|
memory_region_init_io(&d->mmio, OBJECT(dev), &unassigned_io_ops, NULL,
|
|
|
|
"vga.mmio", PCI_VGA_MMIO_SIZE);
|
2012-11-12 14:29:47 +01:00
|
|
|
|
2014-09-23 12:45:56 +02:00
|
|
|
if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
|
2015-04-08 09:50:46 +02:00
|
|
|
qext = true;
|
2014-09-23 12:45:56 +02:00
|
|
|
pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
|
|
|
|
}
|
2018-09-25 09:56:46 +02:00
|
|
|
if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
|
|
|
|
edid = true;
|
|
|
|
}
|
|
|
|
pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, qext, edid);
|
2014-09-23 12:45:56 +02:00
|
|
|
|
2012-11-12 14:29:47 +01:00
|
|
|
pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
|
|
|
|
pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
|
2015-02-10 05:36:15 +01:00
|
|
|
}
|
2012-11-12 14:29:47 +01:00
|
|
|
|
2018-03-13 18:17:29 +01:00
|
|
|
static void pci_secondary_vga_exit(PCIDevice *dev)
|
|
|
|
{
|
|
|
|
PCIVGAState *d = PCI_VGA(dev);
|
|
|
|
VGACommonState *s = &d->vga;
|
|
|
|
|
|
|
|
graphic_console_close(s->con);
|
2018-10-02 14:19:35 +02:00
|
|
|
memory_region_del_subregion(&d->mmio, &d->mrs[0]);
|
|
|
|
memory_region_del_subregion(&d->mmio, &d->mrs[1]);
|
|
|
|
if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
|
|
|
|
memory_region_del_subregion(&d->mmio, &d->mrs[2]);
|
|
|
|
}
|
|
|
|
if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
|
|
|
|
memory_region_del_subregion(&d->mmio, &d->mrs[3]);
|
|
|
|
}
|
2018-03-13 18:17:29 +01:00
|
|
|
}
|
|
|
|
|
2015-02-10 05:36:15 +01:00
|
|
|
static void pci_secondary_vga_init(Object *obj)
|
|
|
|
{
|
|
|
|
/* Expose framebuffer byteorder via QOM */
|
|
|
|
object_property_add_bool(obj, "big-endian-framebuffer",
|
|
|
|
vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
|
2012-11-12 14:29:47 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void pci_secondary_vga_reset(DeviceState *dev)
|
|
|
|
{
|
2015-05-12 11:27:08 +02:00
|
|
|
PCIVGAState *d = PCI_VGA(PCI_DEVICE(dev));
|
2012-11-12 14:29:47 +01:00
|
|
|
vga_common_reset(&d->vga);
|
|
|
|
}
|
|
|
|
|
2012-05-24 09:59:44 +02:00
|
|
|
static Property vga_pci_properties[] = {
|
2012-06-11 10:42:53 +02:00
|
|
|
DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
|
2012-10-15 08:02:55 +02:00
|
|
|
DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
|
2014-09-23 12:45:56 +02:00
|
|
|
DEFINE_PROP_BIT("qemu-extended-regs",
|
|
|
|
PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
|
2018-09-25 09:56:46 +02:00
|
|
|
DEFINE_PROP_BIT("edid",
|
2019-06-07 10:34:44 +02:00
|
|
|
PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, true),
|
2018-09-25 09:56:46 +02:00
|
|
|
DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info),
|
2018-07-02 18:33:44 +02:00
|
|
|
DEFINE_PROP_BOOL("global-vmstate", PCIVGAState, vga.global_vmstate, false),
|
2012-05-24 09:59:44 +02:00
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
2012-11-12 14:29:47 +01:00
|
|
|
static Property secondary_pci_properties[] = {
|
|
|
|
DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
|
2014-09-23 12:45:56 +02:00
|
|
|
DEFINE_PROP_BIT("qemu-extended-regs",
|
|
|
|
PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
|
2018-09-25 09:56:46 +02:00
|
|
|
DEFINE_PROP_BIT("edid",
|
2019-06-07 10:34:44 +02:00
|
|
|
PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, true),
|
2018-09-25 09:56:46 +02:00
|
|
|
DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info),
|
2012-11-12 14:29:47 +01:00
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
2015-05-12 11:27:08 +02:00
|
|
|
static void vga_pci_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
k->vendor_id = PCI_VENDOR_ID_QEMU;
|
|
|
|
k->device_id = PCI_DEVICE_ID_QEMU_VGA;
|
|
|
|
dc->vmsd = &vmstate_vga_pci;
|
|
|
|
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo vga_pci_type_info = {
|
|
|
|
.name = TYPE_PCI_VGA,
|
|
|
|
.parent = TYPE_PCI_DEVICE,
|
|
|
|
.instance_size = sizeof(PCIVGAState),
|
|
|
|
.abstract = true,
|
|
|
|
.class_init = vga_pci_class_init,
|
2017-09-27 21:56:34 +02:00
|
|
|
.interfaces = (InterfaceInfo[]) {
|
|
|
|
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
|
|
|
|
{ },
|
|
|
|
},
|
2015-05-12 11:27:08 +02:00
|
|
|
};
|
|
|
|
|
2011-12-04 19:22:06 +01:00
|
|
|
static void vga_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2011-12-04 19:22:06 +01:00
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
|
2015-01-19 15:52:30 +01:00
|
|
|
k->realize = pci_std_vga_realize;
|
2011-12-04 19:22:06 +01:00
|
|
|
k->romfile = "vgabios-stdvga.bin";
|
|
|
|
k->class_id = PCI_CLASS_DISPLAY_VGA;
|
2020-01-10 16:30:32 +01:00
|
|
|
device_class_set_props(dc, vga_pci_properties);
|
2014-02-05 16:36:48 +01:00
|
|
|
dc->hotpluggable = false;
|
2011-12-04 19:22:06 +01:00
|
|
|
}
|
2011-05-25 03:58:31 +02:00
|
|
|
|
2012-11-12 14:29:47 +01:00
|
|
|
static void secondary_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
|
2015-01-19 15:52:30 +01:00
|
|
|
k->realize = pci_secondary_vga_realize;
|
2018-03-13 18:17:29 +01:00
|
|
|
k->exit = pci_secondary_vga_exit;
|
2012-11-12 14:29:47 +01:00
|
|
|
k->class_id = PCI_CLASS_DISPLAY_OTHER;
|
2020-01-10 16:30:32 +01:00
|
|
|
device_class_set_props(dc, secondary_pci_properties);
|
2012-11-12 14:29:47 +01:00
|
|
|
dc->reset = pci_secondary_vga_reset;
|
|
|
|
}
|
|
|
|
|
2013-01-10 16:19:07 +01:00
|
|
|
static const TypeInfo vga_info = {
|
2011-12-08 04:34:16 +01:00
|
|
|
.name = "VGA",
|
2015-05-12 11:27:08 +02:00
|
|
|
.parent = TYPE_PCI_VGA,
|
2015-02-10 05:36:15 +01:00
|
|
|
.instance_init = pci_std_vga_init,
|
2011-12-08 04:34:16 +01:00
|
|
|
.class_init = vga_class_init,
|
2009-08-31 16:07:15 +02:00
|
|
|
};
|
|
|
|
|
2012-11-12 14:29:47 +01:00
|
|
|
static const TypeInfo secondary_info = {
|
|
|
|
.name = "secondary-vga",
|
2015-05-12 11:27:08 +02:00
|
|
|
.parent = TYPE_PCI_VGA,
|
2015-02-10 05:36:15 +01:00
|
|
|
.instance_init = pci_secondary_vga_init,
|
2012-11-12 14:29:47 +01:00
|
|
|
.class_init = secondary_class_init,
|
|
|
|
};
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
static void vga_register_types(void)
|
2009-08-31 16:07:15 +02:00
|
|
|
{
|
2015-05-12 11:27:08 +02:00
|
|
|
type_register_static(&vga_pci_type_info);
|
2011-12-08 04:34:16 +01:00
|
|
|
type_register_static(&vga_info);
|
2012-11-12 14:29:47 +01:00
|
|
|
type_register_static(&secondary_info);
|
2009-08-31 16:07:15 +02:00
|
|
|
}
|
2012-02-09 15:20:55 +01:00
|
|
|
|
|
|
|
type_init(vga_register_types)
|