2007-04-30 03:48:07 +02:00
|
|
|
/*
|
|
|
|
* Intel XScale PXA255/270 MultiMediaCard/SD/SDIO Controller emulation.
|
|
|
|
*
|
|
|
|
* Copyright (c) 2006 Openedhand Ltd.
|
|
|
|
* Written by Andrzej Zaborowski <balrog@zabor.org>
|
|
|
|
*
|
|
|
|
* This code is licensed under the GPLv2.
|
2012-01-13 17:44:23 +01:00
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|
|
*
|
|
|
|
* Contributions after 2012-01-13 are licensed under the terms of the
|
|
|
|
* GNU GPL, version 2 or (at your option) any later version.
|
2007-04-30 03:48:07 +02:00
|
|
|
*/
|
|
|
|
|
2016-01-26 19:17:05 +01:00
|
|
|
#include "qemu/osdep.h"
|
include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 09:01:28 +01:00
|
|
|
#include "qapi/error.h"
|
2019-08-12 07:23:42 +02:00
|
|
|
#include "hw/irq.h"
|
2016-02-18 15:16:19 +01:00
|
|
|
#include "hw/sysbus.h"
|
2019-08-12 07:23:45 +02:00
|
|
|
#include "migration/vmstate.h"
|
2013-02-05 17:06:20 +01:00
|
|
|
#include "hw/arm/pxa.h"
|
2015-10-08 15:21:01 +02:00
|
|
|
#include "hw/sd/sd.h"
|
2016-02-18 15:16:19 +01:00
|
|
|
#include "hw/qdev-properties.h"
|
2018-01-11 14:25:39 +01:00
|
|
|
#include "qemu/log.h"
|
2019-05-23 16:35:07 +02:00
|
|
|
#include "qemu/module.h"
|
2018-01-11 14:25:39 +01:00
|
|
|
#include "trace.h"
|
2016-02-18 15:16:19 +01:00
|
|
|
|
|
|
|
#define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
|
|
|
|
#define PXA2XX_MMCI(obj) OBJECT_CHECK(PXA2xxMMCIState, (obj), TYPE_PXA2XX_MMCI)
|
2007-04-30 03:48:07 +02:00
|
|
|
|
2016-02-18 15:16:19 +01:00
|
|
|
#define TYPE_PXA2XX_MMCI_BUS "pxa2xx-mmci-bus"
|
|
|
|
#define PXA2XX_MMCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_PXA2XX_MMCI_BUS)
|
|
|
|
|
2009-05-10 02:44:56 +02:00
|
|
|
struct PXA2xxMMCIState {
|
2016-02-18 15:16:19 +01:00
|
|
|
SysBusDevice parent_obj;
|
|
|
|
|
2011-10-30 14:50:18 +01:00
|
|
|
MemoryRegion iomem;
|
2007-04-30 03:48:07 +02:00
|
|
|
qemu_irq irq;
|
2011-03-03 15:04:51 +01:00
|
|
|
qemu_irq rx_dma;
|
|
|
|
qemu_irq tx_dma;
|
2016-02-18 15:16:19 +01:00
|
|
|
qemu_irq inserted;
|
|
|
|
qemu_irq readonly;
|
2007-04-30 03:48:07 +02:00
|
|
|
|
2016-02-18 15:16:19 +01:00
|
|
|
BlockBackend *blk;
|
2016-02-18 15:16:19 +01:00
|
|
|
SDBus sdbus;
|
2007-04-30 03:48:07 +02:00
|
|
|
|
|
|
|
uint32_t status;
|
|
|
|
uint32_t clkrt;
|
|
|
|
uint32_t spi;
|
|
|
|
uint32_t cmdat;
|
|
|
|
uint32_t resp_tout;
|
|
|
|
uint32_t read_tout;
|
2016-02-18 15:16:19 +01:00
|
|
|
int32_t blklen;
|
|
|
|
int32_t numblk;
|
2007-04-30 03:48:07 +02:00
|
|
|
uint32_t intmask;
|
|
|
|
uint32_t intreq;
|
2016-02-18 15:16:19 +01:00
|
|
|
int32_t cmd;
|
2007-04-30 03:48:07 +02:00
|
|
|
uint32_t arg;
|
|
|
|
|
2016-02-18 15:16:19 +01:00
|
|
|
int32_t active;
|
|
|
|
int32_t bytesleft;
|
2007-04-30 03:48:07 +02:00
|
|
|
uint8_t tx_fifo[64];
|
2016-02-18 15:16:19 +01:00
|
|
|
uint32_t tx_start;
|
|
|
|
uint32_t tx_len;
|
2007-04-30 03:48:07 +02:00
|
|
|
uint8_t rx_fifo[32];
|
2016-02-18 15:16:19 +01:00
|
|
|
uint32_t rx_start;
|
|
|
|
uint32_t rx_len;
|
2007-04-30 03:48:07 +02:00
|
|
|
uint16_t resp_fifo[9];
|
2016-02-18 15:16:19 +01:00
|
|
|
uint32_t resp_len;
|
2007-04-30 03:48:07 +02:00
|
|
|
|
2016-02-18 15:16:19 +01:00
|
|
|
int32_t cmdreq;
|
|
|
|
};
|
|
|
|
|
|
|
|
static bool pxa2xx_mmci_vmstate_validate(void *opaque, int version_id)
|
|
|
|
{
|
|
|
|
PXA2xxMMCIState *s = opaque;
|
|
|
|
|
|
|
|
return s->tx_start < ARRAY_SIZE(s->tx_fifo)
|
|
|
|
&& s->rx_start < ARRAY_SIZE(s->rx_fifo)
|
|
|
|
&& s->tx_len <= ARRAY_SIZE(s->tx_fifo)
|
|
|
|
&& s->rx_len <= ARRAY_SIZE(s->rx_fifo)
|
|
|
|
&& s->resp_len <= ARRAY_SIZE(s->resp_fifo);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static const VMStateDescription vmstate_pxa2xx_mmci = {
|
|
|
|
.name = "pxa2xx-mmci",
|
|
|
|
.version_id = 2,
|
|
|
|
.minimum_version_id = 2,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_UINT32(status, PXA2xxMMCIState),
|
|
|
|
VMSTATE_UINT32(clkrt, PXA2xxMMCIState),
|
|
|
|
VMSTATE_UINT32(spi, PXA2xxMMCIState),
|
|
|
|
VMSTATE_UINT32(cmdat, PXA2xxMMCIState),
|
|
|
|
VMSTATE_UINT32(resp_tout, PXA2xxMMCIState),
|
|
|
|
VMSTATE_UINT32(read_tout, PXA2xxMMCIState),
|
|
|
|
VMSTATE_INT32(blklen, PXA2xxMMCIState),
|
|
|
|
VMSTATE_INT32(numblk, PXA2xxMMCIState),
|
|
|
|
VMSTATE_UINT32(intmask, PXA2xxMMCIState),
|
|
|
|
VMSTATE_UINT32(intreq, PXA2xxMMCIState),
|
|
|
|
VMSTATE_INT32(cmd, PXA2xxMMCIState),
|
|
|
|
VMSTATE_UINT32(arg, PXA2xxMMCIState),
|
|
|
|
VMSTATE_INT32(cmdreq, PXA2xxMMCIState),
|
|
|
|
VMSTATE_INT32(active, PXA2xxMMCIState),
|
|
|
|
VMSTATE_INT32(bytesleft, PXA2xxMMCIState),
|
|
|
|
VMSTATE_UINT32(tx_start, PXA2xxMMCIState),
|
|
|
|
VMSTATE_UINT32(tx_len, PXA2xxMMCIState),
|
|
|
|
VMSTATE_UINT32(rx_start, PXA2xxMMCIState),
|
|
|
|
VMSTATE_UINT32(rx_len, PXA2xxMMCIState),
|
|
|
|
VMSTATE_UINT32(resp_len, PXA2xxMMCIState),
|
|
|
|
VMSTATE_VALIDATE("fifo size incorrect", pxa2xx_mmci_vmstate_validate),
|
|
|
|
VMSTATE_UINT8_ARRAY(tx_fifo, PXA2xxMMCIState, 64),
|
|
|
|
VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxMMCIState, 32),
|
|
|
|
VMSTATE_UINT16_ARRAY(resp_fifo, PXA2xxMMCIState, 9),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
2007-04-30 03:48:07 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
#define MMC_STRPCL 0x00 /* MMC Clock Start/Stop register */
|
|
|
|
#define MMC_STAT 0x04 /* MMC Status register */
|
|
|
|
#define MMC_CLKRT 0x08 /* MMC Clock Rate register */
|
|
|
|
#define MMC_SPI 0x0c /* MMC SPI Mode register */
|
|
|
|
#define MMC_CMDAT 0x10 /* MMC Command/Data register */
|
|
|
|
#define MMC_RESTO 0x14 /* MMC Response Time-Out register */
|
|
|
|
#define MMC_RDTO 0x18 /* MMC Read Time-Out register */
|
|
|
|
#define MMC_BLKLEN 0x1c /* MMC Block Length register */
|
|
|
|
#define MMC_NUMBLK 0x20 /* MMC Number of Blocks register */
|
|
|
|
#define MMC_PRTBUF 0x24 /* MMC Buffer Partly Full register */
|
|
|
|
#define MMC_I_MASK 0x28 /* MMC Interrupt Mask register */
|
|
|
|
#define MMC_I_REG 0x2c /* MMC Interrupt Request register */
|
|
|
|
#define MMC_CMD 0x30 /* MMC Command register */
|
|
|
|
#define MMC_ARGH 0x34 /* MMC Argument High register */
|
|
|
|
#define MMC_ARGL 0x38 /* MMC Argument Low register */
|
|
|
|
#define MMC_RES 0x3c /* MMC Response FIFO */
|
|
|
|
#define MMC_RXFIFO 0x40 /* MMC Receive FIFO */
|
|
|
|
#define MMC_TXFIFO 0x44 /* MMC Transmit FIFO */
|
|
|
|
#define MMC_RDWAIT 0x48 /* MMC RD_WAIT register */
|
|
|
|
#define MMC_BLKS_REM 0x4c /* MMC Blocks Remaining register */
|
|
|
|
|
|
|
|
/* Bitfield masks */
|
|
|
|
#define STRPCL_STOP_CLK (1 << 0)
|
|
|
|
#define STRPCL_STRT_CLK (1 << 1)
|
|
|
|
#define STAT_TOUT_RES (1 << 1)
|
|
|
|
#define STAT_CLK_EN (1 << 8)
|
|
|
|
#define STAT_DATA_DONE (1 << 11)
|
|
|
|
#define STAT_PRG_DONE (1 << 12)
|
|
|
|
#define STAT_END_CMDRES (1 << 13)
|
|
|
|
#define SPI_SPI_MODE (1 << 0)
|
|
|
|
#define CMDAT_RES_TYPE (3 << 0)
|
|
|
|
#define CMDAT_DATA_EN (1 << 2)
|
|
|
|
#define CMDAT_WR_RD (1 << 3)
|
|
|
|
#define CMDAT_DMA_EN (1 << 7)
|
|
|
|
#define CMDAT_STOP_TRAN (1 << 10)
|
|
|
|
#define INT_DATA_DONE (1 << 0)
|
|
|
|
#define INT_PRG_DONE (1 << 1)
|
|
|
|
#define INT_END_CMD (1 << 2)
|
|
|
|
#define INT_STOP_CMD (1 << 3)
|
|
|
|
#define INT_CLK_OFF (1 << 4)
|
|
|
|
#define INT_RXFIFO_REQ (1 << 5)
|
|
|
|
#define INT_TXFIFO_REQ (1 << 6)
|
|
|
|
#define INT_TINT (1 << 7)
|
|
|
|
#define INT_DAT_ERR (1 << 8)
|
|
|
|
#define INT_RES_ERR (1 << 9)
|
|
|
|
#define INT_RD_STALLED (1 << 10)
|
|
|
|
#define INT_SDIO_INT (1 << 11)
|
|
|
|
#define INT_SDIO_SACK (1 << 12)
|
|
|
|
#define PRTBUF_PRT_BUF (1 << 0)
|
|
|
|
|
|
|
|
/* Route internal interrupt lines to the global IC and DMA */
|
2009-05-10 02:44:56 +02:00
|
|
|
static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s)
|
2007-04-30 03:48:07 +02:00
|
|
|
{
|
|
|
|
uint32_t mask = s->intmask;
|
|
|
|
if (s->cmdat & CMDAT_DMA_EN) {
|
|
|
|
mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ;
|
|
|
|
|
2011-03-03 15:04:51 +01:00
|
|
|
qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ));
|
|
|
|
qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ));
|
2007-04-30 03:48:07 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
qemu_set_irq(s->irq, !!(s->intreq & ~mask));
|
|
|
|
}
|
|
|
|
|
2009-05-10 02:44:56 +02:00
|
|
|
static void pxa2xx_mmci_fifo_update(PXA2xxMMCIState *s)
|
2007-04-30 03:48:07 +02:00
|
|
|
{
|
|
|
|
if (!s->active)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (s->cmdat & CMDAT_WR_RD) {
|
|
|
|
while (s->bytesleft && s->tx_len) {
|
2016-02-18 15:16:19 +01:00
|
|
|
sdbus_write_data(&s->sdbus, s->tx_fifo[s->tx_start++]);
|
2007-04-30 03:48:07 +02:00
|
|
|
s->tx_start &= 0x1f;
|
|
|
|
s->tx_len --;
|
|
|
|
s->bytesleft --;
|
|
|
|
}
|
|
|
|
if (s->bytesleft)
|
|
|
|
s->intreq |= INT_TXFIFO_REQ;
|
|
|
|
} else
|
|
|
|
while (s->bytesleft && s->rx_len < 32) {
|
|
|
|
s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
|
2016-02-18 15:16:19 +01:00
|
|
|
sdbus_read_data(&s->sdbus);
|
2007-04-30 03:48:07 +02:00
|
|
|
s->bytesleft --;
|
|
|
|
s->intreq |= INT_RXFIFO_REQ;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!s->bytesleft) {
|
|
|
|
s->active = 0;
|
|
|
|
s->intreq |= INT_DATA_DONE;
|
|
|
|
s->status |= STAT_DATA_DONE;
|
|
|
|
|
|
|
|
if (s->cmdat & CMDAT_WR_RD) {
|
|
|
|
s->intreq |= INT_PRG_DONE;
|
|
|
|
s->status |= STAT_PRG_DONE;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
pxa2xx_mmci_int_update(s);
|
|
|
|
}
|
|
|
|
|
2009-05-10 02:44:56 +02:00
|
|
|
static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
|
2007-04-30 03:48:07 +02:00
|
|
|
{
|
|
|
|
int rsplen, i;
|
2009-05-10 02:44:56 +02:00
|
|
|
SDRequest request;
|
2007-04-30 03:48:07 +02:00
|
|
|
uint8_t response[16];
|
|
|
|
|
|
|
|
s->active = 1;
|
|
|
|
s->rx_len = 0;
|
|
|
|
s->tx_len = 0;
|
|
|
|
s->cmdreq = 0;
|
|
|
|
|
|
|
|
request.cmd = s->cmd;
|
|
|
|
request.arg = s->arg;
|
|
|
|
request.crc = 0; /* FIXME */
|
|
|
|
|
2016-02-18 15:16:19 +01:00
|
|
|
rsplen = sdbus_do_command(&s->sdbus, &request, response);
|
2007-04-30 03:48:07 +02:00
|
|
|
s->intreq |= INT_END_CMD;
|
|
|
|
|
|
|
|
memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
|
|
|
|
switch (s->cmdat & CMDAT_RES_TYPE) {
|
|
|
|
#define PXAMMCI_RESP(wd, value0, value1) \
|
|
|
|
s->resp_fifo[(wd) + 0] |= (value0); \
|
|
|
|
s->resp_fifo[(wd) + 1] |= (value1) << 8;
|
|
|
|
case 0: /* No response */
|
|
|
|
goto complete;
|
|
|
|
|
|
|
|
case 1: /* R1, R4, R5 or R6 */
|
|
|
|
if (rsplen < 4)
|
|
|
|
goto timeout;
|
|
|
|
goto complete;
|
|
|
|
|
|
|
|
case 2: /* R2 */
|
|
|
|
if (rsplen < 16)
|
|
|
|
goto timeout;
|
|
|
|
goto complete;
|
|
|
|
|
|
|
|
case 3: /* R3 */
|
|
|
|
if (rsplen < 4)
|
|
|
|
goto timeout;
|
|
|
|
goto complete;
|
|
|
|
|
|
|
|
complete:
|
|
|
|
for (i = 0; rsplen > 0; i ++, rsplen -= 2) {
|
|
|
|
PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]);
|
|
|
|
}
|
|
|
|
s->status |= STAT_END_CMDRES;
|
|
|
|
|
|
|
|
if (!(s->cmdat & CMDAT_DATA_EN))
|
|
|
|
s->active = 0;
|
|
|
|
else
|
|
|
|
s->bytesleft = s->numblk * s->blklen;
|
|
|
|
|
|
|
|
s->resp_len = 0;
|
|
|
|
break;
|
|
|
|
|
|
|
|
timeout:
|
|
|
|
s->active = 0;
|
|
|
|
s->status |= STAT_TOUT_RES;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
pxa2xx_mmci_fifo_update(s);
|
|
|
|
}
|
|
|
|
|
2015-06-15 19:06:09 +02:00
|
|
|
static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size)
|
2007-04-30 03:48:07 +02:00
|
|
|
{
|
2009-05-10 02:44:56 +02:00
|
|
|
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
|
2018-01-11 14:25:39 +01:00
|
|
|
uint32_t ret = 0;
|
2007-04-30 03:48:07 +02:00
|
|
|
|
|
|
|
switch (offset) {
|
|
|
|
case MMC_STRPCL:
|
2018-01-11 14:25:39 +01:00
|
|
|
break;
|
2007-04-30 03:48:07 +02:00
|
|
|
case MMC_STAT:
|
2018-01-11 14:25:39 +01:00
|
|
|
ret = s->status;
|
|
|
|
break;
|
2007-04-30 03:48:07 +02:00
|
|
|
case MMC_CLKRT:
|
2018-01-11 14:25:39 +01:00
|
|
|
ret = s->clkrt;
|
|
|
|
break;
|
2007-04-30 03:48:07 +02:00
|
|
|
case MMC_SPI:
|
2018-01-11 14:25:39 +01:00
|
|
|
ret = s->spi;
|
|
|
|
break;
|
2007-04-30 03:48:07 +02:00
|
|
|
case MMC_CMDAT:
|
2018-01-11 14:25:39 +01:00
|
|
|
ret = s->cmdat;
|
|
|
|
break;
|
2007-04-30 03:48:07 +02:00
|
|
|
case MMC_RESTO:
|
2018-01-11 14:25:39 +01:00
|
|
|
ret = s->resp_tout;
|
|
|
|
break;
|
2007-04-30 03:48:07 +02:00
|
|
|
case MMC_RDTO:
|
2018-01-11 14:25:39 +01:00
|
|
|
ret = s->read_tout;
|
|
|
|
break;
|
2007-04-30 03:48:07 +02:00
|
|
|
case MMC_BLKLEN:
|
2018-01-11 14:25:39 +01:00
|
|
|
ret = s->blklen;
|
|
|
|
break;
|
2007-04-30 03:48:07 +02:00
|
|
|
case MMC_NUMBLK:
|
2018-01-11 14:25:39 +01:00
|
|
|
ret = s->numblk;
|
|
|
|
break;
|
2007-04-30 03:48:07 +02:00
|
|
|
case MMC_PRTBUF:
|
2018-01-11 14:25:39 +01:00
|
|
|
break;
|
2007-04-30 03:48:07 +02:00
|
|
|
case MMC_I_MASK:
|
2018-01-11 14:25:39 +01:00
|
|
|
ret = s->intmask;
|
|
|
|
break;
|
2007-04-30 03:48:07 +02:00
|
|
|
case MMC_I_REG:
|
2018-01-11 14:25:39 +01:00
|
|
|
ret = s->intreq;
|
|
|
|
break;
|
2007-04-30 03:48:07 +02:00
|
|
|
case MMC_CMD:
|
2018-01-11 14:25:39 +01:00
|
|
|
ret = s->cmd | 0x40;
|
|
|
|
break;
|
2007-04-30 03:48:07 +02:00
|
|
|
case MMC_ARGH:
|
2018-01-11 14:25:39 +01:00
|
|
|
ret = s->arg >> 16;
|
|
|
|
break;
|
2007-04-30 03:48:07 +02:00
|
|
|
case MMC_ARGL:
|
2018-01-11 14:25:39 +01:00
|
|
|
ret = s->arg & 0xffff;
|
|
|
|
break;
|
2007-04-30 03:48:07 +02:00
|
|
|
case MMC_RES:
|
2018-01-11 14:25:39 +01:00
|
|
|
ret = (s->resp_len < 9) ? s->resp_fifo[s->resp_len++] : 0;
|
|
|
|
break;
|
2007-04-30 03:48:07 +02:00
|
|
|
case MMC_RXFIFO:
|
2015-06-15 19:06:09 +02:00
|
|
|
while (size-- && s->rx_len) {
|
|
|
|
ret |= s->rx_fifo[s->rx_start++] << (size << 3);
|
2007-04-30 03:48:07 +02:00
|
|
|
s->rx_start &= 0x1f;
|
|
|
|
s->rx_len --;
|
|
|
|
}
|
|
|
|
s->intreq &= ~INT_RXFIFO_REQ;
|
|
|
|
pxa2xx_mmci_fifo_update(s);
|
2018-01-11 14:25:39 +01:00
|
|
|
break;
|
2007-04-30 03:48:07 +02:00
|
|
|
case MMC_RDWAIT:
|
2018-01-11 14:25:39 +01:00
|
|
|
break;
|
2007-04-30 03:48:07 +02:00
|
|
|
case MMC_BLKS_REM:
|
2018-01-11 14:25:39 +01:00
|
|
|
ret = s->numblk;
|
|
|
|
break;
|
2007-04-30 03:48:07 +02:00
|
|
|
default:
|
2018-01-11 14:25:39 +01:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: incorrect register 0x%02" HWADDR_PRIx "\n",
|
|
|
|
__func__, offset);
|
2007-04-30 03:48:07 +02:00
|
|
|
}
|
2018-01-11 14:25:39 +01:00
|
|
|
trace_pxa2xx_mmci_read(size, offset, ret);
|
2007-04-30 03:48:07 +02:00
|
|
|
|
2018-01-11 14:25:39 +01:00
|
|
|
return ret;
|
2007-04-30 03:48:07 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void pxa2xx_mmci_write(void *opaque,
|
2015-06-15 19:06:09 +02:00
|
|
|
hwaddr offset, uint64_t value, unsigned size)
|
2007-04-30 03:48:07 +02:00
|
|
|
{
|
2009-05-10 02:44:56 +02:00
|
|
|
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
|
2007-04-30 03:48:07 +02:00
|
|
|
|
2018-01-11 14:25:39 +01:00
|
|
|
trace_pxa2xx_mmci_write(size, offset, value);
|
2007-04-30 03:48:07 +02:00
|
|
|
switch (offset) {
|
|
|
|
case MMC_STRPCL:
|
|
|
|
if (value & STRPCL_STRT_CLK) {
|
|
|
|
s->status |= STAT_CLK_EN;
|
|
|
|
s->intreq &= ~INT_CLK_OFF;
|
|
|
|
|
|
|
|
if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) {
|
|
|
|
s->status &= STAT_CLK_EN;
|
|
|
|
pxa2xx_mmci_wakequeues(s);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (value & STRPCL_STOP_CLK) {
|
|
|
|
s->status &= ~STAT_CLK_EN;
|
|
|
|
s->intreq |= INT_CLK_OFF;
|
|
|
|
s->active = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
pxa2xx_mmci_int_update(s);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case MMC_CLKRT:
|
|
|
|
s->clkrt = value & 7;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case MMC_SPI:
|
|
|
|
s->spi = value & 0xf;
|
2018-01-11 14:25:39 +01:00
|
|
|
if (value & SPI_SPI_MODE) {
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: attempted to use card in SPI mode\n", __func__);
|
|
|
|
}
|
2007-04-30 03:48:07 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
case MMC_CMDAT:
|
|
|
|
s->cmdat = value & 0x3dff;
|
|
|
|
s->active = 0;
|
|
|
|
s->cmdreq = 1;
|
|
|
|
if (!(value & CMDAT_STOP_TRAN)) {
|
|
|
|
s->status &= STAT_CLK_EN;
|
|
|
|
|
|
|
|
if (s->status & STAT_CLK_EN)
|
|
|
|
pxa2xx_mmci_wakequeues(s);
|
|
|
|
}
|
|
|
|
|
|
|
|
pxa2xx_mmci_int_update(s);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case MMC_RESTO:
|
|
|
|
s->resp_tout = value & 0x7f;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case MMC_RDTO:
|
|
|
|
s->read_tout = value & 0xffff;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case MMC_BLKLEN:
|
|
|
|
s->blklen = value & 0xfff;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case MMC_NUMBLK:
|
|
|
|
s->numblk = value & 0xffff;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case MMC_PRTBUF:
|
|
|
|
if (value & PRTBUF_PRT_BUF) {
|
|
|
|
s->tx_start ^= 32;
|
|
|
|
s->tx_len = 0;
|
|
|
|
}
|
|
|
|
pxa2xx_mmci_fifo_update(s);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case MMC_I_MASK:
|
|
|
|
s->intmask = value & 0x1fff;
|
|
|
|
pxa2xx_mmci_int_update(s);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case MMC_CMD:
|
|
|
|
s->cmd = value & 0x3f;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case MMC_ARGH:
|
|
|
|
s->arg &= 0x0000ffff;
|
|
|
|
s->arg |= value << 16;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case MMC_ARGL:
|
|
|
|
s->arg &= 0xffff0000;
|
|
|
|
s->arg |= value & 0x0000ffff;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case MMC_TXFIFO:
|
2015-06-15 19:06:09 +02:00
|
|
|
while (size-- && s->tx_len < 0x20)
|
2007-04-30 03:48:07 +02:00
|
|
|
s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
|
2015-06-15 19:06:09 +02:00
|
|
|
(value >> (size << 3)) & 0xff;
|
2007-04-30 03:48:07 +02:00
|
|
|
s->intreq &= ~INT_TXFIFO_REQ;
|
|
|
|
pxa2xx_mmci_fifo_update(s);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case MMC_RDWAIT:
|
|
|
|
case MMC_BLKS_REM:
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2018-01-11 14:25:39 +01:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: incorrect reg 0x%02" HWADDR_PRIx " "
|
|
|
|
"(value 0x%08" PRIx64 ")\n", __func__, offset, value);
|
2007-04-30 03:48:07 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-10-30 14:50:18 +01:00
|
|
|
static const MemoryRegionOps pxa2xx_mmci_ops = {
|
2015-06-15 19:06:09 +02:00
|
|
|
.read = pxa2xx_mmci_read,
|
|
|
|
.write = pxa2xx_mmci_write,
|
2011-10-30 14:50:18 +01:00
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2007-04-30 03:48:07 +02:00
|
|
|
};
|
|
|
|
|
2011-10-30 14:50:18 +01:00
|
|
|
PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
|
2012-10-23 12:30:10 +02:00
|
|
|
hwaddr base,
|
2020-07-05 23:22:10 +02:00
|
|
|
qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
|
2007-04-30 03:48:07 +02:00
|
|
|
{
|
2020-07-05 23:22:10 +02:00
|
|
|
DeviceState *dev;
|
2016-02-18 15:16:19 +01:00
|
|
|
SysBusDevice *sbd;
|
2007-04-30 03:48:07 +02:00
|
|
|
|
qdev: Convert uses of qdev_create() with Coccinelle
This is the transformation explained in the commit before previous.
Takes care of just one pattern that needs conversion. More to come in
this series.
Coccinelle script:
@ depends on !(file in "hw/arm/highbank.c")@
expression bus, type_name, dev, expr;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr;
identifier DOWN;
@@
- dev = DOWN(qdev_create(bus, type_name));
+ dev = DOWN(qdev_new(type_name));
... when != dev = expr
- qdev_init_nofail(DEVICE(dev));
+ qdev_realize_and_unref(DEVICE(dev), bus, &error_fatal);
@@
expression bus, type_name, expr;
identifier dev;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr, errp;
symbol true;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
@@
expression bus, type_name, expr, errp;
identifier dev;
symbol true;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
The first rule exempts hw/arm/highbank.c, because it matches along two
control flow paths there, with different @type_name. Covered by the
next commit's manual conversions.
Missing #include "qapi/error.h" added manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-10-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 07:31:58 +02:00
|
|
|
dev = qdev_new(TYPE_PXA2XX_MMCI);
|
2016-02-18 15:16:19 +01:00
|
|
|
sbd = SYS_BUS_DEVICE(dev);
|
|
|
|
sysbus_mmio_map(sbd, 0, base);
|
|
|
|
sysbus_connect_irq(sbd, 0, irq);
|
|
|
|
qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma);
|
|
|
|
qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma);
|
sysbus: Convert to sysbus_realize() etc. with Coccinelle
Convert from qdev_realize(), qdev_realize_and_unref() with null @bus
argument to sysbus_realize(), sysbus_realize_and_unref().
Coccinelle script:
@@
expression dev, errp;
@@
- qdev_realize(DEVICE(dev), NULL, errp);
+ sysbus_realize(SYS_BUS_DEVICE(dev), errp);
@@
expression sysbus_dev, dev, errp;
@@
+ sysbus_dev = SYS_BUS_DEVICE(dev);
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
- sysbus_dev = SYS_BUS_DEVICE(dev);
@@
expression sysbus_dev, dev, errp;
expression expr;
@@
sysbus_dev = SYS_BUS_DEVICE(dev);
... when != dev = expr;
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(DEVICE(dev), NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
Whitespace changes minimized manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-46-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 07:32:34 +02:00
|
|
|
sysbus_realize_and_unref(sbd, &error_fatal);
|
2016-02-18 15:16:19 +01:00
|
|
|
|
2020-07-05 23:22:57 +02:00
|
|
|
return PXA2XX_MMCI(dev);
|
2007-04-30 03:48:07 +02:00
|
|
|
}
|
|
|
|
|
2016-02-18 15:16:19 +01:00
|
|
|
static void pxa2xx_mmci_set_inserted(DeviceState *dev, bool inserted)
|
|
|
|
{
|
|
|
|
PXA2xxMMCIState *s = PXA2XX_MMCI(dev);
|
|
|
|
|
|
|
|
qemu_set_irq(s->inserted, inserted);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pxa2xx_mmci_set_readonly(DeviceState *dev, bool readonly)
|
|
|
|
{
|
|
|
|
PXA2xxMMCIState *s = PXA2XX_MMCI(dev);
|
|
|
|
|
|
|
|
qemu_set_irq(s->readonly, readonly);
|
|
|
|
}
|
|
|
|
|
2009-05-10 02:44:56 +02:00
|
|
|
void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
|
2016-02-18 15:16:19 +01:00
|
|
|
qemu_irq coverswitch)
|
2007-04-30 03:48:07 +02:00
|
|
|
{
|
2016-02-18 15:16:19 +01:00
|
|
|
DeviceState *dev = DEVICE(s);
|
|
|
|
|
|
|
|
s->readonly = readonly;
|
|
|
|
s->inserted = coverswitch;
|
|
|
|
|
|
|
|
pxa2xx_mmci_set_inserted(dev, sdbus_get_inserted(&s->sdbus));
|
|
|
|
pxa2xx_mmci_set_readonly(dev, sdbus_get_readonly(&s->sdbus));
|
2007-04-30 03:48:07 +02:00
|
|
|
}
|
2016-02-18 15:16:19 +01:00
|
|
|
|
2016-02-18 15:16:19 +01:00
|
|
|
static void pxa2xx_mmci_reset(DeviceState *d)
|
|
|
|
{
|
|
|
|
PXA2xxMMCIState *s = PXA2XX_MMCI(d);
|
|
|
|
|
|
|
|
s->status = 0;
|
|
|
|
s->clkrt = 0;
|
|
|
|
s->spi = 0;
|
|
|
|
s->cmdat = 0;
|
|
|
|
s->resp_tout = 0;
|
|
|
|
s->read_tout = 0;
|
|
|
|
s->blklen = 0;
|
|
|
|
s->numblk = 0;
|
|
|
|
s->intmask = 0;
|
|
|
|
s->intreq = 0;
|
|
|
|
s->cmd = 0;
|
|
|
|
s->arg = 0;
|
|
|
|
s->active = 0;
|
|
|
|
s->bytesleft = 0;
|
|
|
|
s->tx_start = 0;
|
|
|
|
s->tx_len = 0;
|
|
|
|
s->rx_start = 0;
|
|
|
|
s->rx_len = 0;
|
|
|
|
s->resp_len = 0;
|
|
|
|
s->cmdreq = 0;
|
|
|
|
memset(s->tx_fifo, 0, sizeof(s->tx_fifo));
|
|
|
|
memset(s->rx_fifo, 0, sizeof(s->rx_fifo));
|
|
|
|
memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
|
|
|
|
}
|
|
|
|
|
2016-02-18 15:16:19 +01:00
|
|
|
static void pxa2xx_mmci_instance_init(Object *obj)
|
|
|
|
{
|
|
|
|
PXA2xxMMCIState *s = PXA2XX_MMCI(obj);
|
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
|
|
|
DeviceState *dev = DEVICE(obj);
|
|
|
|
|
|
|
|
memory_region_init_io(&s->iomem, obj, &pxa2xx_mmci_ops, s,
|
|
|
|
"pxa2xx-mmci", 0x00100000);
|
|
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
|
|
|
sysbus_init_irq(sbd, &s->irq);
|
|
|
|
qdev_init_gpio_out_named(dev, &s->rx_dma, "rx-dma", 1);
|
|
|
|
qdev_init_gpio_out_named(dev, &s->tx_dma, "tx-dma", 1);
|
|
|
|
|
2016-02-18 15:16:19 +01:00
|
|
|
qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
|
|
|
|
TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus");
|
|
|
|
}
|
|
|
|
|
2016-02-18 15:16:19 +01:00
|
|
|
static void pxa2xx_mmci_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
dc->vmsd = &vmstate_pxa2xx_mmci;
|
2016-02-18 15:16:19 +01:00
|
|
|
dc->reset = pxa2xx_mmci_reset;
|
2016-02-18 15:16:19 +01:00
|
|
|
}
|
|
|
|
|
2016-02-18 15:16:19 +01:00
|
|
|
static void pxa2xx_mmci_bus_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
SDBusClass *sbc = SD_BUS_CLASS(klass);
|
|
|
|
|
|
|
|
sbc->set_inserted = pxa2xx_mmci_set_inserted;
|
|
|
|
sbc->set_readonly = pxa2xx_mmci_set_readonly;
|
2016-02-18 15:16:19 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo pxa2xx_mmci_info = {
|
|
|
|
.name = TYPE_PXA2XX_MMCI,
|
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(PXA2xxMMCIState),
|
|
|
|
.instance_init = pxa2xx_mmci_instance_init,
|
2016-02-18 15:16:19 +01:00
|
|
|
.class_init = pxa2xx_mmci_class_init,
|
2016-02-18 15:16:19 +01:00
|
|
|
};
|
|
|
|
|
2016-02-18 15:16:19 +01:00
|
|
|
static const TypeInfo pxa2xx_mmci_bus_info = {
|
|
|
|
.name = TYPE_PXA2XX_MMCI_BUS,
|
|
|
|
.parent = TYPE_SD_BUS,
|
|
|
|
.instance_size = sizeof(SDBus),
|
|
|
|
.class_init = pxa2xx_mmci_bus_class_init,
|
|
|
|
};
|
|
|
|
|
2016-02-18 15:16:19 +01:00
|
|
|
static void pxa2xx_mmci_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&pxa2xx_mmci_info);
|
2016-02-18 15:16:19 +01:00
|
|
|
type_register_static(&pxa2xx_mmci_bus_info);
|
2016-02-18 15:16:19 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
type_init(pxa2xx_mmci_register_types)
|