2012-04-12 02:17:53 +02:00
|
|
|
/*
|
|
|
|
* QEMU MicroBlaze CPU
|
|
|
|
*
|
2012-04-12 02:26:28 +02:00
|
|
|
* Copyright (c) 2009 Edgar E. Iglesias
|
|
|
|
* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
|
2012-04-12 02:17:53 +02:00
|
|
|
* Copyright (c) 2012 SUSE LINUX Products GmbH
|
2014-01-13 04:35:26 +01:00
|
|
|
* Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
|
2012-04-12 02:17:53 +02:00
|
|
|
*
|
|
|
|
* This library is free software; you can redistribute it and/or
|
|
|
|
* modify it under the terms of the GNU Lesser General Public
|
|
|
|
* License as published by the Free Software Foundation; either
|
|
|
|
* version 2.1 of the License, or (at your option) any later version.
|
|
|
|
*
|
|
|
|
* This library is distributed in the hope that it will be useful,
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
|
|
* Lesser General Public License for more details.
|
|
|
|
*
|
|
|
|
* You should have received a copy of the GNU Lesser General Public
|
|
|
|
* License along with this library; if not, see
|
|
|
|
* <http://www.gnu.org/licenses/lgpl-2.1.html>
|
|
|
|
*/
|
|
|
|
|
2016-01-26 19:05:31 +01:00
|
|
|
#include "qemu/osdep.h"
|
include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 09:01:28 +01:00
|
|
|
#include "qapi/error.h"
|
2012-04-12 02:17:53 +02:00
|
|
|
#include "cpu.h"
|
|
|
|
#include "qemu-common.h"
|
2013-04-23 14:27:09 +02:00
|
|
|
#include "hw/qdev-properties.h"
|
2013-01-20 19:03:32 +01:00
|
|
|
#include "migration/vmstate.h"
|
2016-03-15 13:18:37 +01:00
|
|
|
#include "exec/exec-all.h"
|
2012-04-12 02:17:53 +02:00
|
|
|
|
2015-06-19 06:16:38 +02:00
|
|
|
static const struct {
|
|
|
|
const char *name;
|
|
|
|
uint8_t version_id;
|
|
|
|
} mb_cpu_lookup[] = {
|
|
|
|
/* These key value are as per MBV field in PVR0 */
|
|
|
|
{"5.00.a", 0x01},
|
|
|
|
{"5.00.b", 0x02},
|
|
|
|
{"5.00.c", 0x03},
|
|
|
|
{"6.00.a", 0x04},
|
|
|
|
{"6.00.b", 0x06},
|
|
|
|
{"7.00.a", 0x05},
|
|
|
|
{"7.00.b", 0x07},
|
|
|
|
{"7.10.a", 0x08},
|
|
|
|
{"7.10.b", 0x09},
|
|
|
|
{"7.10.c", 0x0a},
|
|
|
|
{"7.10.d", 0x0b},
|
|
|
|
{"7.20.a", 0x0c},
|
|
|
|
{"7.20.b", 0x0d},
|
|
|
|
{"7.20.c", 0x0e},
|
|
|
|
{"7.20.d", 0x0f},
|
|
|
|
{"7.30.a", 0x10},
|
|
|
|
{"7.30.b", 0x11},
|
|
|
|
{"8.00.a", 0x12},
|
|
|
|
{"8.00.b", 0x13},
|
|
|
|
{"8.10.a", 0x14},
|
|
|
|
{"8.20.a", 0x15},
|
|
|
|
{"8.20.b", 0x16},
|
|
|
|
{"8.30.a", 0x17},
|
|
|
|
{"8.40.a", 0x18},
|
|
|
|
{"8.40.b", 0x19},
|
|
|
|
{"8.50.a", 0x1A},
|
|
|
|
{"9.0", 0x1B},
|
|
|
|
{"9.1", 0x1D},
|
|
|
|
{"9.2", 0x1F},
|
|
|
|
{"9.3", 0x20},
|
2017-01-11 12:06:52 +01:00
|
|
|
{"9.4", 0x21},
|
|
|
|
{"9.5", 0x22},
|
|
|
|
{"9.6", 0x23},
|
2015-06-19 06:16:38 +02:00
|
|
|
{NULL, 0},
|
|
|
|
};
|
2012-04-12 02:17:53 +02:00
|
|
|
|
2013-06-21 19:09:18 +02:00
|
|
|
static void mb_cpu_set_pc(CPUState *cs, vaddr value)
|
|
|
|
{
|
|
|
|
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
|
|
|
|
|
|
|
|
cpu->env.sregs[SR_PC] = value;
|
|
|
|
}
|
|
|
|
|
2013-08-25 18:53:55 +02:00
|
|
|
static bool mb_cpu_has_work(CPUState *cs)
|
|
|
|
{
|
|
|
|
return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
|
|
|
|
}
|
|
|
|
|
2014-01-13 04:35:26 +01:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
|
|
|
|
{
|
|
|
|
MicroBlazeCPU *cpu = opaque;
|
|
|
|
CPUState *cs = CPU(cpu);
|
|
|
|
int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
|
|
|
|
|
|
|
|
if (level) {
|
|
|
|
cpu_interrupt(cs, type);
|
|
|
|
} else {
|
|
|
|
cpu_reset_interrupt(cs, type);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-04-12 02:17:53 +02:00
|
|
|
/* CPUClass::reset() */
|
|
|
|
static void mb_cpu_reset(CPUState *s)
|
|
|
|
{
|
|
|
|
MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
|
|
|
|
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
|
|
|
|
CPUMBState *env = &cpu->env;
|
|
|
|
|
|
|
|
mcc->parent_reset(s);
|
|
|
|
|
2016-11-14 15:19:17 +01:00
|
|
|
memset(env, 0, offsetof(CPUMBState, end_reset_fields));
|
2012-06-01 05:23:28 +02:00
|
|
|
env->res_addr = RES_ADDR_NONE;
|
2012-04-12 02:26:28 +02:00
|
|
|
|
|
|
|
/* Disable stack protector. */
|
|
|
|
env->shr = ~0;
|
|
|
|
|
2015-07-23 17:13:56 +02:00
|
|
|
env->sregs[SR_PC] = cpu->cfg.base_vectors;
|
|
|
|
|
2015-05-29 08:30:05 +02:00
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
|
|
/* start in user mode with interrupts enabled. */
|
|
|
|
env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
|
|
|
|
#else
|
|
|
|
env->sregs[SR_MSR] = 0;
|
|
|
|
mmu_init(&env->mmu);
|
|
|
|
env->mmu.c_mmu = 3;
|
|
|
|
env->mmu.c_mmu_tlb_access = 3;
|
|
|
|
env->mmu.c_mmu_zones = 16;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2015-06-24 05:57:36 +02:00
|
|
|
static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
|
|
|
|
{
|
|
|
|
info->mach = bfd_arch_microblaze;
|
|
|
|
info->print_insn = print_insn_microblaze;
|
|
|
|
}
|
|
|
|
|
2015-05-29 08:30:05 +02:00
|
|
|
static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
|
|
|
|
{
|
|
|
|
CPUState *cs = CPU(dev);
|
|
|
|
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
|
|
|
|
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
|
|
|
|
CPUMBState *env = &cpu->env;
|
2015-06-19 06:16:38 +02:00
|
|
|
uint8_t version_code = 0;
|
|
|
|
int i = 0;
|
2016-10-20 13:26:03 +02:00
|
|
|
Error *local_err = NULL;
|
|
|
|
|
|
|
|
cpu_exec_realizefn(cs, &local_err);
|
|
|
|
if (local_err != NULL) {
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
return;
|
|
|
|
}
|
2015-05-29 08:30:05 +02:00
|
|
|
|
|
|
|
qemu_init_vcpu(cs);
|
|
|
|
|
2017-06-20 13:06:44 +02:00
|
|
|
env->pvr.regs[0] = PVR0_USE_EXC_MASK \
|
2012-04-12 02:26:28 +02:00
|
|
|
| PVR0_USE_ICACHE_MASK \
|
2017-01-10 17:24:01 +01:00
|
|
|
| PVR0_USE_DCACHE_MASK;
|
2012-04-12 02:26:28 +02:00
|
|
|
env->pvr.regs[2] = PVR2_D_OPB_MASK \
|
|
|
|
| PVR2_D_LMB_MASK \
|
|
|
|
| PVR2_I_OPB_MASK \
|
|
|
|
| PVR2_I_LMB_MASK \
|
|
|
|
| PVR2_FPU_EXC_MASK \
|
|
|
|
| 0;
|
2015-05-29 08:30:43 +02:00
|
|
|
|
2015-06-19 06:16:38 +02:00
|
|
|
for (i = 0; mb_cpu_lookup[i].name && cpu->cfg.version; i++) {
|
|
|
|
if (strcmp(mb_cpu_lookup[i].name, cpu->cfg.version) == 0) {
|
|
|
|
version_code = mb_cpu_lookup[i].version_id;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!version_code) {
|
|
|
|
qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
|
|
|
|
}
|
|
|
|
|
2015-05-29 08:31:58 +02:00
|
|
|
env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
|
2015-06-19 06:16:29 +02:00
|
|
|
(cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
|
2017-06-20 13:06:44 +02:00
|
|
|
(cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) |
|
2017-06-16 17:21:05 +02:00
|
|
|
(cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) |
|
2017-06-18 09:34:36 +02:00
|
|
|
(cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) |
|
2015-06-19 06:16:35 +02:00
|
|
|
(cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
|
2015-06-19 06:16:38 +02:00
|
|
|
(cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
|
2017-01-10 17:14:34 +01:00
|
|
|
(version_code << PVR0_VERSION_SHIFT) |
|
2015-06-19 06:16:42 +02:00
|
|
|
(cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0);
|
2015-05-29 08:31:58 +02:00
|
|
|
|
2015-06-19 06:16:25 +02:00
|
|
|
env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
|
2017-06-16 17:21:05 +02:00
|
|
|
(cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
|
2017-06-20 13:06:44 +02:00
|
|
|
(cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
|
|
|
|
(cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |
|
2017-06-18 09:34:36 +02:00
|
|
|
(cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
|
2017-06-20 13:13:26 +02:00
|
|
|
(cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
|
2017-06-20 13:53:53 +02:00
|
|
|
(cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) |
|
|
|
|
(cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0);
|
2015-05-29 08:30:43 +02:00
|
|
|
|
2015-06-19 06:16:32 +02:00
|
|
|
env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
|
|
|
|
PVR5_DCACHE_WRITEBACK_MASK : 0;
|
|
|
|
|
2012-04-12 02:26:28 +02:00
|
|
|
env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
|
|
|
|
env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
|
|
|
|
|
2013-01-05 15:27:31 +01:00
|
|
|
mcc->parent_realize(dev, errp);
|
|
|
|
}
|
|
|
|
|
2012-04-12 02:34:40 +02:00
|
|
|
static void mb_cpu_initfn(Object *obj)
|
|
|
|
{
|
2013-01-17 12:13:41 +01:00
|
|
|
CPUState *cs = CPU(obj);
|
2012-04-12 02:34:40 +02:00
|
|
|
MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
|
|
|
|
CPUMBState *env = &cpu->env;
|
2013-01-20 01:10:52 +01:00
|
|
|
static bool tcg_initialized;
|
2012-04-12 02:34:40 +02:00
|
|
|
|
2013-01-17 12:13:41 +01:00
|
|
|
cs->env_ptr = env;
|
2012-04-12 02:34:40 +02:00
|
|
|
|
|
|
|
set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
|
2013-01-20 01:10:52 +01:00
|
|
|
|
2014-01-13 04:35:26 +01:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
/* Inbound IRQ and FIR lines */
|
|
|
|
qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
|
|
|
|
#endif
|
|
|
|
|
2013-01-20 01:10:52 +01:00
|
|
|
if (tcg_enabled() && !tcg_initialized) {
|
|
|
|
tcg_initialized = true;
|
|
|
|
mb_tcg_init();
|
|
|
|
}
|
2012-04-12 02:34:40 +02:00
|
|
|
}
|
|
|
|
|
2013-01-20 19:03:32 +01:00
|
|
|
static const VMStateDescription vmstate_mb_cpu = {
|
|
|
|
.name = "cpu",
|
|
|
|
.unmigratable = 1,
|
|
|
|
};
|
|
|
|
|
2013-04-23 14:27:09 +02:00
|
|
|
static Property mb_properties[] = {
|
2015-05-29 08:31:20 +02:00
|
|
|
DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
|
2015-05-29 08:30:43 +02:00
|
|
|
DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
|
2015-05-29 08:32:35 +02:00
|
|
|
false),
|
2015-05-29 08:31:58 +02:00
|
|
|
/* If use-fpu > 0 - FPU is enabled
|
|
|
|
* If use-fpu = 2 - Floating point conversion and square root instructions
|
|
|
|
* are enabled
|
|
|
|
*/
|
2015-06-19 06:16:25 +02:00
|
|
|
DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
|
2017-06-20 13:06:44 +02:00
|
|
|
/* If use-hw-mul > 0 - Multiplier is enabled
|
|
|
|
* If use-hw-mul = 2 - 64-bit multiplier is enabled
|
|
|
|
*/
|
|
|
|
DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),
|
2017-06-16 17:21:05 +02:00
|
|
|
DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
|
2017-06-18 09:34:36 +02:00
|
|
|
DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
|
2017-06-20 13:13:26 +02:00
|
|
|
DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
|
2017-06-20 13:53:53 +02:00
|
|
|
DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true),
|
2015-06-19 06:16:29 +02:00
|
|
|
DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
|
2015-06-19 06:16:32 +02:00
|
|
|
DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
|
|
|
|
false),
|
2015-06-19 06:16:35 +02:00
|
|
|
DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
|
2015-06-19 06:16:38 +02:00
|
|
|
DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
|
2015-06-19 06:16:42 +02:00
|
|
|
DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
|
2013-04-23 14:27:09 +02:00
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
2012-04-12 02:17:53 +02:00
|
|
|
static void mb_cpu_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-01-20 19:03:32 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2012-04-12 02:17:53 +02:00
|
|
|
CPUClass *cc = CPU_CLASS(oc);
|
|
|
|
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
|
|
|
|
|
2013-01-05 15:27:31 +01:00
|
|
|
mcc->parent_realize = dc->realize;
|
|
|
|
dc->realize = mb_cpu_realizefn;
|
|
|
|
|
2012-04-12 02:17:53 +02:00
|
|
|
mcc->parent_reset = cc->reset;
|
|
|
|
cc->reset = mb_cpu_reset;
|
2013-01-20 19:03:32 +01:00
|
|
|
|
2013-08-25 18:53:55 +02:00
|
|
|
cc->has_work = mb_cpu_has_work;
|
2013-02-02 10:57:51 +01:00
|
|
|
cc->do_interrupt = mb_cpu_do_interrupt;
|
2014-09-13 18:45:30 +02:00
|
|
|
cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
|
2013-05-27 01:33:50 +02:00
|
|
|
cc->dump_state = mb_cpu_dump_state;
|
2013-06-21 19:09:18 +02:00
|
|
|
cc->set_pc = mb_cpu_set_pc;
|
2013-06-29 04:18:45 +02:00
|
|
|
cc->gdb_read_register = mb_cpu_gdb_read_register;
|
|
|
|
cc->gdb_write_register = mb_cpu_gdb_write_register;
|
2013-08-26 03:01:33 +02:00
|
|
|
#ifdef CONFIG_USER_ONLY
|
|
|
|
cc->handle_mmu_fault = mb_cpu_handle_mmu_fault;
|
|
|
|
#else
|
2013-06-29 18:55:54 +02:00
|
|
|
cc->do_unassigned_access = mb_cpu_unassigned_access;
|
|
|
|
cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
|
|
|
|
#endif
|
2013-01-20 19:03:32 +01:00
|
|
|
dc->vmsd = &vmstate_mb_cpu;
|
2013-04-23 14:27:09 +02:00
|
|
|
dc->props = mb_properties;
|
2013-06-28 23:18:47 +02:00
|
|
|
cc->gdb_num_core_regs = 32 + 5;
|
2015-06-24 05:57:36 +02:00
|
|
|
|
|
|
|
cc->disas_set_info = mb_disas_set_info;
|
2012-04-12 02:17:53 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo mb_cpu_type_info = {
|
|
|
|
.name = TYPE_MICROBLAZE_CPU,
|
|
|
|
.parent = TYPE_CPU,
|
|
|
|
.instance_size = sizeof(MicroBlazeCPU),
|
2012-04-12 02:34:40 +02:00
|
|
|
.instance_init = mb_cpu_initfn,
|
2012-04-12 02:17:53 +02:00
|
|
|
.class_size = sizeof(MicroBlazeCPUClass),
|
|
|
|
.class_init = mb_cpu_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void mb_cpu_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&mb_cpu_type_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(mb_cpu_register_types)
|