2010-10-13 20:38:07 +02:00
|
|
|
|
2007-10-29 00:42:18 +01:00
|
|
|
/*
|
2009-01-08 00:38:59 +01:00
|
|
|
* QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
|
2007-10-29 00:42:18 +01:00
|
|
|
*
|
|
|
|
* Copyright (c) 2004-2007 Fabrice Bellard
|
|
|
|
* Copyright (c) 2007 Jocelyn Mayer
|
|
|
|
*
|
|
|
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
|
|
|
* of this software and associated documentation files (the "Software"), to deal
|
|
|
|
* in the Software without restriction, including without limitation the rights
|
|
|
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
|
|
|
* copies of the Software, and to permit persons to whom the Software is
|
|
|
|
* furnished to do so, subject to the following conditions:
|
|
|
|
*
|
|
|
|
* The above copyright notice and this permission notice shall be included in
|
|
|
|
* all copies or substantial portions of the Software.
|
|
|
|
*
|
|
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
|
|
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
|
|
|
* THE SOFTWARE.
|
|
|
|
*/
|
2013-01-24 00:03:54 +01:00
|
|
|
#include "hw/hw.h"
|
2013-02-05 17:06:20 +01:00
|
|
|
#include "hw/ppc/ppc.h"
|
2013-01-24 00:03:54 +01:00
|
|
|
#include "mac.h"
|
2013-02-05 17:06:20 +01:00
|
|
|
#include "hw/input/adb.h"
|
|
|
|
#include "hw/timer/m48t59.h"
|
2012-12-17 18:20:04 +01:00
|
|
|
#include "sysemu/sysemu.h"
|
2012-10-24 08:43:34 +02:00
|
|
|
#include "net/net.h"
|
2013-02-05 17:06:20 +01:00
|
|
|
#include "hw/isa/isa.h"
|
2013-01-24 00:03:54 +01:00
|
|
|
#include "hw/pci/pci.h"
|
|
|
|
#include "hw/boards.h"
|
2013-02-05 17:06:20 +01:00
|
|
|
#include "hw/nvram/fw_cfg.h"
|
|
|
|
#include "hw/char/escc.h"
|
2013-01-24 00:03:54 +01:00
|
|
|
#include "hw/ide.h"
|
|
|
|
#include "hw/loader.h"
|
2009-09-20 16:58:02 +02:00
|
|
|
#include "elf.h"
|
2012-12-17 18:20:04 +01:00
|
|
|
#include "sysemu/kvm.h"
|
2010-02-09 17:37:05 +01:00
|
|
|
#include "kvm_ppc.h"
|
2014-10-07 13:59:18 +02:00
|
|
|
#include "sysemu/block-backend.h"
|
2012-12-17 18:19:49 +01:00
|
|
|
#include "exec/address-spaces.h"
|
2007-10-29 00:42:18 +01:00
|
|
|
|
2007-12-02 05:51:10 +01:00
|
|
|
#define MAX_IDE_BUS 2
|
2008-12-24 21:29:16 +01:00
|
|
|
#define CFG_ADDR 0xf0000510
|
2013-06-29 17:34:58 +02:00
|
|
|
#define TBFREQ 16600000UL
|
2014-04-17 19:04:44 +02:00
|
|
|
#define CLOCKFREQ 266000000UL
|
|
|
|
#define BUSFREQ 66000000UL
|
2008-12-24 21:29:16 +01:00
|
|
|
|
2014-12-03 20:04:02 +01:00
|
|
|
static void fw_cfg_boot_set(void *opaque, const char *boot_device,
|
|
|
|
Error **errp)
|
2009-03-08 10:51:29 +01:00
|
|
|
{
|
2015-06-08 20:10:45 +02:00
|
|
|
fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
2009-03-08 10:51:29 +01:00
|
|
|
}
|
|
|
|
|
2010-03-14 21:20:59 +01:00
|
|
|
static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
|
|
|
|
{
|
|
|
|
return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static hwaddr round_page(hwaddr addr)
|
2011-06-15 23:27:19 +02:00
|
|
|
{
|
|
|
|
return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
|
|
|
|
}
|
|
|
|
|
2012-02-08 03:03:33 +01:00
|
|
|
static void ppc_heathrow_reset(void *opaque)
|
|
|
|
{
|
2012-05-04 17:42:23 +02:00
|
|
|
PowerPCCPU *cpu = opaque;
|
2012-02-08 03:03:33 +01:00
|
|
|
|
2012-05-04 17:42:23 +02:00
|
|
|
cpu_reset(CPU(cpu));
|
2012-02-08 03:03:33 +01:00
|
|
|
}
|
|
|
|
|
2014-05-07 16:42:57 +02:00
|
|
|
static void ppc_heathrow_init(MachineState *machine)
|
2007-10-29 00:42:18 +01:00
|
|
|
{
|
2014-05-07 16:42:57 +02:00
|
|
|
ram_addr_t ram_size = machine->ram_size;
|
|
|
|
const char *cpu_model = machine->cpu_model;
|
|
|
|
const char *kernel_filename = machine->kernel_filename;
|
|
|
|
const char *kernel_cmdline = machine->kernel_cmdline;
|
|
|
|
const char *initrd_filename = machine->initrd_filename;
|
|
|
|
const char *boot_device = machine->boot_order;
|
2011-09-25 15:27:52 +02:00
|
|
|
MemoryRegion *sysmem = get_system_memory();
|
2012-05-04 17:38:41 +02:00
|
|
|
PowerPCCPU *cpu = NULL;
|
2012-03-14 01:38:23 +01:00
|
|
|
CPUPPCState *env = NULL;
|
2009-05-30 01:52:44 +02:00
|
|
|
char *filename;
|
2007-10-29 00:42:18 +01:00
|
|
|
qemu_irq *pic, **heathrow_irqs;
|
|
|
|
int linux_boot, i;
|
2011-09-25 15:27:52 +02:00
|
|
|
MemoryRegion *ram = g_new(MemoryRegion, 1);
|
|
|
|
MemoryRegion *bios = g_new(MemoryRegion, 1);
|
2013-07-22 15:54:12 +02:00
|
|
|
MemoryRegion *isa = g_new(MemoryRegion, 1);
|
2011-06-15 23:27:19 +02:00
|
|
|
uint32_t kernel_base, initrd_base, cmdline_base = 0;
|
2009-01-24 13:00:23 +01:00
|
|
|
int32_t kernel_size, initrd_size;
|
2007-10-29 00:42:18 +01:00
|
|
|
PCIBus *pci_bus;
|
2013-01-24 00:03:57 +01:00
|
|
|
PCIDevice *macio;
|
2013-01-24 00:04:01 +01:00
|
|
|
MACIOIDEState *macio_ide;
|
|
|
|
DeviceState *dev;
|
2013-01-24 00:04:05 +01:00
|
|
|
BusState *adb_bus;
|
2010-10-13 20:38:07 +02:00
|
|
|
int bios_size;
|
2013-01-24 00:04:02 +01:00
|
|
|
MemoryRegion *pic_mem;
|
2013-01-24 00:04:01 +01:00
|
|
|
MemoryRegion *escc_mem, *escc_bar = g_new(MemoryRegion, 1);
|
2009-03-08 10:51:29 +01:00
|
|
|
uint16_t ppc_boot_device;
|
2009-08-28 15:47:03 +02:00
|
|
|
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
|
2008-12-24 21:29:16 +01:00
|
|
|
void *fw_cfg;
|
2014-07-13 22:29:02 +02:00
|
|
|
uint64_t tbfreq;
|
2007-10-29 00:42:18 +01:00
|
|
|
|
|
|
|
linux_boot = (kernel_filename != NULL);
|
|
|
|
|
|
|
|
/* init CPUs */
|
|
|
|
if (cpu_model == NULL)
|
2008-12-21 00:39:46 +01:00
|
|
|
cpu_model = "G3";
|
2007-10-29 00:42:18 +01:00
|
|
|
for (i = 0; i < smp_cpus; i++) {
|
2012-05-04 17:38:41 +02:00
|
|
|
cpu = cpu_ppc_init(cpu_model);
|
|
|
|
if (cpu == NULL) {
|
2007-11-10 16:15:54 +01:00
|
|
|
fprintf(stderr, "Unable to find PowerPC CPU definition\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
2012-05-04 17:38:41 +02:00
|
|
|
env = &cpu->env;
|
|
|
|
|
2009-01-14 15:48:04 +01:00
|
|
|
/* Set time-base frequency to 16.6 Mhz */
|
2013-06-29 17:34:58 +02:00
|
|
|
cpu_ppc_tb_init(env, TBFREQ);
|
2012-05-04 17:42:23 +02:00
|
|
|
qemu_register_reset(ppc_heathrow_reset, cpu);
|
2007-10-29 00:42:18 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* allocate RAM */
|
2009-01-13 20:08:10 +01:00
|
|
|
if (ram_size > (2047 << 20)) {
|
|
|
|
fprintf(stderr,
|
|
|
|
"qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
|
|
|
|
((unsigned int)ram_size / (1 << 20)));
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
2014-07-10 14:01:03 +02:00
|
|
|
memory_region_allocate_system_memory(ram, NULL, "ppc_heathrow.ram",
|
|
|
|
ram_size);
|
2011-09-25 15:27:52 +02:00
|
|
|
memory_region_add_subregion(sysmem, 0, ram);
|
2008-12-21 00:40:35 +01:00
|
|
|
|
2007-10-29 00:42:18 +01:00
|
|
|
/* allocate and load BIOS */
|
2014-09-09 07:27:55 +02:00
|
|
|
memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE,
|
|
|
|
&error_abort);
|
ppc: fix -mem-path failure
commit e938ba0c tried to enable -mem-path for ppc but breaked some ppc
boards.
The problems are:
1. it fails when allocating memory for rom, sram whose sizes are less
than huge page size:
./ppc-softmmu/qemu-system-ppc -m 512 -mem-path /hugepages/ \
-kernel /home/hutao/Downloads/vmlinux-ppc -initrd \
/home/hutao/Downloads/initrd-ppc.gz
qemu-system-ppc: /mnt/data/projects/qemu/exec.c:1184: qemu_ram_set_idstr: Assertion `new_block' failed.
2. if there is a numa node backed by memory backend object, qemu fails
with message:
./ppc-softmmu/qemu-system-ppc -m 512 \
-object memory-backend-file,size=512M,mem-path=/hugepages,id=f0 \
-numa node,nodeid=0,memdev=f0 \
-kernel /home/hutao/Downloads/vmlinux-ppc \
-initrd /home/hutao/Downloads/initrd-ppc.gz
qemu-system-ppc: memory backend f0 is used multiple times. Each -numa option must use a different memdev value.
This patch does following:
1. replaces memory_region_allocate_system_memory() with
memory_region_init_ram() for rom, sram. Then only system memory
is backed by hugepages when specifying mem-path.
2. for memory banks, allocates all ram with
one memory_region_allocate_system_memory(), and use
memory_region_init_alias() to initialize memory banks.
Tested machines: default(g3beige), mac99, taihu, bamboo, ref405ep.
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2014-07-21 11:30:17 +02:00
|
|
|
vmstate_register_ram_global(bios);
|
|
|
|
|
2007-10-29 00:42:18 +01:00
|
|
|
if (bios_name == NULL)
|
2008-12-24 21:23:51 +01:00
|
|
|
bios_name = PROM_FILENAME;
|
2009-05-30 01:52:44 +02:00
|
|
|
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
|
2011-09-25 15:27:52 +02:00
|
|
|
memory_region_set_readonly(bios, true);
|
|
|
|
memory_region_add_subregion(sysmem, PROM_ADDR, bios);
|
2008-12-24 21:23:51 +01:00
|
|
|
|
|
|
|
/* Load OpenBIOS (ELF) */
|
2009-05-30 01:52:44 +02:00
|
|
|
if (filename) {
|
2010-03-14 21:20:59 +01:00
|
|
|
bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL,
|
|
|
|
1, ELF_MACHINE, 0);
|
2011-08-21 05:09:37 +02:00
|
|
|
g_free(filename);
|
2009-05-30 01:52:44 +02:00
|
|
|
} else {
|
|
|
|
bios_size = -1;
|
|
|
|
}
|
2007-10-29 00:42:18 +01:00
|
|
|
if (bios_size < 0 || bios_size > BIOS_SIZE) {
|
2009-05-30 01:52:44 +02:00
|
|
|
hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
|
2007-10-29 00:42:18 +01:00
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (linux_boot) {
|
2009-01-26 11:22:15 +01:00
|
|
|
uint64_t lowaddr = 0;
|
2009-09-20 16:58:02 +02:00
|
|
|
int bswap_needed;
|
|
|
|
|
|
|
|
#ifdef BSWAP_NEEDED
|
|
|
|
bswap_needed = 1;
|
|
|
|
#else
|
|
|
|
bswap_needed = 0;
|
|
|
|
#endif
|
2007-10-29 00:42:18 +01:00
|
|
|
kernel_base = KERNEL_LOAD_ADDR;
|
2010-03-14 21:20:59 +01:00
|
|
|
kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
|
|
|
|
NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
|
2008-12-24 21:30:01 +01:00
|
|
|
if (kernel_size < 0)
|
|
|
|
kernel_size = load_aout(kernel_filename, kernel_base,
|
2009-09-20 16:58:02 +02:00
|
|
|
ram_size - kernel_base, bswap_needed,
|
|
|
|
TARGET_PAGE_SIZE);
|
2008-12-24 21:30:01 +01:00
|
|
|
if (kernel_size < 0)
|
|
|
|
kernel_size = load_image_targphys(kernel_filename,
|
|
|
|
kernel_base,
|
|
|
|
ram_size - kernel_base);
|
2007-10-29 00:42:18 +01:00
|
|
|
if (kernel_size < 0) {
|
2009-05-08 03:35:15 +02:00
|
|
|
hw_error("qemu: could not load kernel '%s'\n",
|
2007-10-29 00:42:18 +01:00
|
|
|
kernel_filename);
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
/* load initrd */
|
|
|
|
if (initrd_filename) {
|
2011-06-15 23:27:19 +02:00
|
|
|
initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
|
2009-04-09 22:05:49 +02:00
|
|
|
initrd_size = load_image_targphys(initrd_filename, initrd_base,
|
|
|
|
ram_size - initrd_base);
|
2007-10-29 00:42:18 +01:00
|
|
|
if (initrd_size < 0) {
|
2009-05-08 03:35:15 +02:00
|
|
|
hw_error("qemu: could not load initial ram disk '%s'\n",
|
|
|
|
initrd_filename);
|
2007-10-29 00:42:18 +01:00
|
|
|
exit(1);
|
|
|
|
}
|
2011-06-15 23:27:19 +02:00
|
|
|
cmdline_base = round_page(initrd_base + initrd_size);
|
2007-10-29 00:42:18 +01:00
|
|
|
} else {
|
|
|
|
initrd_base = 0;
|
|
|
|
initrd_size = 0;
|
2011-06-15 23:27:19 +02:00
|
|
|
cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
|
2007-10-29 00:42:18 +01:00
|
|
|
}
|
2007-10-31 02:54:04 +01:00
|
|
|
ppc_boot_device = 'm';
|
2007-10-29 00:42:18 +01:00
|
|
|
} else {
|
|
|
|
kernel_base = 0;
|
|
|
|
kernel_size = 0;
|
|
|
|
initrd_base = 0;
|
|
|
|
initrd_size = 0;
|
2007-11-11 02:50:45 +01:00
|
|
|
ppc_boot_device = '\0';
|
2007-11-11 15:44:28 +01:00
|
|
|
for (i = 0; boot_device[i] != '\0'; i++) {
|
2007-11-11 02:50:45 +01:00
|
|
|
/* TOFIX: for now, the second IDE channel is not properly
|
2007-11-11 15:44:28 +01:00
|
|
|
* used by OHW. The Mac floppy disk are not emulated.
|
2007-11-11 02:50:45 +01:00
|
|
|
* For now, OHW cannot boot from the network.
|
|
|
|
*/
|
|
|
|
#if 0
|
2007-11-11 15:44:28 +01:00
|
|
|
if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
|
|
|
|
ppc_boot_device = boot_device[i];
|
2007-11-11 02:50:45 +01:00
|
|
|
break;
|
2007-11-11 15:44:28 +01:00
|
|
|
}
|
2007-11-11 02:50:45 +01:00
|
|
|
#else
|
2007-11-11 15:44:28 +01:00
|
|
|
if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
|
|
|
|
ppc_boot_device = boot_device[i];
|
2007-11-11 02:50:45 +01:00
|
|
|
break;
|
2007-11-11 15:44:28 +01:00
|
|
|
}
|
2007-11-11 02:50:45 +01:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
if (ppc_boot_device == '\0') {
|
2009-01-13 20:07:59 +01:00
|
|
|
fprintf(stderr, "No valid boot device for G3 Beige machine\n");
|
2007-11-11 02:50:45 +01:00
|
|
|
exit(1);
|
|
|
|
}
|
2007-10-29 00:42:18 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Register 2 MB of ISA IO space */
|
2013-07-22 15:54:12 +02:00
|
|
|
memory_region_init_alias(isa, NULL, "isa_mmio",
|
|
|
|
get_system_io(), 0, 0x00200000);
|
|
|
|
memory_region_add_subregion(sysmem, 0xfe000000, isa);
|
2007-10-29 00:42:18 +01:00
|
|
|
|
|
|
|
/* XXX: we register only 1 output pin for heathrow PIC */
|
2011-08-21 05:09:37 +02:00
|
|
|
heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
|
2007-10-29 00:42:18 +01:00
|
|
|
heathrow_irqs[0] =
|
2011-08-21 05:09:37 +02:00
|
|
|
g_malloc0(smp_cpus * sizeof(qemu_irq) * 1);
|
2007-10-29 00:42:18 +01:00
|
|
|
/* Connect the heathrow PIC outputs to the 6xx bus */
|
|
|
|
for (i = 0; i < smp_cpus; i++) {
|
|
|
|
switch (PPC_INPUT(env)) {
|
|
|
|
case PPC_FLAGS_INPUT_6xx:
|
|
|
|
heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
|
|
|
|
heathrow_irqs[i][0] =
|
|
|
|
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
|
|
|
|
break;
|
|
|
|
default:
|
2009-05-08 03:35:15 +02:00
|
|
|
hw_error("Bus model not supported on OldWorld Mac machine\n");
|
2007-10-29 00:42:18 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-07-13 22:29:02 +02:00
|
|
|
/* Timebase Frequency */
|
|
|
|
if (kvm_enabled()) {
|
|
|
|
tbfreq = kvmppc_get_tbfreq();
|
|
|
|
} else {
|
|
|
|
tbfreq = TBFREQ;
|
|
|
|
}
|
|
|
|
|
2007-10-29 00:42:18 +01:00
|
|
|
/* init basic PC hardware */
|
|
|
|
if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
|
2009-05-08 03:35:15 +02:00
|
|
|
hw_error("Only 6xx bus is supported on heathrow machine\n");
|
2007-10-29 00:42:18 +01:00
|
|
|
}
|
2011-08-08 15:09:17 +02:00
|
|
|
pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs);
|
2011-08-08 15:09:04 +02:00
|
|
|
pci_bus = pci_grackle_init(0xfec00000, pic,
|
|
|
|
get_system_memory(),
|
|
|
|
get_system_io());
|
2012-09-08 12:21:20 +02:00
|
|
|
pci_vga_init(pci_bus);
|
2007-11-24 03:56:36 +01:00
|
|
|
|
2011-09-30 15:29:12 +02:00
|
|
|
escc_mem = escc_init(0, pic[0x0f], pic[0x10], serial_hds[0],
|
2009-01-12 18:40:23 +01:00
|
|
|
serial_hds[1], ESCC_CLOCK, 4);
|
2013-06-06 11:41:28 +02:00
|
|
|
memory_region_init_alias(escc_bar, NULL, "escc-bar",
|
2011-08-24 20:37:05 +02:00
|
|
|
escc_mem, 0, memory_region_size(escc_mem));
|
2007-11-24 03:56:36 +01:00
|
|
|
|
2009-01-13 20:47:10 +01:00
|
|
|
for(i = 0; i < nb_nics; i++)
|
2013-06-06 10:48:51 +02:00
|
|
|
pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
|
2007-11-11 15:44:28 +01:00
|
|
|
|
2007-12-02 05:51:10 +01:00
|
|
|
|
2014-10-01 20:19:27 +02:00
|
|
|
ide_drive_get(hd, ARRAY_SIZE(hd));
|
2009-03-07 22:35:21 +01:00
|
|
|
|
2013-01-24 00:03:57 +01:00
|
|
|
macio = pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO);
|
2013-01-24 00:04:01 +01:00
|
|
|
dev = DEVICE(macio);
|
2013-01-24 00:04:02 +01:00
|
|
|
qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */
|
2013-06-24 21:40:50 +02:00
|
|
|
qdev_connect_gpio_out(dev, 1, pic[0x0D]); /* IDE-0 */
|
|
|
|
qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE-0 DMA */
|
|
|
|
qdev_connect_gpio_out(dev, 3, pic[0x0E]); /* IDE-1 */
|
|
|
|
qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE-1 DMA */
|
2014-07-13 22:31:53 +02:00
|
|
|
qdev_prop_set_uint64(dev, "frequency", tbfreq);
|
2013-01-24 00:04:02 +01:00
|
|
|
macio_init(macio, pic_mem, escc_bar);
|
2013-01-24 00:04:01 +01:00
|
|
|
|
|
|
|
macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
|
2013-06-24 21:40:50 +02:00
|
|
|
"ide[0]"));
|
2013-01-24 00:04:01 +01:00
|
|
|
macio_ide_init_drives(macio_ide, hd);
|
|
|
|
|
2013-06-24 21:40:50 +02:00
|
|
|
macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
|
|
|
|
"ide[1]"));
|
|
|
|
macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
|
2007-10-29 00:42:18 +01:00
|
|
|
|
2013-01-24 00:04:05 +01:00
|
|
|
dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
|
|
|
|
adb_bus = qdev_get_child_bus(dev, "adb.0");
|
|
|
|
dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
|
2013-01-24 00:04:04 +01:00
|
|
|
qdev_init_nofail(dev);
|
2013-01-24 00:04:05 +01:00
|
|
|
dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
|
2013-01-24 00:04:04 +01:00
|
|
|
qdev_init_nofail(dev);
|
2013-01-24 00:04:02 +01:00
|
|
|
|
2015-01-06 14:29:14 +01:00
|
|
|
if (usb_enabled()) {
|
2012-03-07 15:06:32 +01:00
|
|
|
pci_create_simple(pci_bus, -1, "pci-ohci");
|
2007-10-29 00:42:18 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
|
|
|
|
graphic_depth = 15;
|
|
|
|
|
|
|
|
/* No PCI init: the BIOS will do it */
|
|
|
|
|
2014-12-22 13:11:36 +01:00
|
|
|
fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
|
2013-01-22 21:25:03 +01:00
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
|
2008-12-24 21:29:16 +01:00
|
|
|
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
|
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
|
2009-03-08 10:51:29 +01:00
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
|
|
|
|
if (kernel_cmdline) {
|
2011-06-15 23:27:19 +02:00
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
|
|
|
|
pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
|
2009-03-08 10:51:29 +01:00
|
|
|
} else {
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
|
|
|
}
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
|
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
|
2009-08-08 12:19:24 +02:00
|
|
|
|
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
|
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
|
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
|
|
|
|
|
2010-08-03 15:22:42 +02:00
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
|
2010-02-09 17:37:05 +01:00
|
|
|
if (kvm_enabled()) {
|
|
|
|
#ifdef CONFIG_KVM
|
2010-08-03 15:22:42 +02:00
|
|
|
uint8_t *hypercall;
|
|
|
|
|
2011-08-21 05:09:37 +02:00
|
|
|
hypercall = g_malloc(16);
|
2010-08-03 15:22:42 +02:00
|
|
|
kvmppc_get_hypercall(env, hypercall, 16);
|
|
|
|
fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
|
2010-02-09 17:37:05 +01:00
|
|
|
#endif
|
|
|
|
}
|
2014-07-13 22:29:02 +02:00
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
|
2013-06-23 00:22:50 +02:00
|
|
|
/* Mac OS X requires a "known good" clock-frequency value; pass it one. */
|
2014-04-17 19:04:44 +02:00
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
|
2010-02-09 17:37:05 +01:00
|
|
|
|
2009-03-08 10:51:29 +01:00
|
|
|
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
|
2007-10-29 00:42:18 +01:00
|
|
|
}
|
|
|
|
|
2014-07-24 10:46:47 +02:00
|
|
|
static int heathrow_kvm_type(const char *arg)
|
|
|
|
{
|
|
|
|
/* Always force PR KVM */
|
|
|
|
return 2;
|
|
|
|
}
|
|
|
|
|
2009-05-21 01:38:09 +02:00
|
|
|
static QEMUMachine heathrow_machine = {
|
2009-01-08 00:38:59 +01:00
|
|
|
.name = "g3beige",
|
2008-10-07 22:34:35 +02:00
|
|
|
.desc = "Heathrow based PowerMAC",
|
|
|
|
.init = ppc_heathrow_init,
|
2008-10-28 11:59:59 +01:00
|
|
|
.max_cpus = MAX_CPUS,
|
2009-12-20 00:22:26 +01:00
|
|
|
#ifndef TARGET_PPC64
|
2009-05-22 03:41:01 +02:00
|
|
|
.is_default = 1,
|
2009-12-20 00:22:26 +01:00
|
|
|
#endif
|
hw: Clean up bogus default boot order
We set default boot order "cad" in every single machine definition
except "pseries" and "moxiesim", even though very few boards actually
care for boot order, and "cad" makes sense for even fewer.
Machines that care:
* pc and its variants
Accept up to three letters 'a', 'b' (undocumented alias for 'a'),
'c', 'd' and 'n'. Reject all others (fatal with -boot).
* nseries (n800, n810)
Check whether order starts with 'n'. Silently ignored otherwise.
* prep, g3beige, mac99
Extract the first character the machine understands (subset of
'a'..'f'). Silently ignored otherwise.
* spapr
Accept an arbitrary string (vl.c restricts it to contain only
'a'..'p', no duplicates).
* sun4[mdc]
Use the first character. Silently ignored otherwise.
Strip characters these machines ignore from their default boot order.
For all other machines, remove the unused default boot order
alltogether.
Note that my rename of QEMUMachine member boot_order to
default_boot_order and QEMUMachineInitArgs member boot_device to
boot_order has a welcome side effect: it makes every use of boot
orders visible in this patch, for easy review.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-08-16 13:13:50 +02:00
|
|
|
.default_boot_order = "cd", /* TOFIX "cad" when Mac floppy is implemented */
|
2014-07-24 10:46:47 +02:00
|
|
|
.kvm_type = heathrow_kvm_type,
|
2007-10-29 00:42:18 +01:00
|
|
|
};
|
2009-05-21 01:38:09 +02:00
|
|
|
|
|
|
|
static void heathrow_machine_init(void)
|
|
|
|
{
|
|
|
|
qemu_register_machine(&heathrow_machine);
|
|
|
|
}
|
|
|
|
|
|
|
|
machine_init(heathrow_machine_init);
|