2004-01-04 23:58:38 +01:00
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/*
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2005-07-02 22:59:34 +02:00
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* PowerPC emulation helpers for qemu.
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2007-09-16 23:08:06 +02:00
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*
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2007-03-07 09:32:30 +01:00
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* Copyright (c) 2003-2007 Jocelyn Mayer
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2004-01-04 23:58:38 +01:00
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h"
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2007-03-20 23:11:31 +01:00
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#include "op_helper.h"
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2004-01-04 23:58:38 +01:00
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#define MEMSUFFIX _raw
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2007-03-20 23:11:31 +01:00
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#include "op_helper.h"
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2004-01-04 23:58:38 +01:00
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#include "op_helper_mem.h"
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2004-04-12 22:39:29 +02:00
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#if !defined(CONFIG_USER_ONLY)
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2004-01-04 23:58:38 +01:00
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#define MEMSUFFIX _user
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2007-03-20 23:11:31 +01:00
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#include "op_helper.h"
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2004-01-04 23:58:38 +01:00
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#include "op_helper_mem.h"
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#define MEMSUFFIX _kernel
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2007-03-20 23:11:31 +01:00
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#include "op_helper.h"
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2004-01-04 23:58:38 +01:00
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#include "op_helper_mem.h"
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#endif
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2005-07-05 00:17:05 +02:00
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//#define DEBUG_OP
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//#define DEBUG_EXCEPTIONS
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2007-03-07 09:32:30 +01:00
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//#define DEBUG_SOFTWARE_TLB
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2005-07-05 00:17:05 +02:00
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//#define FLUSH_ALL_TLBS
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2004-01-04 23:58:38 +01:00
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/*****************************************************************************/
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/* Exceptions processing helpers */
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2004-05-21 14:59:32 +02:00
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void do_raise_exception_err (uint32_t exception, int error_code)
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2004-01-04 23:58:38 +01:00
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{
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2004-05-21 14:59:32 +02:00
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#if 0
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printf("Raise exception %3x code : %d\n", exception, error_code);
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#endif
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switch (exception) {
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2007-09-29 15:06:16 +02:00
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case POWERPC_EXCP_PROGRAM:
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if (error_code == POWERPC_EXCP_FP && msr_fe0 == 0 && msr_fe1 == 0)
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2007-03-07 09:32:30 +01:00
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return;
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break;
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2004-05-21 14:59:32 +02:00
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default:
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2007-03-07 09:32:30 +01:00
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break;
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}
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2004-05-21 14:59:32 +02:00
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env->exception_index = exception;
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env->error_code = error_code;
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2007-03-07 09:32:30 +01:00
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cpu_loop_exit();
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}
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2004-05-21 14:59:32 +02:00
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void do_raise_exception (uint32_t exception)
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{
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do_raise_exception_err(exception, 0);
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2004-01-04 23:58:38 +01:00
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}
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2007-04-16 09:10:48 +02:00
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void cpu_dump_EA (target_ulong EA);
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void do_print_mem_EA (target_ulong EA)
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{
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cpu_dump_EA(EA);
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}
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2007-03-07 09:32:30 +01:00
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/*****************************************************************************/
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/* Registers load and stores */
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void do_load_cr (void)
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{
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T0 = (env->crf[0] << 28) |
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(env->crf[1] << 24) |
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(env->crf[2] << 20) |
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(env->crf[3] << 16) |
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(env->crf[4] << 12) |
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(env->crf[5] << 8) |
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(env->crf[6] << 4) |
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(env->crf[7] << 0);
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}
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void do_store_cr (uint32_t mask)
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{
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int i, sh;
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2007-09-17 10:21:54 +02:00
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for (i = 0, sh = 7; i < 8; i++, sh--) {
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2007-03-07 09:32:30 +01:00
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if (mask & (1 << sh))
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env->crf[i] = (T0 >> (sh * 4)) & 0xFUL;
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}
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}
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void do_load_xer (void)
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{
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T0 = (xer_so << XER_SO) |
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(xer_ov << XER_OV) |
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(xer_ca << XER_CA) |
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(xer_bc << XER_BC) |
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(xer_cmp << XER_CMP);
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}
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void do_store_xer (void)
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{
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xer_so = (T0 >> XER_SO) & 0x01;
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xer_ov = (T0 >> XER_OV) & 0x01;
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xer_ca = (T0 >> XER_CA) & 0x01;
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xer_cmp = (T0 >> XER_CMP) & 0xFF;
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2007-03-17 15:02:15 +01:00
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xer_bc = (T0 >> XER_BC) & 0x7F;
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2007-03-07 09:32:30 +01:00
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}
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void do_load_fpscr (void)
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{
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/* The 32 MSB of the target fpr are undefined.
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* They'll be zero...
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*/
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union {
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float64 d;
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struct {
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uint32_t u[2];
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} s;
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} u;
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int i;
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2007-03-17 15:02:15 +01:00
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#if defined(WORDS_BIGENDIAN)
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2007-03-07 09:32:30 +01:00
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#define WORD0 0
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#define WORD1 1
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#else
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#define WORD0 1
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#define WORD1 0
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#endif
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u.s.u[WORD0] = 0;
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u.s.u[WORD1] = 0;
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for (i = 0; i < 8; i++)
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u.s.u[WORD1] |= env->fpscr[i] << (4 * i);
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FT0 = u.d;
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}
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void do_store_fpscr (uint32_t mask)
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{
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/*
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* We use only the 32 LSB of the incoming fpr
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*/
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union {
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double d;
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struct {
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uint32_t u[2];
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} s;
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} u;
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int i, rnd_type;
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u.d = FT0;
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if (mask & 0x80)
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env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[WORD1] >> 28) & ~0x9);
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for (i = 1; i < 7; i++) {
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if (mask & (1 << (7 - i)))
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env->fpscr[i] = (u.s.u[WORD1] >> (4 * (7 - i))) & 0xF;
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}
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/* TODO: update FEX & VX */
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/* Set rounding mode */
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switch (env->fpscr[0] & 0x3) {
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case 0:
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/* Best approximation (round to nearest) */
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rnd_type = float_round_nearest_even;
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break;
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case 1:
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/* Smaller magnitude (round toward zero) */
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rnd_type = float_round_to_zero;
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break;
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case 2:
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/* Round toward +infinite */
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rnd_type = float_round_up;
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break;
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default:
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case 3:
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/* Round toward -infinite */
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rnd_type = float_round_down;
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break;
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}
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set_float_rounding_mode(rnd_type, &env->fp_status);
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}
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2007-04-16 09:10:48 +02:00
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target_ulong ppc_load_dump_spr (int sprn)
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{
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2007-04-24 09:36:03 +02:00
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if (loglevel != 0) {
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2007-04-16 09:10:48 +02:00
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fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
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sprn, sprn, env->spr[sprn]);
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}
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return env->spr[sprn];
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}
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void ppc_store_dump_spr (int sprn, target_ulong val)
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{
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2007-04-24 09:36:03 +02:00
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if (loglevel != 0) {
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2007-04-16 09:10:48 +02:00
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fprintf(logfile, "Write SPR %d %03x => " ADDRX " <= " ADDRX "\n",
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sprn, sprn, env->spr[sprn], val);
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}
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env->spr[sprn] = val;
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}
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2004-01-04 23:58:38 +01:00
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/*****************************************************************************/
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2005-07-05 00:17:05 +02:00
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/* Fixed point operations helpers */
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2007-03-17 15:02:15 +01:00
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#if defined(TARGET_PPC64)
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static void add128 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
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2005-07-05 00:17:05 +02:00
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{
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2007-03-17 15:02:15 +01:00
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*plow += a;
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/* carry test */
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if (*plow < a)
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(*phigh)++;
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*phigh += b;
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2005-07-05 00:17:05 +02:00
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}
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2007-03-17 15:02:15 +01:00
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static void neg128 (uint64_t *plow, uint64_t *phigh)
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2005-07-05 00:17:05 +02:00
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{
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2007-09-17 10:21:54 +02:00
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*plow = ~*plow;
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*phigh = ~*phigh;
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2007-03-17 15:02:15 +01:00
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add128(plow, phigh, 1, 0);
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}
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static void mul64 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
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{
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uint32_t a0, a1, b0, b1;
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uint64_t v;
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a0 = a;
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a1 = a >> 32;
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b0 = b;
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b1 = b >> 32;
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2007-09-17 10:09:54 +02:00
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2007-03-17 15:02:15 +01:00
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v = (uint64_t)a0 * (uint64_t)b0;
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*plow = v;
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*phigh = 0;
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v = (uint64_t)a0 * (uint64_t)b1;
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add128(plow, phigh, v << 32, v >> 32);
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v = (uint64_t)a1 * (uint64_t)b0;
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add128(plow, phigh, v << 32, v >> 32);
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v = (uint64_t)a1 * (uint64_t)b1;
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*phigh += v;
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#if defined(DEBUG_MULDIV)
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printf("mul: 0x%016llx * 0x%016llx = 0x%016llx%016llx\n",
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a, b, *phigh, *plow);
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#endif
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}
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void do_mul64 (uint64_t *plow, uint64_t *phigh)
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{
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mul64(plow, phigh, T0, T1);
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}
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2007-03-20 23:11:31 +01:00
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static void imul64 (uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b)
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2007-03-17 15:02:15 +01:00
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{
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int sa, sb;
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2007-09-17 10:21:54 +02:00
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2007-03-17 15:02:15 +01:00
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sa = (a < 0);
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if (sa)
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a = -a;
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sb = (b < 0);
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if (sb)
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b = -b;
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mul64(plow, phigh, a, b);
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if (sa ^ sb) {
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neg128(plow, phigh);
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2005-07-05 00:17:05 +02:00
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}
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}
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2007-03-17 15:02:15 +01:00
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void do_imul64 (uint64_t *plow, uint64_t *phigh)
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{
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imul64(plow, phigh, T0, T1);
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}
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#endif
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2005-07-05 00:17:05 +02:00
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void do_adde (void)
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{
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T2 = T0;
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T0 += T1 + xer_ca;
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2007-03-17 15:02:15 +01:00
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if (likely(!((uint32_t)T0 < (uint32_t)T2 ||
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(xer_ca == 1 && (uint32_t)T0 == (uint32_t)T2)))) {
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2005-07-05 00:17:05 +02:00
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xer_ca = 0;
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} else {
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xer_ca = 1;
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}
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}
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2007-03-17 15:02:15 +01:00
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#if defined(TARGET_PPC64)
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void do_adde_64 (void)
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2005-07-05 00:17:05 +02:00
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{
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T2 = T0;
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T0 += T1 + xer_ca;
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2007-03-17 15:02:15 +01:00
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if (likely(!((uint64_t)T0 < (uint64_t)T2 ||
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(xer_ca == 1 && (uint64_t)T0 == (uint64_t)T2)))) {
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2005-07-05 00:17:05 +02:00
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xer_ca = 0;
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} else {
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xer_ca = 1;
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}
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}
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2007-03-17 15:02:15 +01:00
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#endif
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2005-07-05 00:17:05 +02:00
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void do_addmeo (void)
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{
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T1 = T0;
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T0 += xer_ca + (-1);
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2007-03-17 15:02:15 +01:00
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if (likely(!((uint32_t)T1 &
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((uint32_t)T1 ^ (uint32_t)T0) & (1UL << 31)))) {
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2005-07-05 00:17:05 +02:00
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xer_ov = 0;
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} else {
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xer_ov = 1;
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2007-09-17 11:51:40 +02:00
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xer_so = 1;
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2005-07-05 00:17:05 +02:00
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}
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if (likely(T1 != 0))
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xer_ca = 1;
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}
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2007-03-17 15:02:15 +01:00
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#if defined(TARGET_PPC64)
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void do_addmeo_64 (void)
|
2005-07-05 00:17:05 +02:00
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|
{
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|
T1 = T0;
|
2007-03-17 15:02:15 +01:00
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|
|
T0 += xer_ca + (-1);
|
|
|
|
if (likely(!((uint64_t)T1 &
|
|
|
|
((uint64_t)T1 ^ (uint64_t)T0) & (1ULL << 63)))) {
|
2005-07-05 00:17:05 +02:00
|
|
|
xer_ov = 0;
|
|
|
|
} else {
|
|
|
|
xer_ov = 1;
|
2007-09-17 11:51:40 +02:00
|
|
|
xer_so = 1;
|
2005-07-05 00:17:05 +02:00
|
|
|
}
|
2007-03-17 15:02:15 +01:00
|
|
|
if (likely(T1 != 0))
|
2005-07-05 00:17:05 +02:00
|
|
|
xer_ca = 1;
|
|
|
|
}
|
2007-03-17 15:02:15 +01:00
|
|
|
#endif
|
2005-07-05 00:17:05 +02:00
|
|
|
|
|
|
|
void do_divwo (void)
|
|
|
|
{
|
2007-03-17 15:02:15 +01:00
|
|
|
if (likely(!(((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) ||
|
|
|
|
(int32_t)T1 == 0))) {
|
2005-07-05 00:17:05 +02:00
|
|
|
xer_ov = 0;
|
2007-03-17 15:02:15 +01:00
|
|
|
T0 = (int32_t)T0 / (int32_t)T1;
|
2005-07-05 00:17:05 +02:00
|
|
|
} else {
|
|
|
|
xer_ov = 1;
|
2007-09-17 11:51:40 +02:00
|
|
|
xer_so = 1;
|
2005-07-05 00:17:05 +02:00
|
|
|
T0 = (-1) * ((uint32_t)T0 >> 31);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-03-17 15:02:15 +01:00
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
void do_divdo (void)
|
|
|
|
{
|
|
|
|
if (likely(!(((int64_t)T0 == INT64_MIN && (int64_t)T1 == -1ULL) ||
|
|
|
|
(int64_t)T1 == 0))) {
|
|
|
|
xer_ov = 0;
|
|
|
|
T0 = (int64_t)T0 / (int64_t)T1;
|
|
|
|
} else {
|
|
|
|
xer_ov = 1;
|
2007-09-17 11:51:40 +02:00
|
|
|
xer_so = 1;
|
2007-03-17 15:02:15 +01:00
|
|
|
T0 = (-1ULL) * ((uint64_t)T0 >> 63);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2005-07-05 00:17:05 +02:00
|
|
|
void do_divwuo (void)
|
|
|
|
{
|
|
|
|
if (likely((uint32_t)T1 != 0)) {
|
|
|
|
xer_ov = 0;
|
|
|
|
T0 = (uint32_t)T0 / (uint32_t)T1;
|
|
|
|
} else {
|
|
|
|
xer_ov = 1;
|
2007-09-17 11:51:40 +02:00
|
|
|
xer_so = 1;
|
2005-07-05 00:17:05 +02:00
|
|
|
T0 = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-03-17 15:02:15 +01:00
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
void do_divduo (void)
|
|
|
|
{
|
|
|
|
if (likely((uint64_t)T1 != 0)) {
|
|
|
|
xer_ov = 0;
|
|
|
|
T0 = (uint64_t)T0 / (uint64_t)T1;
|
|
|
|
} else {
|
|
|
|
xer_ov = 1;
|
2007-09-17 11:51:40 +02:00
|
|
|
xer_so = 1;
|
2007-03-17 15:02:15 +01:00
|
|
|
T0 = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2005-07-05 00:17:05 +02:00
|
|
|
void do_mullwo (void)
|
|
|
|
{
|
2007-03-17 15:02:15 +01:00
|
|
|
int64_t res = (int64_t)T0 * (int64_t)T1;
|
2005-07-05 00:17:05 +02:00
|
|
|
|
|
|
|
if (likely((int32_t)res == res)) {
|
|
|
|
xer_ov = 0;
|
|
|
|
} else {
|
|
|
|
xer_ov = 1;
|
|
|
|
xer_so = 1;
|
|
|
|
}
|
|
|
|
T0 = (int32_t)res;
|
|
|
|
}
|
|
|
|
|
2007-03-17 15:02:15 +01:00
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
void do_mulldo (void)
|
2005-07-05 00:17:05 +02:00
|
|
|
{
|
2007-03-17 15:02:15 +01:00
|
|
|
int64_t th;
|
|
|
|
uint64_t tl;
|
|
|
|
|
|
|
|
do_imul64(&tl, &th);
|
|
|
|
if (likely(th == 0)) {
|
2005-07-05 00:17:05 +02:00
|
|
|
xer_ov = 0;
|
|
|
|
} else {
|
|
|
|
xer_ov = 1;
|
|
|
|
xer_so = 1;
|
|
|
|
}
|
2007-03-17 15:02:15 +01:00
|
|
|
T0 = (int64_t)tl;
|
2005-07-05 00:17:05 +02:00
|
|
|
}
|
2007-03-17 15:02:15 +01:00
|
|
|
#endif
|
2005-07-05 00:17:05 +02:00
|
|
|
|
2007-03-17 15:02:15 +01:00
|
|
|
void do_nego (void)
|
2005-07-05 00:17:05 +02:00
|
|
|
{
|
2007-03-17 15:02:15 +01:00
|
|
|
if (likely((int32_t)T0 != INT32_MIN)) {
|
2005-07-05 00:17:05 +02:00
|
|
|
xer_ov = 0;
|
2007-03-17 15:02:15 +01:00
|
|
|
T0 = -(int32_t)T0;
|
2005-07-05 00:17:05 +02:00
|
|
|
} else {
|
|
|
|
xer_ov = 1;
|
2007-03-17 15:02:15 +01:00
|
|
|
xer_so = 1;
|
2005-07-05 00:17:05 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-03-17 15:02:15 +01:00
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
void do_nego_64 (void)
|
2005-07-05 00:17:05 +02:00
|
|
|
{
|
2007-03-17 15:02:15 +01:00
|
|
|
if (likely((int64_t)T0 != INT64_MIN)) {
|
2005-07-05 00:17:05 +02:00
|
|
|
xer_ov = 0;
|
2007-03-17 15:02:15 +01:00
|
|
|
T0 = -(int64_t)T0;
|
2005-07-05 00:17:05 +02:00
|
|
|
} else {
|
|
|
|
xer_ov = 1;
|
2007-03-17 15:02:15 +01:00
|
|
|
xer_so = 1;
|
2005-07-05 00:17:05 +02:00
|
|
|
}
|
|
|
|
}
|
2007-03-17 15:02:15 +01:00
|
|
|
#endif
|
2005-07-05 00:17:05 +02:00
|
|
|
|
|
|
|
void do_subfe (void)
|
|
|
|
{
|
|
|
|
T0 = T1 + ~T0 + xer_ca;
|
2007-03-17 15:02:15 +01:00
|
|
|
if (likely((uint32_t)T0 >= (uint32_t)T1 &&
|
|
|
|
(xer_ca == 0 || (uint32_t)T0 != (uint32_t)T1))) {
|
2005-07-05 00:17:05 +02:00
|
|
|
xer_ca = 0;
|
|
|
|
} else {
|
|
|
|
xer_ca = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-03-17 15:02:15 +01:00
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
void do_subfe_64 (void)
|
2005-07-05 00:17:05 +02:00
|
|
|
{
|
|
|
|
T0 = T1 + ~T0 + xer_ca;
|
2007-03-17 15:02:15 +01:00
|
|
|
if (likely((uint64_t)T0 >= (uint64_t)T1 &&
|
|
|
|
(xer_ca == 0 || (uint64_t)T0 != (uint64_t)T1))) {
|
|
|
|
xer_ca = 0;
|
|
|
|
} else {
|
|
|
|
xer_ca = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
void do_subfmeo (void)
|
|
|
|
{
|
|
|
|
T1 = T0;
|
|
|
|
T0 = ~T0 + xer_ca - 1;
|
|
|
|
if (likely(!((uint32_t)~T1 & ((uint32_t)~T1 ^ (uint32_t)T0) &
|
|
|
|
(1UL << 31)))) {
|
2005-07-05 00:17:05 +02:00
|
|
|
xer_ov = 0;
|
|
|
|
} else {
|
|
|
|
xer_ov = 1;
|
2007-09-17 11:51:40 +02:00
|
|
|
xer_so = 1;
|
2005-07-05 00:17:05 +02:00
|
|
|
}
|
2007-03-17 15:02:15 +01:00
|
|
|
if (likely((uint32_t)T1 != UINT32_MAX))
|
2005-07-05 00:17:05 +02:00
|
|
|
xer_ca = 1;
|
|
|
|
}
|
|
|
|
|
2007-03-17 15:02:15 +01:00
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
void do_subfmeo_64 (void)
|
2005-07-05 00:17:05 +02:00
|
|
|
{
|
|
|
|
T1 = T0;
|
|
|
|
T0 = ~T0 + xer_ca - 1;
|
2007-03-17 15:02:15 +01:00
|
|
|
if (likely(!((uint64_t)~T1 & ((uint64_t)~T1 ^ (uint64_t)T0) &
|
|
|
|
(1ULL << 63)))) {
|
2005-07-05 00:17:05 +02:00
|
|
|
xer_ov = 0;
|
|
|
|
} else {
|
|
|
|
xer_ov = 1;
|
2007-09-17 11:51:40 +02:00
|
|
|
xer_so = 1;
|
2005-07-05 00:17:05 +02:00
|
|
|
}
|
2007-03-17 15:02:15 +01:00
|
|
|
if (likely((uint64_t)T1 != UINT64_MAX))
|
2005-07-05 00:17:05 +02:00
|
|
|
xer_ca = 1;
|
|
|
|
}
|
2007-03-17 15:02:15 +01:00
|
|
|
#endif
|
2005-07-05 00:17:05 +02:00
|
|
|
|
|
|
|
void do_subfzeo (void)
|
|
|
|
{
|
|
|
|
T1 = T0;
|
|
|
|
T0 = ~T0 + xer_ca;
|
2007-03-17 15:02:15 +01:00
|
|
|
if (likely(!(((uint32_t)~T1 ^ UINT32_MAX) &
|
|
|
|
((uint32_t)(~T1) ^ (uint32_t)T0) & (1UL << 31)))) {
|
2005-07-05 00:17:05 +02:00
|
|
|
xer_ov = 0;
|
|
|
|
} else {
|
|
|
|
xer_ov = 1;
|
|
|
|
xer_so = 1;
|
|
|
|
}
|
2007-03-17 15:02:15 +01:00
|
|
|
if (likely((uint32_t)T0 >= (uint32_t)~T1)) {
|
2005-07-05 00:17:05 +02:00
|
|
|
xer_ca = 0;
|
|
|
|
} else {
|
|
|
|
xer_ca = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-03-17 15:02:15 +01:00
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
void do_subfzeo_64 (void)
|
|
|
|
{
|
|
|
|
T1 = T0;
|
|
|
|
T0 = ~T0 + xer_ca;
|
|
|
|
if (likely(!(((uint64_t)~T1 ^ UINT64_MAX) &
|
|
|
|
((uint64_t)(~T1) ^ (uint64_t)T0) & (1ULL << 63)))) {
|
|
|
|
xer_ov = 0;
|
|
|
|
} else {
|
|
|
|
xer_ov = 1;
|
|
|
|
xer_so = 1;
|
|
|
|
}
|
|
|
|
if (likely((uint64_t)T0 >= (uint64_t)~T1)) {
|
|
|
|
xer_ca = 0;
|
|
|
|
} else {
|
|
|
|
xer_ca = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/* shift right arithmetic helper */
|
|
|
|
void do_sraw (void)
|
|
|
|
{
|
|
|
|
int32_t ret;
|
|
|
|
|
2005-07-05 00:17:05 +02:00
|
|
|
if (likely(!(T1 & 0x20UL))) {
|
2007-03-17 15:02:15 +01:00
|
|
|
if (likely((uint32_t)T1 != 0)) {
|
2005-07-05 00:17:05 +02:00
|
|
|
ret = (int32_t)T0 >> (T1 & 0x1fUL);
|
|
|
|
if (likely(ret >= 0 || ((int32_t)T0 & ((1 << T1) - 1)) == 0)) {
|
2007-03-07 09:32:30 +01:00
|
|
|
xer_ca = 0;
|
2005-07-05 00:17:05 +02:00
|
|
|
} else {
|
2007-03-07 09:32:30 +01:00
|
|
|
xer_ca = 1;
|
2005-07-05 00:17:05 +02:00
|
|
|
}
|
|
|
|
} else {
|
2007-03-07 09:32:30 +01:00
|
|
|
ret = T0;
|
2005-07-05 00:17:05 +02:00
|
|
|
xer_ca = 0;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
ret = (-1) * ((uint32_t)T0 >> 31);
|
|
|
|
if (likely(ret >= 0 || ((uint32_t)T0 & ~0x80000000UL) == 0)) {
|
|
|
|
xer_ca = 0;
|
2007-03-07 09:32:30 +01:00
|
|
|
} else {
|
2004-01-04 23:58:38 +01:00
|
|
|
xer_ca = 1;
|
2007-03-07 09:32:30 +01:00
|
|
|
}
|
2005-07-05 00:17:05 +02:00
|
|
|
}
|
2004-05-24 00:18:12 +02:00
|
|
|
T0 = ret;
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
2007-03-17 15:02:15 +01:00
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
void do_srad (void)
|
|
|
|
{
|
|
|
|
int64_t ret;
|
|
|
|
|
|
|
|
if (likely(!(T1 & 0x40UL))) {
|
|
|
|
if (likely((uint64_t)T1 != 0)) {
|
|
|
|
ret = (int64_t)T0 >> (T1 & 0x3FUL);
|
|
|
|
if (likely(ret >= 0 || ((int64_t)T0 & ((1 << T1) - 1)) == 0)) {
|
|
|
|
xer_ca = 0;
|
|
|
|
} else {
|
|
|
|
xer_ca = 1;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
ret = T0;
|
|
|
|
xer_ca = 0;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
ret = (-1) * ((uint64_t)T0 >> 63);
|
|
|
|
if (likely(ret >= 0 || ((uint64_t)T0 & ~0x8000000000000000ULL) == 0)) {
|
|
|
|
xer_ca = 0;
|
|
|
|
} else {
|
|
|
|
xer_ca = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
T0 = ret;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static inline int popcnt (uint32_t val)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; val != 0;)
|
|
|
|
val = val ^ (val - 1);
|
|
|
|
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_popcntb (void)
|
|
|
|
{
|
|
|
|
uint32_t ret;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
ret = 0;
|
|
|
|
for (i = 0; i < 32; i += 8)
|
|
|
|
ret |= popcnt((T0 >> i) & 0xFF) << i;
|
|
|
|
T0 = ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
void do_popcntb_64 (void)
|
|
|
|
{
|
|
|
|
uint64_t ret;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
ret = 0;
|
|
|
|
for (i = 0; i < 64; i += 8)
|
|
|
|
ret |= popcnt((T0 >> i) & 0xFF) << i;
|
|
|
|
T0 = ret;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2005-07-05 00:17:05 +02:00
|
|
|
/*****************************************************************************/
|
2004-01-04 23:58:38 +01:00
|
|
|
/* Floating point operations helpers */
|
|
|
|
void do_fctiw (void)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
double d;
|
|
|
|
uint64_t i;
|
2005-03-13 18:01:22 +01:00
|
|
|
} p;
|
2004-01-04 23:58:38 +01:00
|
|
|
|
2007-03-22 23:17:08 +01:00
|
|
|
p.i = float64_to_int32(FT0, &env->fp_status);
|
|
|
|
#if USE_PRECISE_EMULATION
|
2005-03-13 18:01:22 +01:00
|
|
|
/* XXX: higher bits are not supposed to be significant.
|
2007-03-07 09:32:30 +01:00
|
|
|
* to make tests easier, return the same as a real PowerPC 750 (aka G3)
|
2005-03-13 18:01:22 +01:00
|
|
|
*/
|
|
|
|
p.i |= 0xFFF80000ULL << 32;
|
2007-03-22 23:17:08 +01:00
|
|
|
#endif
|
2005-03-13 18:01:22 +01:00
|
|
|
FT0 = p.d;
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void do_fctiwz (void)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
double d;
|
|
|
|
uint64_t i;
|
2005-03-13 18:01:22 +01:00
|
|
|
} p;
|
|
|
|
|
2007-03-22 23:17:08 +01:00
|
|
|
p.i = float64_to_int32_round_to_zero(FT0, &env->fp_status);
|
|
|
|
#if USE_PRECISE_EMULATION
|
2005-03-13 18:01:22 +01:00
|
|
|
/* XXX: higher bits are not supposed to be significant.
|
2007-03-17 15:02:15 +01:00
|
|
|
* to make tests easier, return the same as a real PowerPC 750 (aka G3)
|
2005-03-13 18:01:22 +01:00
|
|
|
*/
|
|
|
|
p.i |= 0xFFF80000ULL << 32;
|
2007-03-22 23:17:08 +01:00
|
|
|
#endif
|
2005-03-13 18:01:22 +01:00
|
|
|
FT0 = p.d;
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
2007-03-23 10:45:27 +01:00
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
void do_fcfid (void)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
double d;
|
|
|
|
uint64_t i;
|
|
|
|
} p;
|
|
|
|
|
|
|
|
p.d = FT0;
|
|
|
|
FT0 = int64_to_float64(p.i, &env->fp_status);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_fctid (void)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
double d;
|
|
|
|
uint64_t i;
|
|
|
|
} p;
|
|
|
|
|
|
|
|
p.i = float64_to_int64(FT0, &env->fp_status);
|
|
|
|
FT0 = p.d;
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_fctidz (void)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
double d;
|
|
|
|
uint64_t i;
|
|
|
|
} p;
|
|
|
|
|
|
|
|
p.i = float64_to_int64_round_to_zero(FT0, &env->fp_status);
|
|
|
|
FT0 = p.d;
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
2007-09-30 03:11:48 +02:00
|
|
|
static inline void do_fri (int rounding_mode)
|
|
|
|
{
|
|
|
|
int curmode;
|
|
|
|
|
|
|
|
curmode = env->fp_status.float_rounding_mode;
|
|
|
|
set_float_rounding_mode(rounding_mode, &env->fp_status);
|
|
|
|
FT0 = float64_round_to_int(FT0, &env->fp_status);
|
|
|
|
set_float_rounding_mode(curmode, &env->fp_status);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_frin (void)
|
|
|
|
{
|
|
|
|
do_fri(float_round_nearest_even);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_friz (void)
|
|
|
|
{
|
|
|
|
do_fri(float_round_to_zero);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_frip (void)
|
|
|
|
{
|
|
|
|
do_fri(float_round_up);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_frim (void)
|
|
|
|
{
|
|
|
|
do_fri(float_round_down);
|
|
|
|
}
|
|
|
|
|
2007-03-22 23:17:08 +01:00
|
|
|
#if USE_PRECISE_EMULATION
|
|
|
|
void do_fmadd (void)
|
|
|
|
{
|
|
|
|
#ifdef FLOAT128
|
|
|
|
float128 ft0_128, ft1_128;
|
|
|
|
|
|
|
|
ft0_128 = float64_to_float128(FT0, &env->fp_status);
|
|
|
|
ft1_128 = float64_to_float128(FT1, &env->fp_status);
|
|
|
|
ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
|
|
|
|
ft1_128 = float64_to_float128(FT2, &env->fp_status);
|
|
|
|
ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
|
|
|
|
FT0 = float128_to_float64(ft0_128, &env->fp_status);
|
|
|
|
#else
|
|
|
|
/* This is OK on x86 hosts */
|
|
|
|
FT0 = (FT0 * FT1) + FT2;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_fmsub (void)
|
|
|
|
{
|
|
|
|
#ifdef FLOAT128
|
|
|
|
float128 ft0_128, ft1_128;
|
|
|
|
|
|
|
|
ft0_128 = float64_to_float128(FT0, &env->fp_status);
|
|
|
|
ft1_128 = float64_to_float128(FT1, &env->fp_status);
|
|
|
|
ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
|
|
|
|
ft1_128 = float64_to_float128(FT2, &env->fp_status);
|
|
|
|
ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
|
|
|
|
FT0 = float128_to_float64(ft0_128, &env->fp_status);
|
|
|
|
#else
|
|
|
|
/* This is OK on x86 hosts */
|
|
|
|
FT0 = (FT0 * FT1) - FT2;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
#endif /* USE_PRECISE_EMULATION */
|
|
|
|
|
2004-05-24 00:18:12 +02:00
|
|
|
void do_fnmadd (void)
|
|
|
|
{
|
2007-03-22 23:17:08 +01:00
|
|
|
#if USE_PRECISE_EMULATION
|
|
|
|
#ifdef FLOAT128
|
|
|
|
float128 ft0_128, ft1_128;
|
|
|
|
|
|
|
|
ft0_128 = float64_to_float128(FT0, &env->fp_status);
|
|
|
|
ft1_128 = float64_to_float128(FT1, &env->fp_status);
|
|
|
|
ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
|
|
|
|
ft1_128 = float64_to_float128(FT2, &env->fp_status);
|
|
|
|
ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
|
|
|
|
FT0 = float128_to_float64(ft0_128, &env->fp_status);
|
|
|
|
#else
|
|
|
|
/* This is OK on x86 hosts */
|
|
|
|
FT0 = (FT0 * FT1) + FT2;
|
|
|
|
#endif
|
|
|
|
#else
|
2005-07-05 00:17:05 +02:00
|
|
|
FT0 = float64_mul(FT0, FT1, &env->fp_status);
|
|
|
|
FT0 = float64_add(FT0, FT2, &env->fp_status);
|
2007-03-22 23:17:08 +01:00
|
|
|
#endif
|
2005-07-05 00:17:05 +02:00
|
|
|
if (likely(!isnan(FT0)))
|
|
|
|
FT0 = float64_chs(FT0);
|
2004-05-24 00:18:12 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void do_fnmsub (void)
|
|
|
|
{
|
2007-03-22 23:17:08 +01:00
|
|
|
#if USE_PRECISE_EMULATION
|
|
|
|
#ifdef FLOAT128
|
|
|
|
float128 ft0_128, ft1_128;
|
|
|
|
|
|
|
|
ft0_128 = float64_to_float128(FT0, &env->fp_status);
|
|
|
|
ft1_128 = float64_to_float128(FT1, &env->fp_status);
|
|
|
|
ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
|
|
|
|
ft1_128 = float64_to_float128(FT2, &env->fp_status);
|
|
|
|
ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
|
|
|
|
FT0 = float128_to_float64(ft0_128, &env->fp_status);
|
|
|
|
#else
|
|
|
|
/* This is OK on x86 hosts */
|
|
|
|
FT0 = (FT0 * FT1) - FT2;
|
|
|
|
#endif
|
|
|
|
#else
|
2005-07-05 00:17:05 +02:00
|
|
|
FT0 = float64_mul(FT0, FT1, &env->fp_status);
|
|
|
|
FT0 = float64_sub(FT0, FT2, &env->fp_status);
|
2007-03-22 23:17:08 +01:00
|
|
|
#endif
|
2005-07-05 00:17:05 +02:00
|
|
|
if (likely(!isnan(FT0)))
|
|
|
|
FT0 = float64_chs(FT0);
|
2004-04-26 21:48:05 +02:00
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
void do_fsqrt (void)
|
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
FT0 = float64_sqrt(FT0, &env->fp_status);
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
2007-09-30 03:11:48 +02:00
|
|
|
void do_fre (void)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
double d;
|
|
|
|
uint64_t i;
|
|
|
|
} p;
|
|
|
|
|
|
|
|
if (likely(isnormal(FT0))) {
|
|
|
|
FT0 = float64_div(1.0, FT0, &env->fp_status);
|
|
|
|
} else {
|
|
|
|
p.d = FT0;
|
|
|
|
if (p.i == 0x8000000000000000ULL) {
|
|
|
|
p.i = 0xFFF0000000000000ULL;
|
|
|
|
} else if (p.i == 0x0000000000000000ULL) {
|
|
|
|
p.i = 0x7FF0000000000000ULL;
|
|
|
|
} else if (isnan(FT0)) {
|
|
|
|
p.i = 0x7FF8000000000000ULL;
|
|
|
|
} else if (FT0 < 0.0) {
|
|
|
|
p.i = 0x8000000000000000ULL;
|
|
|
|
} else {
|
|
|
|
p.i = 0x0000000000000000ULL;
|
|
|
|
}
|
|
|
|
FT0 = p.d;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
void do_fres (void)
|
|
|
|
{
|
2005-03-13 18:01:22 +01:00
|
|
|
union {
|
|
|
|
double d;
|
|
|
|
uint64_t i;
|
|
|
|
} p;
|
|
|
|
|
2005-07-05 00:17:05 +02:00
|
|
|
if (likely(isnormal(FT0))) {
|
2007-03-22 23:17:08 +01:00
|
|
|
#if USE_PRECISE_EMULATION
|
|
|
|
FT0 = float64_div(1.0, FT0, &env->fp_status);
|
|
|
|
FT0 = float64_to_float32(FT0, &env->fp_status);
|
|
|
|
#else
|
2007-03-07 09:32:30 +01:00
|
|
|
FT0 = float32_div(1.0, FT0, &env->fp_status);
|
2007-03-22 23:17:08 +01:00
|
|
|
#endif
|
2005-03-13 18:01:22 +01:00
|
|
|
} else {
|
|
|
|
p.d = FT0;
|
|
|
|
if (p.i == 0x8000000000000000ULL) {
|
|
|
|
p.i = 0xFFF0000000000000ULL;
|
|
|
|
} else if (p.i == 0x0000000000000000ULL) {
|
|
|
|
p.i = 0x7FF0000000000000ULL;
|
|
|
|
} else if (isnan(FT0)) {
|
|
|
|
p.i = 0x7FF8000000000000ULL;
|
|
|
|
} else if (FT0 < 0.0) {
|
|
|
|
p.i = 0x8000000000000000ULL;
|
|
|
|
} else {
|
|
|
|
p.i = 0x0000000000000000ULL;
|
|
|
|
}
|
|
|
|
FT0 = p.d;
|
|
|
|
}
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
2005-03-13 18:01:22 +01:00
|
|
|
void do_frsqrte (void)
|
2004-01-04 23:58:38 +01:00
|
|
|
{
|
2005-03-13 18:01:22 +01:00
|
|
|
union {
|
|
|
|
double d;
|
|
|
|
uint64_t i;
|
|
|
|
} p;
|
|
|
|
|
2005-07-05 00:17:05 +02:00
|
|
|
if (likely(isnormal(FT0) && FT0 > 0.0)) {
|
|
|
|
FT0 = float64_sqrt(FT0, &env->fp_status);
|
|
|
|
FT0 = float32_div(1.0, FT0, &env->fp_status);
|
2005-03-13 18:01:22 +01:00
|
|
|
} else {
|
|
|
|
p.d = FT0;
|
|
|
|
if (p.i == 0x8000000000000000ULL) {
|
|
|
|
p.i = 0xFFF0000000000000ULL;
|
|
|
|
} else if (p.i == 0x0000000000000000ULL) {
|
|
|
|
p.i = 0x7FF0000000000000ULL;
|
|
|
|
} else if (isnan(FT0)) {
|
|
|
|
if (!(p.i & 0x0008000000000000ULL))
|
|
|
|
p.i |= 0x000FFFFFFFFFFFFFULL;
|
|
|
|
} else if (FT0 < 0) {
|
|
|
|
p.i = 0x7FF8000000000000ULL;
|
|
|
|
} else {
|
|
|
|
p.i = 0x0000000000000000ULL;
|
|
|
|
}
|
|
|
|
FT0 = p.d;
|
|
|
|
}
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void do_fsel (void)
|
|
|
|
{
|
|
|
|
if (FT0 >= 0)
|
|
|
|
FT0 = FT1;
|
2005-03-13 18:01:22 +01:00
|
|
|
else
|
|
|
|
FT0 = FT2;
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void do_fcmpu (void)
|
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
if (likely(!isnan(FT0) && !isnan(FT1))) {
|
|
|
|
if (float64_lt(FT0, FT1, &env->fp_status)) {
|
|
|
|
T0 = 0x08UL;
|
|
|
|
} else if (!float64_le(FT0, FT1, &env->fp_status)) {
|
|
|
|
T0 = 0x04UL;
|
|
|
|
} else {
|
|
|
|
T0 = 0x02UL;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
T0 = 0x01UL;
|
2004-01-04 23:58:38 +01:00
|
|
|
env->fpscr[4] |= 0x1;
|
|
|
|
env->fpscr[6] |= 0x1;
|
|
|
|
}
|
2004-05-24 00:18:12 +02:00
|
|
|
env->fpscr[3] = T0;
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void do_fcmpo (void)
|
|
|
|
{
|
|
|
|
env->fpscr[4] &= ~0x1;
|
2005-07-05 00:17:05 +02:00
|
|
|
if (likely(!isnan(FT0) && !isnan(FT1))) {
|
|
|
|
if (float64_lt(FT0, FT1, &env->fp_status)) {
|
|
|
|
T0 = 0x08UL;
|
|
|
|
} else if (!float64_le(FT0, FT1, &env->fp_status)) {
|
|
|
|
T0 = 0x04UL;
|
|
|
|
} else {
|
|
|
|
T0 = 0x02UL;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
T0 = 0x01UL;
|
2004-01-04 23:58:38 +01:00
|
|
|
env->fpscr[4] |= 0x1;
|
2007-03-07 09:32:30 +01:00
|
|
|
if (!float64_is_signaling_nan(FT0) || !float64_is_signaling_nan(FT1)) {
|
|
|
|
/* Quiet NaN case */
|
2004-01-04 23:58:38 +01:00
|
|
|
env->fpscr[6] |= 0x1;
|
|
|
|
if (!(env->fpscr[1] & 0x8))
|
|
|
|
env->fpscr[4] |= 0x8;
|
|
|
|
} else {
|
|
|
|
env->fpscr[4] |= 0x8;
|
|
|
|
}
|
|
|
|
}
|
2004-05-24 00:18:12 +02:00
|
|
|
env->fpscr[3] = T0;
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
#if !defined (CONFIG_USER_ONLY)
|
2007-04-24 09:36:03 +02:00
|
|
|
void cpu_dump_rfi (target_ulong RA, target_ulong msr);
|
2005-07-05 00:17:05 +02:00
|
|
|
void do_rfi (void)
|
2004-01-04 23:58:38 +01:00
|
|
|
{
|
2007-03-23 10:45:27 +01:00
|
|
|
#if defined(TARGET_PPC64)
|
2007-03-30 12:22:46 +02:00
|
|
|
if (env->spr[SPR_SRR1] & (1ULL << MSR_SF)) {
|
|
|
|
env->nip = (uint64_t)(env->spr[SPR_SRR0] & ~0x00000003);
|
|
|
|
do_store_msr(env, (uint64_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
|
|
|
|
} else {
|
|
|
|
env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003);
|
|
|
|
ppc_store_msr_32(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
|
|
|
|
}
|
2007-03-23 10:45:27 +01:00
|
|
|
#else
|
2007-03-30 12:22:46 +02:00
|
|
|
env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003);
|
|
|
|
do_store_msr(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
|
2007-03-23 10:45:27 +01:00
|
|
|
#endif
|
2005-07-05 00:17:05 +02:00
|
|
|
#if defined (DEBUG_OP)
|
2007-04-24 09:36:03 +02:00
|
|
|
cpu_dump_rfi(env->nip, do_load_msr(env));
|
2005-07-05 00:17:05 +02:00
|
|
|
#endif
|
|
|
|
env->interrupt_request |= CPU_INTERRUPT_EXITTB;
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
2007-03-17 15:02:15 +01:00
|
|
|
|
|
|
|
#if defined(TARGET_PPC64)
|
2007-03-23 10:45:27 +01:00
|
|
|
void do_rfid (void)
|
|
|
|
{
|
2007-03-30 12:22:46 +02:00
|
|
|
if (env->spr[SPR_SRR1] & (1ULL << MSR_SF)) {
|
|
|
|
env->nip = (uint64_t)(env->spr[SPR_SRR0] & ~0x00000003);
|
|
|
|
do_store_msr(env, (uint64_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
|
|
|
|
} else {
|
|
|
|
env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003);
|
|
|
|
do_store_msr(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
|
|
|
|
}
|
2007-03-17 15:02:15 +01:00
|
|
|
#if defined (DEBUG_OP)
|
2007-04-24 09:36:03 +02:00
|
|
|
cpu_dump_rfi(env->nip, do_load_msr(env));
|
2007-03-17 15:02:15 +01:00
|
|
|
#endif
|
|
|
|
env->interrupt_request |= CPU_INTERRUPT_EXITTB;
|
|
|
|
}
|
|
|
|
#endif
|
2007-03-07 09:32:30 +01:00
|
|
|
#endif
|
2004-01-04 23:58:38 +01:00
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
void do_tw (int flags)
|
2004-01-04 23:58:38 +01:00
|
|
|
{
|
2007-03-17 15:02:15 +01:00
|
|
|
if (!likely(!(((int32_t)T0 < (int32_t)T1 && (flags & 0x10)) ||
|
|
|
|
((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) ||
|
|
|
|
((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) ||
|
|
|
|
((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) ||
|
2007-03-30 12:22:46 +02:00
|
|
|
((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) {
|
2007-09-29 15:06:16 +02:00
|
|
|
do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
|
2007-03-30 12:22:46 +02:00
|
|
|
}
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
2007-03-17 15:02:15 +01:00
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
void do_td (int flags)
|
|
|
|
{
|
|
|
|
if (!likely(!(((int64_t)T0 < (int64_t)T1 && (flags & 0x10)) ||
|
|
|
|
((int64_t)T0 > (int64_t)T1 && (flags & 0x08)) ||
|
|
|
|
((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) ||
|
|
|
|
((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) ||
|
|
|
|
((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01)))))
|
2007-09-29 15:06:16 +02:00
|
|
|
do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
|
2007-03-17 15:02:15 +01:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2005-07-05 00:17:05 +02:00
|
|
|
/*****************************************************************************/
|
2007-03-07 09:32:30 +01:00
|
|
|
/* PowerPC 601 specific instructions (POWER bridge) */
|
|
|
|
void do_POWER_abso (void)
|
2004-01-04 23:58:38 +01:00
|
|
|
{
|
2007-03-17 15:02:15 +01:00
|
|
|
if ((uint32_t)T0 == INT32_MIN) {
|
2007-03-07 09:32:30 +01:00
|
|
|
T0 = INT32_MAX;
|
|
|
|
xer_ov = 1;
|
|
|
|
xer_so = 1;
|
|
|
|
} else {
|
|
|
|
T0 = -T0;
|
|
|
|
xer_ov = 0;
|
|
|
|
}
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
void do_POWER_clcs (void)
|
2004-01-04 23:58:38 +01:00
|
|
|
{
|
2007-03-07 09:32:30 +01:00
|
|
|
switch (T0) {
|
|
|
|
case 0x0CUL:
|
|
|
|
/* Instruction cache line size */
|
|
|
|
T0 = ICACHE_LINE_SIZE;
|
|
|
|
break;
|
|
|
|
case 0x0DUL:
|
|
|
|
/* Data cache line size */
|
|
|
|
T0 = DCACHE_LINE_SIZE;
|
|
|
|
break;
|
|
|
|
case 0x0EUL:
|
|
|
|
/* Minimum cache line size */
|
|
|
|
T0 = ICACHE_LINE_SIZE < DCACHE_LINE_SIZE ?
|
|
|
|
ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
|
|
|
|
break;
|
|
|
|
case 0x0FUL:
|
|
|
|
/* Maximum cache line size */
|
|
|
|
T0 = ICACHE_LINE_SIZE > DCACHE_LINE_SIZE ?
|
|
|
|
ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* Undefined */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_POWER_div (void)
|
|
|
|
{
|
|
|
|
uint64_t tmp;
|
|
|
|
|
2007-03-17 15:02:15 +01:00
|
|
|
if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
|
2007-03-07 09:32:30 +01:00
|
|
|
T0 = (long)((-1) * (T0 >> 31));
|
|
|
|
env->spr[SPR_MQ] = 0;
|
|
|
|
} else {
|
|
|
|
tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
|
|
|
|
env->spr[SPR_MQ] = tmp % T1;
|
2007-03-17 15:02:15 +01:00
|
|
|
T0 = tmp / (int32_t)T1;
|
2007-03-07 09:32:30 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_POWER_divo (void)
|
|
|
|
{
|
|
|
|
int64_t tmp;
|
|
|
|
|
2007-03-17 15:02:15 +01:00
|
|
|
if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
|
2007-03-07 09:32:30 +01:00
|
|
|
T0 = (long)((-1) * (T0 >> 31));
|
|
|
|
env->spr[SPR_MQ] = 0;
|
|
|
|
xer_ov = 1;
|
|
|
|
xer_so = 1;
|
|
|
|
} else {
|
|
|
|
tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
|
|
|
|
env->spr[SPR_MQ] = tmp % T1;
|
2007-03-17 15:02:15 +01:00
|
|
|
tmp /= (int32_t)T1;
|
2007-03-07 09:32:30 +01:00
|
|
|
if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
|
|
|
|
xer_ov = 1;
|
|
|
|
xer_so = 1;
|
|
|
|
} else {
|
|
|
|
xer_ov = 0;
|
|
|
|
}
|
|
|
|
T0 = tmp;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_POWER_divs (void)
|
|
|
|
{
|
2007-03-17 15:02:15 +01:00
|
|
|
if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
|
2007-03-07 09:32:30 +01:00
|
|
|
T0 = (long)((-1) * (T0 >> 31));
|
|
|
|
env->spr[SPR_MQ] = 0;
|
|
|
|
} else {
|
|
|
|
env->spr[SPR_MQ] = T0 % T1;
|
2007-03-17 15:02:15 +01:00
|
|
|
T0 = (int32_t)T0 / (int32_t)T1;
|
2007-03-07 09:32:30 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_POWER_divso (void)
|
|
|
|
{
|
2007-03-17 15:02:15 +01:00
|
|
|
if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
|
2007-03-07 09:32:30 +01:00
|
|
|
T0 = (long)((-1) * (T0 >> 31));
|
|
|
|
env->spr[SPR_MQ] = 0;
|
|
|
|
xer_ov = 1;
|
|
|
|
xer_so = 1;
|
|
|
|
} else {
|
2007-03-17 15:02:15 +01:00
|
|
|
T0 = (int32_t)T0 / (int32_t)T1;
|
|
|
|
env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
|
2007-03-07 09:32:30 +01:00
|
|
|
xer_ov = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_POWER_dozo (void)
|
|
|
|
{
|
2007-03-17 15:02:15 +01:00
|
|
|
if ((int32_t)T1 > (int32_t)T0) {
|
2007-03-07 09:32:30 +01:00
|
|
|
T2 = T0;
|
|
|
|
T0 = T1 - T0;
|
2007-03-17 15:02:15 +01:00
|
|
|
if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
|
|
|
|
((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
|
2007-03-07 09:32:30 +01:00
|
|
|
xer_ov = 1;
|
2007-09-17 11:51:40 +02:00
|
|
|
xer_so = 1;
|
2007-03-07 09:32:30 +01:00
|
|
|
} else {
|
|
|
|
xer_ov = 0;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
T0 = 0;
|
|
|
|
xer_ov = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_POWER_maskg (void)
|
|
|
|
{
|
|
|
|
uint32_t ret;
|
|
|
|
|
2007-03-17 15:02:15 +01:00
|
|
|
if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
|
2007-03-07 09:32:30 +01:00
|
|
|
ret = -1;
|
|
|
|
} else {
|
2007-03-17 15:02:15 +01:00
|
|
|
ret = (((uint32_t)(-1)) >> ((uint32_t)T0)) ^
|
|
|
|
(((uint32_t)(-1) >> ((uint32_t)T1)) >> 1);
|
|
|
|
if ((uint32_t)T0 > (uint32_t)T1)
|
2007-03-07 09:32:30 +01:00
|
|
|
ret = ~ret;
|
|
|
|
}
|
|
|
|
T0 = ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_POWER_mulo (void)
|
|
|
|
{
|
|
|
|
uint64_t tmp;
|
|
|
|
|
|
|
|
tmp = (uint64_t)T0 * (uint64_t)T1;
|
|
|
|
env->spr[SPR_MQ] = tmp >> 32;
|
|
|
|
T0 = tmp;
|
|
|
|
if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
|
|
|
|
xer_ov = 1;
|
|
|
|
xer_so = 1;
|
|
|
|
} else {
|
|
|
|
xer_ov = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#if !defined (CONFIG_USER_ONLY)
|
|
|
|
void do_POWER_rac (void)
|
|
|
|
{
|
|
|
|
#if 0
|
|
|
|
mmu_ctx_t ctx;
|
|
|
|
|
|
|
|
/* We don't have to generate many instances of this instruction,
|
|
|
|
* as rac is supervisor only.
|
|
|
|
*/
|
|
|
|
if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT, 1) == 0)
|
|
|
|
T0 = ctx.raddr;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_POWER_rfsvc (void)
|
|
|
|
{
|
|
|
|
env->nip = env->lr & ~0x00000003UL;
|
|
|
|
T0 = env->ctr & 0x0000FFFFUL;
|
|
|
|
do_store_msr(env, T0);
|
|
|
|
#if defined (DEBUG_OP)
|
2007-04-24 09:36:03 +02:00
|
|
|
cpu_dump_rfi(env->nip, do_load_msr(env));
|
2007-03-07 09:32:30 +01:00
|
|
|
#endif
|
|
|
|
env->interrupt_request |= CPU_INTERRUPT_EXITTB;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* PowerPC 601 BAT management helper */
|
|
|
|
void do_store_601_batu (int nr)
|
|
|
|
{
|
2007-03-17 15:02:15 +01:00
|
|
|
do_store_ibatu(env, nr, (uint32_t)T0);
|
2007-03-07 09:32:30 +01:00
|
|
|
env->DBAT[0][nr] = env->IBAT[0][nr];
|
|
|
|
env->DBAT[1][nr] = env->IBAT[1][nr];
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/*****************************************************************************/
|
|
|
|
/* 602 specific instructions */
|
|
|
|
/* mfrom is the most crazy instruction ever seen, imho ! */
|
|
|
|
/* Real implementation uses a ROM table. Do the same */
|
|
|
|
#define USE_MFROM_ROM_TABLE
|
|
|
|
void do_op_602_mfrom (void)
|
|
|
|
{
|
|
|
|
if (likely(T0 < 602)) {
|
2007-03-17 15:02:15 +01:00
|
|
|
#if defined(USE_MFROM_ROM_TABLE)
|
2007-03-07 09:32:30 +01:00
|
|
|
#include "mfrom_table.c"
|
|
|
|
T0 = mfrom_ROM_table[T0];
|
2005-07-05 00:17:05 +02:00
|
|
|
#else
|
2007-03-07 09:32:30 +01:00
|
|
|
double d;
|
|
|
|
/* Extremly decomposed:
|
|
|
|
* -T0 / 256
|
|
|
|
* T0 = 256 * log10(10 + 1.0) + 0.5
|
|
|
|
*/
|
|
|
|
d = T0;
|
|
|
|
d = float64_div(d, 256, &env->fp_status);
|
|
|
|
d = float64_chs(d);
|
|
|
|
d = exp10(d); // XXX: use float emulation function
|
|
|
|
d = float64_add(d, 1.0, &env->fp_status);
|
|
|
|
d = log10(d); // XXX: use float emulation function
|
|
|
|
d = float64_mul(d, 256, &env->fp_status);
|
|
|
|
d = float64_add(d, 0.5, &env->fp_status);
|
|
|
|
T0 = float64_round_to_int(d, &env->fp_status);
|
2005-07-05 00:17:05 +02:00
|
|
|
#endif
|
2007-03-07 09:32:30 +01:00
|
|
|
} else {
|
|
|
|
T0 = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*****************************************************************************/
|
|
|
|
/* Embedded PowerPC specific helpers */
|
|
|
|
void do_405_check_ov (void)
|
|
|
|
{
|
2007-03-17 15:02:15 +01:00
|
|
|
if (likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
|
|
|
|
!(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
|
2007-03-07 09:32:30 +01:00
|
|
|
xer_ov = 0;
|
|
|
|
} else {
|
|
|
|
xer_ov = 1;
|
|
|
|
xer_so = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_405_check_sat (void)
|
|
|
|
{
|
2007-03-17 15:02:15 +01:00
|
|
|
if (!likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
|
|
|
|
!(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
|
2007-03-07 09:32:30 +01:00
|
|
|
/* Saturate result */
|
|
|
|
if (T2 >> 31) {
|
|
|
|
T0 = INT32_MIN;
|
|
|
|
} else {
|
|
|
|
T0 = INT32_MAX;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* XXX: to be improved to check access rights when in user-mode */
|
|
|
|
void do_load_dcr (void)
|
|
|
|
{
|
|
|
|
target_ulong val;
|
|
|
|
|
|
|
|
if (unlikely(env->dcr_env == NULL)) {
|
|
|
|
if (loglevel != 0) {
|
|
|
|
fprintf(logfile, "No DCR environment\n");
|
|
|
|
}
|
2007-09-29 15:06:16 +02:00
|
|
|
do_raise_exception_err(POWERPC_EXCP_PROGRAM,
|
|
|
|
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
} else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
|
|
|
|
if (loglevel != 0) {
|
|
|
|
fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
|
|
|
|
}
|
2007-09-29 15:06:16 +02:00
|
|
|
do_raise_exception_err(POWERPC_EXCP_PROGRAM,
|
|
|
|
POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
} else {
|
|
|
|
T0 = val;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_store_dcr (void)
|
|
|
|
{
|
|
|
|
if (unlikely(env->dcr_env == NULL)) {
|
|
|
|
if (loglevel != 0) {
|
|
|
|
fprintf(logfile, "No DCR environment\n");
|
|
|
|
}
|
2007-09-29 15:06:16 +02:00
|
|
|
do_raise_exception_err(POWERPC_EXCP_PROGRAM,
|
|
|
|
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
} else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
|
|
|
|
if (loglevel != 0) {
|
|
|
|
fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
|
|
|
|
}
|
2007-09-29 15:06:16 +02:00
|
|
|
do_raise_exception_err(POWERPC_EXCP_PROGRAM,
|
|
|
|
POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2007-03-30 12:22:46 +02:00
|
|
|
void do_40x_rfci (void)
|
2007-03-07 09:32:30 +01:00
|
|
|
{
|
|
|
|
env->nip = env->spr[SPR_40x_SRR2];
|
2007-03-30 12:22:46 +02:00
|
|
|
do_store_msr(env, env->spr[SPR_40x_SRR3] & ~0xFFFF0000);
|
|
|
|
#if defined (DEBUG_OP)
|
2007-04-24 09:36:03 +02:00
|
|
|
cpu_dump_rfi(env->nip, do_load_msr(env));
|
2007-03-30 12:22:46 +02:00
|
|
|
#endif
|
|
|
|
env->interrupt_request = CPU_INTERRUPT_EXITTB;
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_rfci (void)
|
|
|
|
{
|
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
if (env->spr[SPR_BOOKE_CSRR1] & (1 << MSR_CM)) {
|
|
|
|
env->nip = (uint64_t)env->spr[SPR_BOOKE_CSRR0];
|
|
|
|
} else
|
|
|
|
#endif
|
|
|
|
{
|
|
|
|
env->nip = (uint32_t)env->spr[SPR_BOOKE_CSRR0];
|
|
|
|
}
|
|
|
|
do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_CSRR1] & ~0x3FFF0000);
|
|
|
|
#if defined (DEBUG_OP)
|
2007-04-24 09:36:03 +02:00
|
|
|
cpu_dump_rfi(env->nip, do_load_msr(env));
|
2007-03-30 12:22:46 +02:00
|
|
|
#endif
|
|
|
|
env->interrupt_request = CPU_INTERRUPT_EXITTB;
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_rfdi (void)
|
|
|
|
{
|
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
if (env->spr[SPR_BOOKE_DSRR1] & (1 << MSR_CM)) {
|
|
|
|
env->nip = (uint64_t)env->spr[SPR_BOOKE_DSRR0];
|
|
|
|
} else
|
|
|
|
#endif
|
|
|
|
{
|
|
|
|
env->nip = (uint32_t)env->spr[SPR_BOOKE_DSRR0];
|
|
|
|
}
|
|
|
|
do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_DSRR1] & ~0x3FFF0000);
|
|
|
|
#if defined (DEBUG_OP)
|
2007-04-24 09:36:03 +02:00
|
|
|
cpu_dump_rfi(env->nip, do_load_msr(env));
|
2007-03-30 12:22:46 +02:00
|
|
|
#endif
|
|
|
|
env->interrupt_request = CPU_INTERRUPT_EXITTB;
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_rfmci (void)
|
|
|
|
{
|
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
if (env->spr[SPR_BOOKE_MCSRR1] & (1 << MSR_CM)) {
|
|
|
|
env->nip = (uint64_t)env->spr[SPR_BOOKE_MCSRR0];
|
|
|
|
} else
|
|
|
|
#endif
|
|
|
|
{
|
|
|
|
env->nip = (uint32_t)env->spr[SPR_BOOKE_MCSRR0];
|
|
|
|
}
|
|
|
|
do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_MCSRR1] & ~0x3FFF0000);
|
2007-03-07 09:32:30 +01:00
|
|
|
#if defined (DEBUG_OP)
|
2007-04-24 09:36:03 +02:00
|
|
|
cpu_dump_rfi(env->nip, do_load_msr(env));
|
2007-03-07 09:32:30 +01:00
|
|
|
#endif
|
|
|
|
env->interrupt_request = CPU_INTERRUPT_EXITTB;
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_load_403_pb (int num)
|
|
|
|
{
|
|
|
|
T0 = env->pb[num];
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_store_403_pb (int num)
|
|
|
|
{
|
|
|
|
if (likely(env->pb[num] != T0)) {
|
|
|
|
env->pb[num] = T0;
|
|
|
|
/* Should be optimized */
|
|
|
|
tlb_flush(env, 1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* 440 specific */
|
|
|
|
void do_440_dlmzb (void)
|
|
|
|
{
|
|
|
|
target_ulong mask;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
i = 1;
|
|
|
|
for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
|
|
|
|
if ((T0 & mask) == 0)
|
|
|
|
goto done;
|
|
|
|
i++;
|
|
|
|
}
|
|
|
|
for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
|
|
|
|
if ((T1 & mask) == 0)
|
|
|
|
break;
|
|
|
|
i++;
|
|
|
|
}
|
|
|
|
done:
|
|
|
|
T0 = i;
|
2005-07-05 00:17:05 +02:00
|
|
|
}
|
|
|
|
|
2007-04-24 08:50:21 +02:00
|
|
|
#if defined(TARGET_PPCEMB)
|
2007-03-20 23:11:31 +01:00
|
|
|
/* SPE extension helpers */
|
|
|
|
/* Use a table to make this quicker */
|
|
|
|
static uint8_t hbrev[16] = {
|
|
|
|
0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
|
|
|
|
0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
|
|
|
|
};
|
|
|
|
|
|
|
|
static inline uint8_t byte_reverse (uint8_t val)
|
|
|
|
{
|
|
|
|
return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint32_t word_reverse (uint32_t val)
|
|
|
|
{
|
|
|
|
return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
|
|
|
|
(byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MASKBITS 16 // Random value - to be fixed
|
|
|
|
void do_brinc (void)
|
|
|
|
{
|
|
|
|
uint32_t a, b, d, mask;
|
|
|
|
|
|
|
|
mask = (uint32_t)(-1UL) >> MASKBITS;
|
|
|
|
b = T1_64 & mask;
|
|
|
|
a = T0_64 & mask;
|
|
|
|
d = word_reverse(1 + word_reverse(a | ~mask));
|
|
|
|
T0_64 = (T0_64 & ~mask) | (d & mask);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define DO_SPE_OP2(name) \
|
|
|
|
void do_ev##name (void) \
|
|
|
|
{ \
|
|
|
|
T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) | \
|
|
|
|
(uint64_t)_do_e##name(T0_64, T1_64); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define DO_SPE_OP1(name) \
|
|
|
|
void do_ev##name (void) \
|
|
|
|
{ \
|
|
|
|
T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) | \
|
|
|
|
(uint64_t)_do_e##name(T0_64); \
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Fixed-point vector arithmetic */
|
|
|
|
static inline uint32_t _do_eabs (uint32_t val)
|
|
|
|
{
|
|
|
|
if (val != 0x80000000)
|
|
|
|
val &= ~0x80000000;
|
|
|
|
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint32_t _do_eaddw (uint32_t op1, uint32_t op2)
|
|
|
|
{
|
|
|
|
return op1 + op2;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int _do_ecntlsw (uint32_t val)
|
|
|
|
{
|
|
|
|
if (val & 0x80000000)
|
|
|
|
return _do_cntlzw(~val);
|
|
|
|
else
|
|
|
|
return _do_cntlzw(val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int _do_ecntlzw (uint32_t val)
|
|
|
|
{
|
|
|
|
return _do_cntlzw(val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint32_t _do_eneg (uint32_t val)
|
|
|
|
{
|
|
|
|
if (val != 0x80000000)
|
|
|
|
val ^= 0x80000000;
|
|
|
|
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint32_t _do_erlw (uint32_t op1, uint32_t op2)
|
|
|
|
{
|
|
|
|
return rotl32(op1, op2);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint32_t _do_erndw (uint32_t val)
|
|
|
|
{
|
|
|
|
return (val + 0x000080000000) & 0xFFFF0000;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint32_t _do_eslw (uint32_t op1, uint32_t op2)
|
|
|
|
{
|
|
|
|
/* No error here: 6 bits are used */
|
|
|
|
return op1 << (op2 & 0x3F);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int32_t _do_esrws (int32_t op1, uint32_t op2)
|
|
|
|
{
|
|
|
|
/* No error here: 6 bits are used */
|
|
|
|
return op1 >> (op2 & 0x3F);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint32_t _do_esrwu (uint32_t op1, uint32_t op2)
|
|
|
|
{
|
|
|
|
/* No error here: 6 bits are used */
|
|
|
|
return op1 >> (op2 & 0x3F);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint32_t _do_esubfw (uint32_t op1, uint32_t op2)
|
|
|
|
{
|
|
|
|
return op2 - op1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* evabs */
|
|
|
|
DO_SPE_OP1(abs);
|
|
|
|
/* evaddw */
|
|
|
|
DO_SPE_OP2(addw);
|
|
|
|
/* evcntlsw */
|
|
|
|
DO_SPE_OP1(cntlsw);
|
|
|
|
/* evcntlzw */
|
|
|
|
DO_SPE_OP1(cntlzw);
|
|
|
|
/* evneg */
|
|
|
|
DO_SPE_OP1(neg);
|
|
|
|
/* evrlw */
|
|
|
|
DO_SPE_OP2(rlw);
|
|
|
|
/* evrnd */
|
|
|
|
DO_SPE_OP1(rndw);
|
|
|
|
/* evslw */
|
|
|
|
DO_SPE_OP2(slw);
|
|
|
|
/* evsrws */
|
|
|
|
DO_SPE_OP2(srws);
|
|
|
|
/* evsrwu */
|
|
|
|
DO_SPE_OP2(srwu);
|
|
|
|
/* evsubfw */
|
|
|
|
DO_SPE_OP2(subfw);
|
|
|
|
|
|
|
|
/* evsel is a little bit more complicated... */
|
|
|
|
static inline uint32_t _do_esel (uint32_t op1, uint32_t op2, int n)
|
|
|
|
{
|
|
|
|
if (n)
|
|
|
|
return op1;
|
|
|
|
else
|
|
|
|
return op2;
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_evsel (void)
|
|
|
|
{
|
|
|
|
T0_64 = ((uint64_t)_do_esel(T0_64 >> 32, T1_64 >> 32, T0 >> 3) << 32) |
|
|
|
|
(uint64_t)_do_esel(T0_64, T1_64, (T0 >> 2) & 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Fixed-point vector comparisons */
|
|
|
|
#define DO_SPE_CMP(name) \
|
|
|
|
void do_ev##name (void) \
|
|
|
|
{ \
|
|
|
|
T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32, \
|
|
|
|
T1_64 >> 32) << 32, \
|
|
|
|
_do_e##name(T0_64, T1_64)); \
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint32_t _do_evcmp_merge (int t0, int t1)
|
|
|
|
{
|
|
|
|
return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
|
|
|
|
}
|
|
|
|
static inline int _do_ecmpeq (uint32_t op1, uint32_t op2)
|
|
|
|
{
|
|
|
|
return op1 == op2 ? 1 : 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int _do_ecmpgts (int32_t op1, int32_t op2)
|
|
|
|
{
|
|
|
|
return op1 > op2 ? 1 : 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int _do_ecmpgtu (uint32_t op1, uint32_t op2)
|
|
|
|
{
|
|
|
|
return op1 > op2 ? 1 : 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int _do_ecmplts (int32_t op1, int32_t op2)
|
|
|
|
{
|
|
|
|
return op1 < op2 ? 1 : 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int _do_ecmpltu (uint32_t op1, uint32_t op2)
|
|
|
|
{
|
|
|
|
return op1 < op2 ? 1 : 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* evcmpeq */
|
|
|
|
DO_SPE_CMP(cmpeq);
|
|
|
|
/* evcmpgts */
|
|
|
|
DO_SPE_CMP(cmpgts);
|
|
|
|
/* evcmpgtu */
|
|
|
|
DO_SPE_CMP(cmpgtu);
|
|
|
|
/* evcmplts */
|
|
|
|
DO_SPE_CMP(cmplts);
|
|
|
|
/* evcmpltu */
|
|
|
|
DO_SPE_CMP(cmpltu);
|
|
|
|
|
|
|
|
/* Single precision floating-point conversions from/to integer */
|
|
|
|
static inline uint32_t _do_efscfsi (int32_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
uint32_t u;
|
|
|
|
float32 f;
|
|
|
|
} u;
|
|
|
|
|
|
|
|
u.f = int32_to_float32(val, &env->spe_status);
|
|
|
|
|
|
|
|
return u.u;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint32_t _do_efscfui (uint32_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
uint32_t u;
|
|
|
|
float32 f;
|
|
|
|
} u;
|
|
|
|
|
|
|
|
u.f = uint32_to_float32(val, &env->spe_status);
|
|
|
|
|
|
|
|
return u.u;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int32_t _do_efsctsi (uint32_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
int32_t u;
|
|
|
|
float32 f;
|
|
|
|
} u;
|
|
|
|
|
|
|
|
u.u = val;
|
|
|
|
/* NaN are not treated the same way IEEE 754 does */
|
|
|
|
if (unlikely(isnan(u.f)))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return float32_to_int32(u.f, &env->spe_status);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint32_t _do_efsctui (uint32_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
int32_t u;
|
|
|
|
float32 f;
|
|
|
|
} u;
|
|
|
|
|
|
|
|
u.u = val;
|
|
|
|
/* NaN are not treated the same way IEEE 754 does */
|
|
|
|
if (unlikely(isnan(u.f)))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return float32_to_uint32(u.f, &env->spe_status);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int32_t _do_efsctsiz (uint32_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
int32_t u;
|
|
|
|
float32 f;
|
|
|
|
} u;
|
|
|
|
|
|
|
|
u.u = val;
|
|
|
|
/* NaN are not treated the same way IEEE 754 does */
|
|
|
|
if (unlikely(isnan(u.f)))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return float32_to_int32_round_to_zero(u.f, &env->spe_status);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint32_t _do_efsctuiz (uint32_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
int32_t u;
|
|
|
|
float32 f;
|
|
|
|
} u;
|
|
|
|
|
|
|
|
u.u = val;
|
|
|
|
/* NaN are not treated the same way IEEE 754 does */
|
|
|
|
if (unlikely(isnan(u.f)))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efscfsi (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efscfsi(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efscfui (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efscfui(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efsctsi (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efsctsi(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efsctui (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efsctui(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efsctsiz (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efsctsiz(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efsctuiz (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efsctuiz(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Single precision floating-point conversion to/from fractional */
|
|
|
|
static inline uint32_t _do_efscfsf (uint32_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
uint32_t u;
|
|
|
|
float32 f;
|
|
|
|
} u;
|
|
|
|
float32 tmp;
|
|
|
|
|
|
|
|
u.f = int32_to_float32(val, &env->spe_status);
|
|
|
|
tmp = int64_to_float32(1ULL << 32, &env->spe_status);
|
|
|
|
u.f = float32_div(u.f, tmp, &env->spe_status);
|
|
|
|
|
|
|
|
return u.u;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint32_t _do_efscfuf (uint32_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
uint32_t u;
|
|
|
|
float32 f;
|
|
|
|
} u;
|
|
|
|
float32 tmp;
|
|
|
|
|
|
|
|
u.f = uint32_to_float32(val, &env->spe_status);
|
|
|
|
tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
|
|
|
|
u.f = float32_div(u.f, tmp, &env->spe_status);
|
|
|
|
|
|
|
|
return u.u;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int32_t _do_efsctsf (uint32_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
int32_t u;
|
|
|
|
float32 f;
|
|
|
|
} u;
|
|
|
|
float32 tmp;
|
|
|
|
|
|
|
|
u.u = val;
|
|
|
|
/* NaN are not treated the same way IEEE 754 does */
|
|
|
|
if (unlikely(isnan(u.f)))
|
|
|
|
return 0;
|
|
|
|
tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
|
|
|
|
u.f = float32_mul(u.f, tmp, &env->spe_status);
|
|
|
|
|
|
|
|
return float32_to_int32(u.f, &env->spe_status);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint32_t _do_efsctuf (uint32_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
int32_t u;
|
|
|
|
float32 f;
|
|
|
|
} u;
|
|
|
|
float32 tmp;
|
|
|
|
|
|
|
|
u.u = val;
|
|
|
|
/* NaN are not treated the same way IEEE 754 does */
|
|
|
|
if (unlikely(isnan(u.f)))
|
|
|
|
return 0;
|
|
|
|
tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
|
|
|
|
u.f = float32_mul(u.f, tmp, &env->spe_status);
|
|
|
|
|
|
|
|
return float32_to_uint32(u.f, &env->spe_status);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int32_t _do_efsctsfz (uint32_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
int32_t u;
|
|
|
|
float32 f;
|
|
|
|
} u;
|
|
|
|
float32 tmp;
|
|
|
|
|
|
|
|
u.u = val;
|
|
|
|
/* NaN are not treated the same way IEEE 754 does */
|
|
|
|
if (unlikely(isnan(u.f)))
|
|
|
|
return 0;
|
|
|
|
tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
|
|
|
|
u.f = float32_mul(u.f, tmp, &env->spe_status);
|
|
|
|
|
|
|
|
return float32_to_int32_round_to_zero(u.f, &env->spe_status);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint32_t _do_efsctufz (uint32_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
int32_t u;
|
|
|
|
float32 f;
|
|
|
|
} u;
|
|
|
|
float32 tmp;
|
|
|
|
|
|
|
|
u.u = val;
|
|
|
|
/* NaN are not treated the same way IEEE 754 does */
|
|
|
|
if (unlikely(isnan(u.f)))
|
|
|
|
return 0;
|
|
|
|
tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
|
|
|
|
u.f = float32_mul(u.f, tmp, &env->spe_status);
|
|
|
|
|
|
|
|
return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efscfsf (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efscfsf(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efscfuf (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efscfuf(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efsctsf (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efsctsf(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efsctuf (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efsctuf(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efsctsfz (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efsctsfz(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efsctufz (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efsctufz(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Double precision floating point helpers */
|
|
|
|
static inline int _do_efdcmplt (uint64_t op1, uint64_t op2)
|
|
|
|
{
|
|
|
|
/* XXX: TODO: test special values (NaN, infinites, ...) */
|
|
|
|
return _do_efdtstlt(op1, op2);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int _do_efdcmpgt (uint64_t op1, uint64_t op2)
|
|
|
|
{
|
|
|
|
/* XXX: TODO: test special values (NaN, infinites, ...) */
|
|
|
|
return _do_efdtstgt(op1, op2);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int _do_efdcmpeq (uint64_t op1, uint64_t op2)
|
|
|
|
{
|
|
|
|
/* XXX: TODO: test special values (NaN, infinites, ...) */
|
|
|
|
return _do_efdtsteq(op1, op2);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efdcmplt (void)
|
|
|
|
{
|
|
|
|
T0 = _do_efdcmplt(T0_64, T1_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efdcmpgt (void)
|
|
|
|
{
|
|
|
|
T0 = _do_efdcmpgt(T0_64, T1_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efdcmpeq (void)
|
|
|
|
{
|
|
|
|
T0 = _do_efdcmpeq(T0_64, T1_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Double precision floating-point conversion to/from integer */
|
|
|
|
static inline uint64_t _do_efdcfsi (int64_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
uint64_t u;
|
|
|
|
float64 f;
|
|
|
|
} u;
|
|
|
|
|
|
|
|
u.f = int64_to_float64(val, &env->spe_status);
|
|
|
|
|
|
|
|
return u.u;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint64_t _do_efdcfui (uint64_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
uint64_t u;
|
|
|
|
float64 f;
|
|
|
|
} u;
|
|
|
|
|
|
|
|
u.f = uint64_to_float64(val, &env->spe_status);
|
|
|
|
|
|
|
|
return u.u;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int64_t _do_efdctsi (uint64_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
int64_t u;
|
|
|
|
float64 f;
|
|
|
|
} u;
|
|
|
|
|
|
|
|
u.u = val;
|
|
|
|
/* NaN are not treated the same way IEEE 754 does */
|
|
|
|
if (unlikely(isnan(u.f)))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return float64_to_int64(u.f, &env->spe_status);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint64_t _do_efdctui (uint64_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
int64_t u;
|
|
|
|
float64 f;
|
|
|
|
} u;
|
|
|
|
|
|
|
|
u.u = val;
|
|
|
|
/* NaN are not treated the same way IEEE 754 does */
|
|
|
|
if (unlikely(isnan(u.f)))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return float64_to_uint64(u.f, &env->spe_status);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int64_t _do_efdctsiz (uint64_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
int64_t u;
|
|
|
|
float64 f;
|
|
|
|
} u;
|
|
|
|
|
|
|
|
u.u = val;
|
|
|
|
/* NaN are not treated the same way IEEE 754 does */
|
|
|
|
if (unlikely(isnan(u.f)))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return float64_to_int64_round_to_zero(u.f, &env->spe_status);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint64_t _do_efdctuiz (uint64_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
int64_t u;
|
|
|
|
float64 f;
|
|
|
|
} u;
|
|
|
|
|
|
|
|
u.u = val;
|
|
|
|
/* NaN are not treated the same way IEEE 754 does */
|
|
|
|
if (unlikely(isnan(u.f)))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return float64_to_uint64_round_to_zero(u.f, &env->spe_status);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efdcfsi (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efdcfsi(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efdcfui (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efdcfui(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efdctsi (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efdctsi(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efdctui (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efdctui(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efdctsiz (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efdctsiz(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efdctuiz (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efdctuiz(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Double precision floating-point conversion to/from fractional */
|
|
|
|
static inline uint64_t _do_efdcfsf (int64_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
uint64_t u;
|
|
|
|
float64 f;
|
|
|
|
} u;
|
|
|
|
float64 tmp;
|
|
|
|
|
|
|
|
u.f = int32_to_float64(val, &env->spe_status);
|
|
|
|
tmp = int64_to_float64(1ULL << 32, &env->spe_status);
|
|
|
|
u.f = float64_div(u.f, tmp, &env->spe_status);
|
|
|
|
|
|
|
|
return u.u;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint64_t _do_efdcfuf (uint64_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
uint64_t u;
|
|
|
|
float64 f;
|
|
|
|
} u;
|
|
|
|
float64 tmp;
|
|
|
|
|
|
|
|
u.f = uint32_to_float64(val, &env->spe_status);
|
|
|
|
tmp = int64_to_float64(1ULL << 32, &env->spe_status);
|
|
|
|
u.f = float64_div(u.f, tmp, &env->spe_status);
|
|
|
|
|
|
|
|
return u.u;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int64_t _do_efdctsf (uint64_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
int64_t u;
|
|
|
|
float64 f;
|
|
|
|
} u;
|
|
|
|
float64 tmp;
|
|
|
|
|
|
|
|
u.u = val;
|
|
|
|
/* NaN are not treated the same way IEEE 754 does */
|
|
|
|
if (unlikely(isnan(u.f)))
|
|
|
|
return 0;
|
|
|
|
tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
|
|
|
|
u.f = float64_mul(u.f, tmp, &env->spe_status);
|
|
|
|
|
|
|
|
return float64_to_int32(u.f, &env->spe_status);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint64_t _do_efdctuf (uint64_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
int64_t u;
|
|
|
|
float64 f;
|
|
|
|
} u;
|
|
|
|
float64 tmp;
|
|
|
|
|
|
|
|
u.u = val;
|
|
|
|
/* NaN are not treated the same way IEEE 754 does */
|
|
|
|
if (unlikely(isnan(u.f)))
|
|
|
|
return 0;
|
|
|
|
tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
|
|
|
|
u.f = float64_mul(u.f, tmp, &env->spe_status);
|
|
|
|
|
|
|
|
return float64_to_uint32(u.f, &env->spe_status);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int64_t _do_efdctsfz (uint64_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
int64_t u;
|
|
|
|
float64 f;
|
|
|
|
} u;
|
|
|
|
float64 tmp;
|
|
|
|
|
|
|
|
u.u = val;
|
|
|
|
/* NaN are not treated the same way IEEE 754 does */
|
|
|
|
if (unlikely(isnan(u.f)))
|
|
|
|
return 0;
|
|
|
|
tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
|
|
|
|
u.f = float64_mul(u.f, tmp, &env->spe_status);
|
|
|
|
|
|
|
|
return float64_to_int32_round_to_zero(u.f, &env->spe_status);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint64_t _do_efdctufz (uint64_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
int64_t u;
|
|
|
|
float64 f;
|
|
|
|
} u;
|
|
|
|
float64 tmp;
|
|
|
|
|
|
|
|
u.u = val;
|
|
|
|
/* NaN are not treated the same way IEEE 754 does */
|
|
|
|
if (unlikely(isnan(u.f)))
|
|
|
|
return 0;
|
|
|
|
tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
|
|
|
|
u.f = float64_mul(u.f, tmp, &env->spe_status);
|
|
|
|
|
|
|
|
return float64_to_uint32_round_to_zero(u.f, &env->spe_status);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efdcfsf (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efdcfsf(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efdcfuf (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efdcfuf(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efdctsf (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efdctsf(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efdctuf (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efdctuf(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efdctsfz (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efdctsfz(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efdctufz (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efdctufz(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Floating point conversion between single and double precision */
|
|
|
|
static inline uint32_t _do_efscfd (uint64_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
uint64_t u;
|
|
|
|
float64 f;
|
|
|
|
} u1;
|
|
|
|
union {
|
|
|
|
uint32_t u;
|
|
|
|
float32 f;
|
|
|
|
} u2;
|
|
|
|
|
|
|
|
u1.u = val;
|
|
|
|
u2.f = float64_to_float32(u1.f, &env->spe_status);
|
|
|
|
|
|
|
|
return u2.u;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint64_t _do_efdcfs (uint32_t val)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
uint64_t u;
|
|
|
|
float64 f;
|
|
|
|
} u2;
|
|
|
|
union {
|
|
|
|
uint32_t u;
|
|
|
|
float32 f;
|
|
|
|
} u1;
|
|
|
|
|
|
|
|
u1.u = val;
|
|
|
|
u2.f = float32_to_float64(u1.f, &env->spe_status);
|
|
|
|
|
|
|
|
return u2.u;
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efscfd (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efscfd(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efdcfs (void)
|
|
|
|
{
|
|
|
|
T0_64 = _do_efdcfs(T0_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Single precision fixed-point vector arithmetic */
|
|
|
|
/* evfsabs */
|
|
|
|
DO_SPE_OP1(fsabs);
|
|
|
|
/* evfsnabs */
|
|
|
|
DO_SPE_OP1(fsnabs);
|
|
|
|
/* evfsneg */
|
|
|
|
DO_SPE_OP1(fsneg);
|
|
|
|
/* evfsadd */
|
|
|
|
DO_SPE_OP2(fsadd);
|
|
|
|
/* evfssub */
|
|
|
|
DO_SPE_OP2(fssub);
|
|
|
|
/* evfsmul */
|
|
|
|
DO_SPE_OP2(fsmul);
|
|
|
|
/* evfsdiv */
|
|
|
|
DO_SPE_OP2(fsdiv);
|
|
|
|
|
|
|
|
/* Single-precision floating-point comparisons */
|
|
|
|
static inline int _do_efscmplt (uint32_t op1, uint32_t op2)
|
|
|
|
{
|
|
|
|
/* XXX: TODO: test special values (NaN, infinites, ...) */
|
|
|
|
return _do_efststlt(op1, op2);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int _do_efscmpgt (uint32_t op1, uint32_t op2)
|
|
|
|
{
|
|
|
|
/* XXX: TODO: test special values (NaN, infinites, ...) */
|
|
|
|
return _do_efststgt(op1, op2);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int _do_efscmpeq (uint32_t op1, uint32_t op2)
|
|
|
|
{
|
|
|
|
/* XXX: TODO: test special values (NaN, infinites, ...) */
|
|
|
|
return _do_efststeq(op1, op2);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efscmplt (void)
|
|
|
|
{
|
|
|
|
T0 = _do_efscmplt(T0_64, T1_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efscmpgt (void)
|
|
|
|
{
|
|
|
|
T0 = _do_efscmpgt(T0_64, T1_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_efscmpeq (void)
|
|
|
|
{
|
|
|
|
T0 = _do_efscmpeq(T0_64, T1_64);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Single-precision floating-point vector comparisons */
|
|
|
|
/* evfscmplt */
|
|
|
|
DO_SPE_CMP(fscmplt);
|
|
|
|
/* evfscmpgt */
|
|
|
|
DO_SPE_CMP(fscmpgt);
|
|
|
|
/* evfscmpeq */
|
|
|
|
DO_SPE_CMP(fscmpeq);
|
|
|
|
/* evfststlt */
|
|
|
|
DO_SPE_CMP(fststlt);
|
|
|
|
/* evfststgt */
|
|
|
|
DO_SPE_CMP(fststgt);
|
|
|
|
/* evfststeq */
|
|
|
|
DO_SPE_CMP(fststeq);
|
|
|
|
|
|
|
|
/* Single-precision floating-point vector conversions */
|
|
|
|
/* evfscfsi */
|
|
|
|
DO_SPE_OP1(fscfsi);
|
|
|
|
/* evfscfui */
|
|
|
|
DO_SPE_OP1(fscfui);
|
|
|
|
/* evfscfuf */
|
|
|
|
DO_SPE_OP1(fscfuf);
|
|
|
|
/* evfscfsf */
|
|
|
|
DO_SPE_OP1(fscfsf);
|
|
|
|
/* evfsctsi */
|
|
|
|
DO_SPE_OP1(fsctsi);
|
|
|
|
/* evfsctui */
|
|
|
|
DO_SPE_OP1(fsctui);
|
|
|
|
/* evfsctsiz */
|
|
|
|
DO_SPE_OP1(fsctsiz);
|
|
|
|
/* evfsctuiz */
|
|
|
|
DO_SPE_OP1(fsctuiz);
|
|
|
|
/* evfsctsf */
|
|
|
|
DO_SPE_OP1(fsctsf);
|
|
|
|
/* evfsctuf */
|
|
|
|
DO_SPE_OP1(fsctuf);
|
2007-04-24 08:50:21 +02:00
|
|
|
#endif /* defined(TARGET_PPCEMB) */
|
2007-03-20 23:11:31 +01:00
|
|
|
|
2005-07-05 00:17:05 +02:00
|
|
|
/*****************************************************************************/
|
|
|
|
/* Softmmu support */
|
|
|
|
#if !defined (CONFIG_USER_ONLY)
|
|
|
|
|
|
|
|
#define MMUSUFFIX _mmu
|
|
|
|
#define GETPC() (__builtin_return_address(0))
|
|
|
|
|
|
|
|
#define SHIFT 0
|
|
|
|
#include "softmmu_template.h"
|
|
|
|
|
|
|
|
#define SHIFT 1
|
|
|
|
#include "softmmu_template.h"
|
|
|
|
|
|
|
|
#define SHIFT 2
|
|
|
|
#include "softmmu_template.h"
|
|
|
|
|
|
|
|
#define SHIFT 3
|
|
|
|
#include "softmmu_template.h"
|
|
|
|
|
|
|
|
/* try to fill the TLB and return an exception if error. If retaddr is
|
|
|
|
NULL, it means that the function was called in C code (i.e. not
|
|
|
|
from generated code or from helper.c) */
|
|
|
|
/* XXX: fix it to restore all registers */
|
|
|
|
void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
|
|
|
|
{
|
|
|
|
TranslationBlock *tb;
|
|
|
|
CPUState *saved_env;
|
|
|
|
target_phys_addr_t pc;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* XXX: hack to restore env in all cases, even if not called from
|
|
|
|
generated code */
|
|
|
|
saved_env = env;
|
|
|
|
env = cpu_single_env;
|
|
|
|
ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
|
2007-03-07 09:32:30 +01:00
|
|
|
if (unlikely(ret != 0)) {
|
2005-07-05 00:17:05 +02:00
|
|
|
if (likely(retaddr)) {
|
|
|
|
/* now we have a real cpu fault */
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
pc = (target_phys_addr_t)(unsigned long)retaddr;
|
2005-07-05 00:17:05 +02:00
|
|
|
tb = tb_find_pc(pc);
|
|
|
|
if (likely(tb)) {
|
|
|
|
/* the PC is inside the translated code. It means that we have
|
|
|
|
a virtual CPU fault */
|
|
|
|
cpu_restore_state(tb, env, pc, NULL);
|
2007-03-07 09:32:30 +01:00
|
|
|
}
|
2005-07-05 00:17:05 +02:00
|
|
|
}
|
|
|
|
do_raise_exception_err(env->exception_index, env->error_code);
|
|
|
|
}
|
|
|
|
env = saved_env;
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
/* TLB invalidation helpers */
|
|
|
|
void do_tlbia (void)
|
|
|
|
{
|
2007-04-16 10:56:52 +02:00
|
|
|
ppc_tlb_invalidate_all(env);
|
2007-03-07 09:32:30 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void do_tlbie (void)
|
|
|
|
{
|
2007-03-17 15:02:15 +01:00
|
|
|
T0 = (uint32_t)T0;
|
2007-03-07 09:32:30 +01:00
|
|
|
#if !defined(FLUSH_ALL_TLBS)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
/* XXX: Remove thoses tests */
|
|
|
|
if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx)) {
|
2007-03-07 09:32:30 +01:00
|
|
|
ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 0);
|
|
|
|
if (env->id_tlbs == 1)
|
|
|
|
ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 1);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
} else if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_4xx)) {
|
|
|
|
ppc4xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK,
|
|
|
|
env->spr[SPR_40x_PID]);
|
2007-03-07 09:32:30 +01:00
|
|
|
} else {
|
|
|
|
/* tlbie invalidate TLBs for all segments */
|
|
|
|
T0 &= TARGET_PAGE_MASK;
|
|
|
|
T0 &= ~((target_ulong)-1 << 28);
|
|
|
|
/* XXX: this case should be optimized,
|
|
|
|
* giving a mask to tlb_flush_page
|
|
|
|
*/
|
|
|
|
tlb_flush_page(env, T0 | (0x0 << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0x1 << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0x2 << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0x3 << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0x4 << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0x5 << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0x6 << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0x7 << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0x8 << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0x9 << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0xA << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0xB << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0xC << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0xD << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0xE << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0xF << 28));
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
do_tlbia();
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2007-03-17 15:02:15 +01:00
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
void do_tlbie_64 (void)
|
|
|
|
{
|
|
|
|
T0 = (uint64_t)T0;
|
|
|
|
#if !defined(FLUSH_ALL_TLBS)
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx)) {
|
2007-03-17 15:02:15 +01:00
|
|
|
ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 0);
|
|
|
|
if (env->id_tlbs == 1)
|
|
|
|
ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 1);
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
} else if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_4xx)) {
|
2007-03-17 15:02:15 +01:00
|
|
|
/* XXX: TODO */
|
|
|
|
#if 0
|
|
|
|
ppcbooke_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK,
|
|
|
|
env->spr[SPR_BOOKE_PID]);
|
|
|
|
#endif
|
|
|
|
} else {
|
|
|
|
/* tlbie invalidate TLBs for all segments
|
|
|
|
* As we have 2^36 segments, invalidate all qemu TLBs
|
|
|
|
*/
|
|
|
|
#if 0
|
|
|
|
T0 &= TARGET_PAGE_MASK;
|
|
|
|
T0 &= ~((target_ulong)-1 << 28);
|
|
|
|
/* XXX: this case should be optimized,
|
|
|
|
* giving a mask to tlb_flush_page
|
|
|
|
*/
|
|
|
|
tlb_flush_page(env, T0 | (0x0 << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0x1 << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0x2 << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0x3 << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0x4 << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0x5 << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0x6 << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0x7 << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0x8 << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0x9 << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0xA << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0xB << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0xC << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0xD << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0xE << 28));
|
|
|
|
tlb_flush_page(env, T0 | (0xF << 28));
|
|
|
|
#else
|
|
|
|
tlb_flush(env, 1);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
do_tlbia();
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#if defined(TARGET_PPC64)
|
|
|
|
void do_slbia (void)
|
|
|
|
{
|
|
|
|
/* XXX: TODO */
|
|
|
|
tlb_flush(env, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_slbie (void)
|
|
|
|
{
|
|
|
|
/* XXX: TODO */
|
|
|
|
tlb_flush(env, 1);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
/* Software driven TLBs management */
|
|
|
|
/* PowerPC 602/603 software TLB load instructions helpers */
|
|
|
|
void do_load_6xx_tlb (int is_code)
|
|
|
|
{
|
|
|
|
target_ulong RPN, CMP, EPN;
|
|
|
|
int way;
|
2007-03-17 15:02:15 +01:00
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
RPN = env->spr[SPR_RPA];
|
|
|
|
if (is_code) {
|
|
|
|
CMP = env->spr[SPR_ICMP];
|
|
|
|
EPN = env->spr[SPR_IMISS];
|
|
|
|
} else {
|
|
|
|
CMP = env->spr[SPR_DCMP];
|
|
|
|
EPN = env->spr[SPR_DMISS];
|
|
|
|
}
|
|
|
|
way = (env->spr[SPR_SRR1] >> 17) & 1;
|
|
|
|
#if defined (DEBUG_SOFTWARE_TLB)
|
|
|
|
if (loglevel != 0) {
|
|
|
|
fprintf(logfile, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
|
|
|
|
__func__, (unsigned long)T0, (unsigned long)EPN,
|
|
|
|
(unsigned long)CMP, (unsigned long)RPN, way);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
/* Store this TLB */
|
2007-03-17 15:02:15 +01:00
|
|
|
ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
|
|
|
|
way, is_code, CMP, RPN);
|
2007-03-07 09:32:30 +01:00
|
|
|
}
|
|
|
|
|
2007-03-31 13:33:48 +02:00
|
|
|
static target_ulong booke_tlb_to_page_size (int size)
|
|
|
|
{
|
|
|
|
return 1024 << (2 * size);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int booke_page_size_to_tlb (target_ulong page_size)
|
|
|
|
{
|
|
|
|
int size;
|
|
|
|
|
|
|
|
switch (page_size) {
|
|
|
|
case 0x00000400UL:
|
|
|
|
size = 0x0;
|
|
|
|
break;
|
|
|
|
case 0x00001000UL:
|
|
|
|
size = 0x1;
|
|
|
|
break;
|
|
|
|
case 0x00004000UL:
|
|
|
|
size = 0x2;
|
|
|
|
break;
|
|
|
|
case 0x00010000UL:
|
|
|
|
size = 0x3;
|
|
|
|
break;
|
|
|
|
case 0x00040000UL:
|
|
|
|
size = 0x4;
|
|
|
|
break;
|
|
|
|
case 0x00100000UL:
|
|
|
|
size = 0x5;
|
|
|
|
break;
|
|
|
|
case 0x00400000UL:
|
|
|
|
size = 0x6;
|
|
|
|
break;
|
|
|
|
case 0x01000000UL:
|
|
|
|
size = 0x7;
|
|
|
|
break;
|
|
|
|
case 0x04000000UL:
|
|
|
|
size = 0x8;
|
|
|
|
break;
|
|
|
|
case 0x10000000UL:
|
|
|
|
size = 0x9;
|
|
|
|
break;
|
|
|
|
case 0x40000000UL:
|
|
|
|
size = 0xA;
|
|
|
|
break;
|
|
|
|
#if defined (TARGET_PPC64)
|
|
|
|
case 0x000100000000ULL:
|
|
|
|
size = 0xB;
|
|
|
|
break;
|
|
|
|
case 0x000400000000ULL:
|
|
|
|
size = 0xC;
|
|
|
|
break;
|
|
|
|
case 0x001000000000ULL:
|
|
|
|
size = 0xD;
|
|
|
|
break;
|
|
|
|
case 0x004000000000ULL:
|
|
|
|
size = 0xE;
|
|
|
|
break;
|
|
|
|
case 0x010000000000ULL:
|
|
|
|
size = 0xF;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
default:
|
|
|
|
size = -1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return size;
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
/* Helpers for 4xx TLB management */
|
|
|
|
void do_4xx_tlbre_lo (void)
|
|
|
|
{
|
2007-03-31 13:33:48 +02:00
|
|
|
ppcemb_tlb_t *tlb;
|
|
|
|
int size;
|
2007-03-07 09:32:30 +01:00
|
|
|
|
|
|
|
T0 &= 0x3F;
|
2007-03-31 13:33:48 +02:00
|
|
|
tlb = &env->tlb[T0].tlbe;
|
|
|
|
T0 = tlb->EPN;
|
|
|
|
if (tlb->prot & PAGE_VALID)
|
|
|
|
T0 |= 0x400;
|
|
|
|
size = booke_page_size_to_tlb(tlb->size);
|
|
|
|
if (size < 0 || size > 0x7)
|
|
|
|
size = 1;
|
|
|
|
T0 |= size << 7;
|
|
|
|
env->spr[SPR_40x_PID] = tlb->PID;
|
2007-03-07 09:32:30 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void do_4xx_tlbre_hi (void)
|
|
|
|
{
|
2007-03-31 13:33:48 +02:00
|
|
|
ppcemb_tlb_t *tlb;
|
2007-03-07 09:32:30 +01:00
|
|
|
|
|
|
|
T0 &= 0x3F;
|
2007-03-31 13:33:48 +02:00
|
|
|
tlb = &env->tlb[T0].tlbe;
|
|
|
|
T0 = tlb->RPN;
|
|
|
|
if (tlb->prot & PAGE_EXEC)
|
|
|
|
T0 |= 0x200;
|
|
|
|
if (tlb->prot & PAGE_WRITE)
|
|
|
|
T0 |= 0x100;
|
2007-03-07 09:32:30 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void do_4xx_tlbsx (void)
|
|
|
|
{
|
2007-09-17 10:21:54 +02:00
|
|
|
T0 = ppcemb_tlb_search(env, T0, env->spr[SPR_40x_PID]);
|
2007-03-07 09:32:30 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void do_4xx_tlbsx_ (void)
|
|
|
|
{
|
2007-09-17 11:51:40 +02:00
|
|
|
int tmp = xer_so;
|
2007-03-07 09:32:30 +01:00
|
|
|
|
2007-09-17 10:21:54 +02:00
|
|
|
T0 = ppcemb_tlb_search(env, T0, env->spr[SPR_40x_PID]);
|
2007-03-07 09:32:30 +01:00
|
|
|
if (T0 != -1)
|
|
|
|
tmp |= 0x02;
|
|
|
|
env->crf[0] = tmp;
|
|
|
|
}
|
|
|
|
|
2007-04-16 11:21:46 +02:00
|
|
|
void do_4xx_tlbwe_hi (void)
|
2007-03-07 09:32:30 +01:00
|
|
|
{
|
2007-03-31 13:33:48 +02:00
|
|
|
ppcemb_tlb_t *tlb;
|
2007-03-07 09:32:30 +01:00
|
|
|
target_ulong page, end;
|
|
|
|
|
2007-04-16 11:21:46 +02:00
|
|
|
#if defined (DEBUG_SOFTWARE_TLB)
|
2007-04-24 09:36:03 +02:00
|
|
|
if (loglevel != 0) {
|
2007-04-16 11:21:46 +02:00
|
|
|
fprintf(logfile, "%s T0 " REGX " T1 " REGX "\n", __func__, T0, T1);
|
|
|
|
}
|
|
|
|
#endif
|
2007-03-07 09:32:30 +01:00
|
|
|
T0 &= 0x3F;
|
2007-03-31 13:33:48 +02:00
|
|
|
tlb = &env->tlb[T0].tlbe;
|
2007-03-07 09:32:30 +01:00
|
|
|
/* Invalidate previous TLB (if it's valid) */
|
|
|
|
if (tlb->prot & PAGE_VALID) {
|
|
|
|
end = tlb->EPN + tlb->size;
|
2007-04-16 11:21:46 +02:00
|
|
|
#if defined (DEBUG_SOFTWARE_TLB)
|
2007-04-24 09:36:03 +02:00
|
|
|
if (loglevel != 0) {
|
2007-04-16 11:21:46 +02:00
|
|
|
fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
|
|
|
|
" end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
|
|
|
|
}
|
|
|
|
#endif
|
2007-03-07 09:32:30 +01:00
|
|
|
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
|
|
|
|
tlb_flush_page(env, page);
|
|
|
|
}
|
2007-03-31 13:33:48 +02:00
|
|
|
tlb->size = booke_tlb_to_page_size((T1 >> 7) & 0x7);
|
2007-04-24 08:44:14 +02:00
|
|
|
/* We cannot handle TLB size < TARGET_PAGE_SIZE.
|
|
|
|
* If this ever occurs, one should use the ppcemb target instead
|
|
|
|
* of the ppc or ppc64 one
|
|
|
|
*/
|
|
|
|
if ((T1 & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
|
2007-09-19 07:46:03 +02:00
|
|
|
cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
|
|
|
|
"are not supported (%d)\n",
|
2007-04-24 08:44:14 +02:00
|
|
|
tlb->size, TARGET_PAGE_SIZE, (int)((T1 >> 7) & 0x7));
|
|
|
|
}
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
tlb->EPN = T1 & ~(tlb->size - 1);
|
2007-04-16 11:21:46 +02:00
|
|
|
if (T1 & 0x40)
|
2007-03-07 09:32:30 +01:00
|
|
|
tlb->prot |= PAGE_VALID;
|
|
|
|
else
|
|
|
|
tlb->prot &= ~PAGE_VALID;
|
2007-04-24 08:44:14 +02:00
|
|
|
if (T1 & 0x20) {
|
|
|
|
/* XXX: TO BE FIXED */
|
|
|
|
cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
|
|
|
|
}
|
2007-04-16 11:21:46 +02:00
|
|
|
tlb->PID = env->spr[SPR_40x_PID]; /* PID */
|
2007-03-31 13:33:48 +02:00
|
|
|
tlb->attr = T1 & 0xFF;
|
2007-04-16 11:21:46 +02:00
|
|
|
#if defined (DEBUG_SOFTWARE_TLB)
|
2007-04-24 08:44:14 +02:00
|
|
|
if (loglevel != 0) {
|
|
|
|
fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
|
2007-04-16 11:21:46 +02:00
|
|
|
" size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
|
2007-09-16 23:08:06 +02:00
|
|
|
(int)T0, tlb->RPN, tlb->EPN, tlb->size,
|
2007-04-16 11:21:46 +02:00
|
|
|
tlb->prot & PAGE_READ ? 'r' : '-',
|
|
|
|
tlb->prot & PAGE_WRITE ? 'w' : '-',
|
|
|
|
tlb->prot & PAGE_EXEC ? 'x' : '-',
|
|
|
|
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
|
|
|
|
}
|
|
|
|
#endif
|
2007-03-07 09:32:30 +01:00
|
|
|
/* Invalidate new TLB (if valid) */
|
|
|
|
if (tlb->prot & PAGE_VALID) {
|
|
|
|
end = tlb->EPN + tlb->size;
|
2007-04-16 11:21:46 +02:00
|
|
|
#if defined (DEBUG_SOFTWARE_TLB)
|
2007-04-24 09:36:03 +02:00
|
|
|
if (loglevel != 0) {
|
2007-04-16 11:21:46 +02:00
|
|
|
fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
|
|
|
|
" end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
|
|
|
|
}
|
|
|
|
#endif
|
2007-03-07 09:32:30 +01:00
|
|
|
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
|
|
|
|
tlb_flush_page(env, page);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-04-16 11:21:46 +02:00
|
|
|
void do_4xx_tlbwe_lo (void)
|
2007-03-07 09:32:30 +01:00
|
|
|
{
|
2007-03-31 13:33:48 +02:00
|
|
|
ppcemb_tlb_t *tlb;
|
2007-03-07 09:32:30 +01:00
|
|
|
|
2007-04-16 11:21:46 +02:00
|
|
|
#if defined (DEBUG_SOFTWARE_TLB)
|
2007-04-24 09:36:03 +02:00
|
|
|
if (loglevel != 0) {
|
2007-04-16 11:21:46 +02:00
|
|
|
fprintf(logfile, "%s T0 " REGX " T1 " REGX "\n", __func__, T0, T1);
|
|
|
|
}
|
|
|
|
#endif
|
2007-03-07 09:32:30 +01:00
|
|
|
T0 &= 0x3F;
|
2007-03-31 13:33:48 +02:00
|
|
|
tlb = &env->tlb[T0].tlbe;
|
2007-03-07 09:32:30 +01:00
|
|
|
tlb->RPN = T1 & 0xFFFFFC00;
|
|
|
|
tlb->prot = PAGE_READ;
|
|
|
|
if (T1 & 0x200)
|
|
|
|
tlb->prot |= PAGE_EXEC;
|
|
|
|
if (T1 & 0x100)
|
|
|
|
tlb->prot |= PAGE_WRITE;
|
2007-04-16 11:21:46 +02:00
|
|
|
#if defined (DEBUG_SOFTWARE_TLB)
|
2007-04-24 09:36:03 +02:00
|
|
|
if (loglevel != 0) {
|
|
|
|
fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
|
2007-04-16 11:21:46 +02:00
|
|
|
" size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
|
2007-09-16 23:08:06 +02:00
|
|
|
(int)T0, tlb->RPN, tlb->EPN, tlb->size,
|
2007-04-16 11:21:46 +02:00
|
|
|
tlb->prot & PAGE_READ ? 'r' : '-',
|
|
|
|
tlb->prot & PAGE_WRITE ? 'w' : '-',
|
|
|
|
tlb->prot & PAGE_EXEC ? 'x' : '-',
|
|
|
|
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
|
|
|
|
}
|
|
|
|
#endif
|
2007-03-07 09:32:30 +01:00
|
|
|
}
|
2007-09-19 07:44:04 +02:00
|
|
|
|
2007-09-21 07:28:33 +02:00
|
|
|
/* PowerPC 440 TLB management */
|
|
|
|
void do_440_tlbwe (int word)
|
2007-09-19 07:44:04 +02:00
|
|
|
{
|
|
|
|
ppcemb_tlb_t *tlb;
|
2007-09-21 07:28:33 +02:00
|
|
|
target_ulong EPN, RPN, size;
|
2007-09-19 07:44:04 +02:00
|
|
|
int do_flush_tlbs;
|
|
|
|
|
|
|
|
#if defined (DEBUG_SOFTWARE_TLB)
|
|
|
|
if (loglevel != 0) {
|
2007-09-21 07:28:33 +02:00
|
|
|
fprintf(logfile, "%s word %d T0 " REGX " T1 " REGX "\n",
|
|
|
|
__func__, word, T0, T1);
|
2007-09-19 07:44:04 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
do_flush_tlbs = 0;
|
|
|
|
T0 &= 0x3F;
|
|
|
|
tlb = &env->tlb[T0].tlbe;
|
2007-09-21 07:28:33 +02:00
|
|
|
switch (word) {
|
|
|
|
default:
|
|
|
|
/* Just here to please gcc */
|
|
|
|
case 0:
|
|
|
|
EPN = T1 & 0xFFFFFC00;
|
|
|
|
if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
|
2007-09-19 07:44:04 +02:00
|
|
|
do_flush_tlbs = 1;
|
2007-09-21 07:28:33 +02:00
|
|
|
tlb->EPN = EPN;
|
|
|
|
size = booke_tlb_to_page_size((T1 >> 4) & 0xF);
|
|
|
|
if ((tlb->prot & PAGE_VALID) && tlb->size < size)
|
|
|
|
do_flush_tlbs = 1;
|
|
|
|
tlb->size = size;
|
|
|
|
tlb->attr &= ~0x1;
|
|
|
|
tlb->attr |= (T1 >> 8) & 1;
|
|
|
|
if (T1 & 0x200) {
|
|
|
|
tlb->prot |= PAGE_VALID;
|
|
|
|
} else {
|
|
|
|
if (tlb->prot & PAGE_VALID) {
|
|
|
|
tlb->prot &= ~PAGE_VALID;
|
|
|
|
do_flush_tlbs = 1;
|
|
|
|
}
|
2007-09-19 07:44:04 +02:00
|
|
|
}
|
2007-09-21 07:28:33 +02:00
|
|
|
tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
|
|
|
|
if (do_flush_tlbs)
|
|
|
|
tlb_flush(env, 1);
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
RPN = T1 & 0xFFFFFC0F;
|
|
|
|
if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
|
|
|
|
tlb_flush(env, 1);
|
|
|
|
tlb->RPN = RPN;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
tlb->attr = (tlb->attr & 0x1) | (T1 & 0x0000FF00);
|
|
|
|
tlb->prot = tlb->prot & PAGE_VALID;
|
|
|
|
if (T1 & 0x1)
|
|
|
|
tlb->prot |= PAGE_READ << 4;
|
|
|
|
if (T1 & 0x2)
|
|
|
|
tlb->prot |= PAGE_WRITE << 4;
|
|
|
|
if (T1 & 0x4)
|
|
|
|
tlb->prot |= PAGE_EXEC << 4;
|
|
|
|
if (T1 & 0x8)
|
|
|
|
tlb->prot |= PAGE_READ;
|
|
|
|
if (T1 & 0x10)
|
|
|
|
tlb->prot |= PAGE_WRITE;
|
|
|
|
if (T1 & 0x20)
|
|
|
|
tlb->prot |= PAGE_EXEC;
|
|
|
|
break;
|
2007-09-19 07:44:04 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-09-21 07:28:33 +02:00
|
|
|
void do_440_tlbsx (void)
|
2007-09-19 07:44:04 +02:00
|
|
|
{
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
T0 = ppcemb_tlb_search(env, T0, env->spr[SPR_440_MMUCR] & 0xFF);
|
2007-09-19 07:44:04 +02:00
|
|
|
}
|
|
|
|
|
2007-09-21 07:28:33 +02:00
|
|
|
void do_440_tlbsx_ (void)
|
2007-09-19 07:44:04 +02:00
|
|
|
{
|
|
|
|
int tmp = xer_so;
|
|
|
|
|
Great rework and cleanups to ease PowerPC implementations definitions.
* cleanup cpu.h, removing definitions used only in translate.c/translate_init.c
* add new flags to define instructions sets more precisely
* various changes in MMU models definitions
* add definitions for PowerPC 440/460 support (insns and SPRs).
* add definitions for PowerPC 401/403 and 620 input pins model
* Fix definitions for most PowerPC 401, 403, 405, 440, 601, 602, 603 and 7x0
* Preliminary support for PowerPC 74xx (aka G4) without altivec.
* Code provision for other PowerPC support (7x5, 970, ...).
* New SPR and PVR defined, from PowerPC 2.04 specification and other sources
* Misc code bugs, error messages and styles fixes.
* Update status files for PowerPC cores support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3244 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 01:54:22 +02:00
|
|
|
T0 = ppcemb_tlb_search(env, T0, env->spr[SPR_440_MMUCR] & 0xFF);
|
2007-09-19 07:44:04 +02:00
|
|
|
if (T0 != -1)
|
|
|
|
tmp |= 0x02;
|
|
|
|
env->crf[0] = tmp;
|
|
|
|
}
|
|
|
|
|
2007-09-21 07:28:33 +02:00
|
|
|
void do_440_tlbre (int word)
|
2007-09-19 07:44:04 +02:00
|
|
|
{
|
|
|
|
ppcemb_tlb_t *tlb;
|
|
|
|
int size;
|
|
|
|
|
|
|
|
T0 &= 0x3F;
|
|
|
|
tlb = &env->tlb[T0].tlbe;
|
2007-09-21 07:28:33 +02:00
|
|
|
switch (word) {
|
|
|
|
default:
|
|
|
|
/* Just here to please gcc */
|
|
|
|
case 0:
|
|
|
|
T0 = tlb->EPN;
|
|
|
|
size = booke_page_size_to_tlb(tlb->size);
|
|
|
|
if (size < 0 || size > 0xF)
|
|
|
|
size = 1;
|
|
|
|
T0 |= size << 4;
|
|
|
|
if (tlb->attr & 0x1)
|
|
|
|
T0 |= 0x100;
|
|
|
|
if (tlb->prot & PAGE_VALID)
|
|
|
|
T0 |= 0x200;
|
|
|
|
env->spr[SPR_440_MMUCR] &= ~0x000000FF;
|
|
|
|
env->spr[SPR_440_MMUCR] |= tlb->PID;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
T0 = tlb->RPN;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
T0 = tlb->attr & ~0x1;
|
|
|
|
if (tlb->prot & (PAGE_READ << 4))
|
|
|
|
T0 |= 0x1;
|
|
|
|
if (tlb->prot & (PAGE_WRITE << 4))
|
|
|
|
T0 |= 0x2;
|
|
|
|
if (tlb->prot & (PAGE_EXEC << 4))
|
|
|
|
T0 |= 0x4;
|
|
|
|
if (tlb->prot & PAGE_READ)
|
|
|
|
T0 |= 0x8;
|
|
|
|
if (tlb->prot & PAGE_WRITE)
|
|
|
|
T0 |= 0x10;
|
|
|
|
if (tlb->prot & PAGE_EXEC)
|
|
|
|
T0 |= 0x20;
|
|
|
|
break;
|
|
|
|
}
|
2007-09-19 07:44:04 +02:00
|
|
|
}
|
2007-03-07 09:32:30 +01:00
|
|
|
#endif /* !CONFIG_USER_ONLY */
|