2009-06-21 18:49:54 +02:00
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/*
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* MSI-X device support
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*
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* This module includes support for MSI-X in pci devices.
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*
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* Author: Michael S. Tsirkin <mst@redhat.com>
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*
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* Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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2012-01-13 17:44:23 +01:00
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*
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* Contributions after 2012-01-13 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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2009-06-21 18:49:54 +02:00
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*/
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2016-01-26 19:17:15 +01:00
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#include "qemu/osdep.h"
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2012-12-12 22:05:42 +01:00
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#include "hw/pci/msi.h"
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#include "hw/pci/msix.h"
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#include "hw/pci/pci.h"
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2016-01-13 15:59:09 +01:00
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#include "hw/xen/xen.h"
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2020-05-08 12:02:22 +02:00
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#include "sysemu/xen.h"
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2019-08-12 07:23:39 +02:00
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#include "migration/qemu-file-types.h"
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2019-08-12 07:23:45 +02:00
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#include "migration/vmstate.h"
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2012-12-17 18:20:00 +01:00
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#include "qemu/range.h"
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2017-01-17 07:18:48 +01:00
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#include "qapi/error.h"
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2017-05-09 08:00:43 +02:00
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#include "trace.h"
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2009-06-21 18:49:54 +02:00
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2009-11-25 11:18:00 +01:00
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/* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
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#define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
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2009-06-21 18:49:54 +02:00
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#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
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2009-11-25 11:19:32 +01:00
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#define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
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2009-06-21 18:49:54 +02:00
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2012-12-20 23:27:02 +01:00
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MSIMessage msix_get_message(PCIDevice *dev, unsigned vector)
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2012-05-17 15:32:29 +02:00
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{
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2012-06-14 20:16:37 +02:00
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uint8_t *table_entry = dev->msix_table + vector * PCI_MSIX_ENTRY_SIZE;
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2012-05-17 15:32:29 +02:00
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MSIMessage msg;
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msg.address = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
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msg.data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA);
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return msg;
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}
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2009-06-21 18:49:54 +02:00
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2012-07-19 02:35:07 +02:00
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/*
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* Special API for POWER to configure the vectors through
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* a side channel. Should never be used by devices.
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*/
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void msix_set_message(PCIDevice *dev, int vector, struct MSIMessage msg)
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{
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uint8_t *table_entry = dev->msix_table + vector * PCI_MSIX_ENTRY_SIZE;
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pci_set_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR, msg.address);
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pci_set_long(table_entry + PCI_MSIX_ENTRY_DATA, msg.data);
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table_entry[PCI_MSIX_ENTRY_VECTOR_CTRL] &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
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}
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2009-06-21 18:49:54 +02:00
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static uint8_t msix_pending_mask(int vector)
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{
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return 1 << (vector % 8);
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}
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static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
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{
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2012-06-14 20:16:37 +02:00
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return dev->msix_pba + vector / 8;
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2009-06-21 18:49:54 +02:00
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}
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static int msix_is_pending(PCIDevice *dev, int vector)
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{
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return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
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}
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2012-12-18 12:54:32 +01:00
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void msix_set_pending(PCIDevice *dev, unsigned int vector)
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2009-06-21 18:49:54 +02:00
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{
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*msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
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}
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2016-06-01 10:23:31 +02:00
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void msix_clr_pending(PCIDevice *dev, int vector)
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2009-06-21 18:49:54 +02:00
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{
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*msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
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}
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2012-12-18 12:54:32 +01:00
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static bool msix_vector_masked(PCIDevice *dev, unsigned int vector, bool fmask)
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2009-06-21 18:49:54 +02:00
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{
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2016-01-13 15:59:09 +01:00
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unsigned offset = vector * PCI_MSIX_ENTRY_SIZE;
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2016-02-13 19:50:50 +01:00
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uint8_t *data = &dev->msix_table[offset + PCI_MSIX_ENTRY_DATA];
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2016-01-13 15:59:09 +01:00
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/* MSIs on Xen can be remapped into pirqs. In those cases, masking
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* and unmasking go through the PV evtchn path. */
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2016-02-13 19:50:50 +01:00
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if (xen_enabled() && xen_is_pirq_msi(pci_get_long(data))) {
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2016-01-13 15:59:09 +01:00
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return false;
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}
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return fmask || dev->msix_table[offset + PCI_MSIX_ENTRY_VECTOR_CTRL] &
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PCI_MSIX_ENTRY_CTRL_MASKBIT;
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2009-11-25 11:19:32 +01:00
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}
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2012-12-18 12:54:32 +01:00
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bool msix_is_masked(PCIDevice *dev, unsigned int vector)
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2009-11-25 11:19:32 +01:00
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{
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2011-11-21 17:57:50 +01:00
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return msix_vector_masked(dev, vector, dev->msix_function_masked);
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}
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2012-05-17 15:32:31 +02:00
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static void msix_fire_vector_notifier(PCIDevice *dev,
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unsigned int vector, bool is_masked)
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{
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MSIMessage msg;
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int ret;
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if (!dev->msix_vector_use_notifier) {
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return;
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}
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if (is_masked) {
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dev->msix_vector_release_notifier(dev, vector);
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} else {
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msg = msix_get_message(dev, vector);
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ret = dev->msix_vector_use_notifier(dev, vector, msg);
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assert(ret >= 0);
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}
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}
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2011-11-21 17:57:50 +01:00
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static void msix_handle_mask_update(PCIDevice *dev, int vector, bool was_masked)
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{
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bool is_masked = msix_is_masked(dev, vector);
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2012-05-17 15:32:31 +02:00
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2011-11-21 17:57:50 +01:00
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if (is_masked == was_masked) {
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return;
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}
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2012-05-17 15:32:31 +02:00
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msix_fire_vector_notifier(dev, vector, is_masked);
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2011-11-21 17:57:50 +01:00
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if (!is_masked && msix_is_pending(dev, vector)) {
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2009-11-25 11:19:32 +01:00
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msix_clr_pending(dev, vector);
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msix_notify(dev, vector);
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}
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}
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2017-05-09 08:00:43 +02:00
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static bool msix_masked(PCIDevice *dev)
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{
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return dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK;
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}
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2011-11-21 17:57:21 +01:00
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static void msix_update_function_masked(PCIDevice *dev)
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{
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2017-05-09 08:00:43 +02:00
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dev->msix_function_masked = !msix_enabled(dev) || msix_masked(dev);
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2011-11-21 17:57:21 +01:00
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}
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2009-11-25 11:19:32 +01:00
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/* Handle MSI-X capability config write. */
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void msix_write_config(PCIDevice *dev, uint32_t addr,
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uint32_t val, int len)
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{
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unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
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int vector;
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2011-11-21 17:57:21 +01:00
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bool was_masked;
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2009-11-25 11:19:32 +01:00
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2012-05-11 16:42:39 +02:00
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if (!msix_present(dev) || !range_covers_byte(addr, len, enable_pos)) {
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2009-11-25 11:19:32 +01:00
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return;
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}
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2017-05-09 08:00:43 +02:00
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trace_msix_write_config(dev->name, msix_enabled(dev), msix_masked(dev));
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2011-11-21 17:57:21 +01:00
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was_masked = dev->msix_function_masked;
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msix_update_function_masked(dev);
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2009-11-25 11:19:32 +01:00
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if (!msix_enabled(dev)) {
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return;
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}
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2011-01-20 08:21:40 +01:00
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pci_device_deassert_intx(dev);
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2009-11-25 11:19:32 +01:00
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2011-11-21 17:57:21 +01:00
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if (dev->msix_function_masked == was_masked) {
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2009-11-25 11:19:32 +01:00
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return;
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}
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for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
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2011-11-21 17:57:50 +01:00
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msix_handle_mask_update(dev, vector,
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msix_vector_masked(dev, vector, was_masked));
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2009-11-25 11:19:32 +01:00
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}
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2009-06-21 18:49:54 +02:00
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}
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2012-10-23 12:30:10 +02:00
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static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr,
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2012-06-14 20:16:37 +02:00
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unsigned size)
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2012-06-14 20:16:19 +02:00
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{
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PCIDevice *dev = opaque;
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2012-06-14 20:16:37 +02:00
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return pci_get_long(dev->msix_table + addr);
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2012-06-14 20:16:19 +02:00
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}
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2012-10-23 12:30:10 +02:00
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static void msix_table_mmio_write(void *opaque, hwaddr addr,
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2012-06-14 20:16:37 +02:00
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uint64_t val, unsigned size)
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2009-06-21 18:49:54 +02:00
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{
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PCIDevice *dev = opaque;
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2012-06-14 20:16:37 +02:00
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int vector = addr / PCI_MSIX_ENTRY_SIZE;
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2011-11-21 17:57:50 +01:00
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bool was_masked;
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2011-11-21 17:57:31 +01:00
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2011-11-21 17:57:50 +01:00
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was_masked = msix_is_masked(dev, vector);
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2012-06-14 20:16:37 +02:00
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pci_set_long(dev->msix_table + addr, val);
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2011-11-21 17:57:50 +01:00
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msix_handle_mask_update(dev, vector, was_masked);
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2009-06-21 18:49:54 +02:00
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}
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2012-06-14 20:16:37 +02:00
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static const MemoryRegionOps msix_table_mmio_ops = {
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.read = msix_table_mmio_read,
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.write = msix_table_mmio_write,
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2012-12-06 04:11:33 +01:00
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.endianness = DEVICE_LITTLE_ENDIAN,
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2012-06-14 20:16:37 +02:00
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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2012-10-23 12:30:10 +02:00
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static uint64_t msix_pba_mmio_read(void *opaque, hwaddr addr,
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2012-06-14 20:16:37 +02:00
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unsigned size)
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{
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PCIDevice *dev = opaque;
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2012-12-12 15:10:02 +01:00
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if (dev->msix_vector_poll_notifier) {
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unsigned vector_start = addr * 8;
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unsigned vector_end = MIN(addr + size * 8, dev->msix_entries_nr);
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dev->msix_vector_poll_notifier(dev, vector_start, vector_end);
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}
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2012-06-14 20:16:37 +02:00
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return pci_get_long(dev->msix_pba + addr);
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}
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msix: implement pba write (but read-only)
qpci_msix_pending() writes on pba region, causing qemu to SEGV:
Program received signal SIGSEGV, Segmentation fault.
[Switching to Thread 0x7ffff7fba8c0 (LWP 25882)]
0x0000000000000000 in ?? ()
(gdb) bt
#0 0x0000000000000000 in ()
#1 0x00005555556556c5 in memory_region_oldmmio_write_accessor (mr=0x5555579f3f80, addr=0, value=0x7fffffffbf68, size=4, shift=0, mask=4294967295, attrs=...) at /home/elmarco/src/qemu/memory.c:434
#2 0x00005555556558e1 in access_with_adjusted_size (addr=0, value=0x7fffffffbf68, size=4, access_size_min=1, access_size_max=4, access=0x55555565563e <memory_region_oldmmio_write_accessor>, mr=0x5555579f3f80, attrs=...) at /home/elmarco/src/qemu/memory.c:506
#3 0x00005555556581eb in memory_region_dispatch_write (mr=0x5555579f3f80, addr=0, data=0, size=4, attrs=...) at /home/elmarco/src/qemu/memory.c:1176
#4 0x000055555560b6f9 in address_space_rw (as=0x555555eff4e0 <address_space_memory>, addr=3759147008, attrs=..., buf=0x7fffffffc1b0 "", len=4, is_write=true) at /home/elmarco/src/qemu/exec.c:2439
#5 0x000055555560baa2 in cpu_physical_memory_rw (addr=3759147008, buf=0x7fffffffc1b0 "", len=4, is_write=1) at /home/elmarco/src/qemu/exec.c:2534
#6 0x000055555564c005 in cpu_physical_memory_write (addr=3759147008, buf=0x7fffffffc1b0, len=4) at /home/elmarco/src/qemu/include/exec/cpu-common.h:80
#7 0x000055555564cd9c in qtest_process_command (chr=0x55555642b890, words=0x5555578de4b0) at /home/elmarco/src/qemu/qtest.c:378
#8 0x000055555564db77 in qtest_process_inbuf (chr=0x55555642b890, inbuf=0x55555641b340) at /home/elmarco/src/qemu/qtest.c:569
#9 0x000055555564dc07 in qtest_read (opaque=0x55555642b890, buf=0x7fffffffc2e0 "writel 0xe0100800 0x0\n", size=22) at /home/elmarco/src/qemu/qtest.c:581
#10 0x000055555574ce3e in qemu_chr_be_write (s=0x55555642b890, buf=0x7fffffffc2e0 "writel 0xe0100800 0x0\n", len=22) at qemu-char.c:306
#11 0x0000555555751263 in tcp_chr_read (chan=0x55555642bcf0, cond=G_IO_IN, opaque=0x55555642b890) at qemu-char.c:2876
#12 0x00007ffff64c9a8a in g_main_context_dispatch (context=0x55555641c400) at gmain.c:3122
(without this patch, this can be reproduced with the ivshmem qtest)
Implement an empty mmio write to avoid the crash.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-26 14:25:29 +02:00
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static void msix_pba_mmio_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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}
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2012-06-14 20:16:37 +02:00
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static const MemoryRegionOps msix_pba_mmio_ops = {
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.read = msix_pba_mmio_read,
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msix: implement pba write (but read-only)
qpci_msix_pending() writes on pba region, causing qemu to SEGV:
Program received signal SIGSEGV, Segmentation fault.
[Switching to Thread 0x7ffff7fba8c0 (LWP 25882)]
0x0000000000000000 in ?? ()
(gdb) bt
#0 0x0000000000000000 in ()
#1 0x00005555556556c5 in memory_region_oldmmio_write_accessor (mr=0x5555579f3f80, addr=0, value=0x7fffffffbf68, size=4, shift=0, mask=4294967295, attrs=...) at /home/elmarco/src/qemu/memory.c:434
#2 0x00005555556558e1 in access_with_adjusted_size (addr=0, value=0x7fffffffbf68, size=4, access_size_min=1, access_size_max=4, access=0x55555565563e <memory_region_oldmmio_write_accessor>, mr=0x5555579f3f80, attrs=...) at /home/elmarco/src/qemu/memory.c:506
#3 0x00005555556581eb in memory_region_dispatch_write (mr=0x5555579f3f80, addr=0, data=0, size=4, attrs=...) at /home/elmarco/src/qemu/memory.c:1176
#4 0x000055555560b6f9 in address_space_rw (as=0x555555eff4e0 <address_space_memory>, addr=3759147008, attrs=..., buf=0x7fffffffc1b0 "", len=4, is_write=true) at /home/elmarco/src/qemu/exec.c:2439
#5 0x000055555560baa2 in cpu_physical_memory_rw (addr=3759147008, buf=0x7fffffffc1b0 "", len=4, is_write=1) at /home/elmarco/src/qemu/exec.c:2534
#6 0x000055555564c005 in cpu_physical_memory_write (addr=3759147008, buf=0x7fffffffc1b0, len=4) at /home/elmarco/src/qemu/include/exec/cpu-common.h:80
#7 0x000055555564cd9c in qtest_process_command (chr=0x55555642b890, words=0x5555578de4b0) at /home/elmarco/src/qemu/qtest.c:378
#8 0x000055555564db77 in qtest_process_inbuf (chr=0x55555642b890, inbuf=0x55555641b340) at /home/elmarco/src/qemu/qtest.c:569
#9 0x000055555564dc07 in qtest_read (opaque=0x55555642b890, buf=0x7fffffffc2e0 "writel 0xe0100800 0x0\n", size=22) at /home/elmarco/src/qemu/qtest.c:581
#10 0x000055555574ce3e in qemu_chr_be_write (s=0x55555642b890, buf=0x7fffffffc2e0 "writel 0xe0100800 0x0\n", len=22) at qemu-char.c:306
#11 0x0000555555751263 in tcp_chr_read (chan=0x55555642bcf0, cond=G_IO_IN, opaque=0x55555642b890) at qemu-char.c:2876
#12 0x00007ffff64c9a8a in g_main_context_dispatch (context=0x55555641c400) at gmain.c:3122
(without this patch, this can be reproduced with the ivshmem qtest)
Implement an empty mmio write to avoid the crash.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-26 14:25:29 +02:00
|
|
|
.write = msix_pba_mmio_write,
|
2012-12-06 04:11:33 +01:00
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
2011-08-08 15:09:26 +02:00
|
|
|
.valid = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
2009-06-21 18:49:54 +02:00
|
|
|
};
|
|
|
|
|
2009-11-25 10:41:48 +01:00
|
|
|
static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
|
|
|
|
{
|
|
|
|
int vector;
|
2012-05-17 15:32:30 +02:00
|
|
|
|
2009-11-25 10:41:48 +01:00
|
|
|
for (vector = 0; vector < nentries; ++vector) {
|
2011-06-09 09:39:56 +02:00
|
|
|
unsigned offset =
|
|
|
|
vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
|
2012-05-17 15:32:30 +02:00
|
|
|
bool was_masked = msix_is_masked(dev, vector);
|
|
|
|
|
2012-06-14 20:16:37 +02:00
|
|
|
dev->msix_table[offset] |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
|
2012-05-17 15:32:30 +02:00
|
|
|
msix_handle_mask_update(dev, vector, was_masked);
|
2009-11-25 10:41:48 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-01-17 07:18:48 +01:00
|
|
|
/*
|
|
|
|
* Make PCI device @dev MSI-X capable
|
|
|
|
* @nentries is the max number of MSI-X vectors that the device support.
|
|
|
|
* @table_bar is the MemoryRegion that MSI-X table structure resides.
|
|
|
|
* @table_bar_nr is number of base address register corresponding to @table_bar.
|
|
|
|
* @table_offset indicates the offset that the MSI-X table structure starts with
|
|
|
|
* in @table_bar.
|
|
|
|
* @pba_bar is the MemoryRegion that the Pending Bit Array structure resides.
|
|
|
|
* @pba_bar_nr is number of base address register corresponding to @pba_bar.
|
|
|
|
* @pba_offset indicates the offset that the Pending Bit Array structure
|
|
|
|
* starts with in @pba_bar.
|
|
|
|
* Non-zero @cap_pos puts capability MSI-X at that offset in PCI config space.
|
|
|
|
* @errp is for returning errors.
|
|
|
|
*
|
|
|
|
* Return 0 on success; set @errp and return -errno on error:
|
|
|
|
* -ENOTSUP means lacking msi support for a msi-capable platform.
|
|
|
|
* -EINVAL means capability overlap, happens when @cap_pos is non-zero,
|
|
|
|
* also means a programming error, except device assignment, which can check
|
|
|
|
* if a real HW is broken.
|
|
|
|
*/
|
2009-06-21 18:49:54 +02:00
|
|
|
int msix_init(struct PCIDevice *dev, unsigned short nentries,
|
2012-06-14 20:16:47 +02:00
|
|
|
MemoryRegion *table_bar, uint8_t table_bar_nr,
|
|
|
|
unsigned table_offset, MemoryRegion *pba_bar,
|
2017-01-17 07:18:48 +01:00
|
|
|
uint8_t pba_bar_nr, unsigned pba_offset, uint8_t cap_pos,
|
|
|
|
Error **errp)
|
2009-06-21 18:49:54 +02:00
|
|
|
{
|
2012-06-14 20:16:47 +02:00
|
|
|
int cap;
|
2012-06-14 20:16:37 +02:00
|
|
|
unsigned table_size, pba_size;
|
2012-06-14 20:16:47 +02:00
|
|
|
uint8_t *config;
|
2011-10-15 14:33:17 +02:00
|
|
|
|
2009-06-21 18:49:54 +02:00
|
|
|
/* Nothing to do if MSI is not supported by interrupt controller */
|
2016-03-04 10:24:28 +01:00
|
|
|
if (!msi_nonbroken) {
|
2017-01-17 07:18:48 +01:00
|
|
|
error_setg(errp, "MSI-X is not supported by interrupt controller");
|
2009-06-21 18:49:54 +02:00
|
|
|
return -ENOTSUP;
|
2011-10-15 14:33:17 +02:00
|
|
|
}
|
2012-06-14 20:16:47 +02:00
|
|
|
|
|
|
|
if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1) {
|
2017-01-17 07:18:48 +01:00
|
|
|
error_setg(errp, "The number of MSI-X vectors is invalid");
|
2009-06-21 18:49:54 +02:00
|
|
|
return -EINVAL;
|
2012-06-14 20:16:47 +02:00
|
|
|
}
|
2009-06-21 18:49:54 +02:00
|
|
|
|
2012-06-14 20:16:37 +02:00
|
|
|
table_size = nentries * PCI_MSIX_ENTRY_SIZE;
|
|
|
|
pba_size = QEMU_ALIGN_UP(nentries, 64) / 8;
|
|
|
|
|
2012-06-14 20:16:47 +02:00
|
|
|
/* Sanity test: table & pba don't overlap, fit within BARs, min aligned */
|
|
|
|
if ((table_bar_nr == pba_bar_nr &&
|
|
|
|
ranges_overlap(table_offset, table_size, pba_offset, pba_size)) ||
|
|
|
|
table_offset + table_size > memory_region_size(table_bar) ||
|
|
|
|
pba_offset + pba_size > memory_region_size(pba_bar) ||
|
|
|
|
(table_offset | pba_offset) & PCI_MSIX_FLAGS_BIRMASK) {
|
2017-01-17 07:18:48 +01:00
|
|
|
error_setg(errp, "table & pba overlap, or they don't fit in BARs,"
|
|
|
|
" or don't align");
|
2012-06-14 20:16:47 +02:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2017-06-27 08:16:51 +02:00
|
|
|
cap = pci_add_capability(dev, PCI_CAP_ID_MSIX,
|
2017-01-17 07:18:48 +01:00
|
|
|
cap_pos, MSIX_CAP_LENGTH, errp);
|
2012-06-14 20:16:47 +02:00
|
|
|
if (cap < 0) {
|
|
|
|
return cap;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev->msix_cap = cap;
|
|
|
|
dev->cap_present |= QEMU_PCI_CAP_MSIX;
|
|
|
|
config = dev->config + cap;
|
|
|
|
|
|
|
|
pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
|
|
|
|
dev->msix_entries_nr = nentries;
|
|
|
|
dev->msix_function_masked = true;
|
|
|
|
|
|
|
|
pci_set_long(config + PCI_MSIX_TABLE, table_offset | table_bar_nr);
|
|
|
|
pci_set_long(config + PCI_MSIX_PBA, pba_offset | pba_bar_nr);
|
|
|
|
|
|
|
|
/* Make flags bit writable. */
|
|
|
|
dev->wmask[cap + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
|
|
|
|
MSIX_MASKALL_MASK;
|
2009-06-21 18:49:54 +02:00
|
|
|
|
2012-06-14 20:16:37 +02:00
|
|
|
dev->msix_table = g_malloc0(table_size);
|
|
|
|
dev->msix_pba = g_malloc0(pba_size);
|
2012-06-14 20:16:47 +02:00
|
|
|
dev->msix_entry_used = g_malloc0(nentries * sizeof *dev->msix_entry_used);
|
|
|
|
|
2009-11-25 10:41:48 +01:00
|
|
|
msix_mask_all(dev, nentries);
|
2009-06-21 18:49:54 +02:00
|
|
|
|
2013-06-07 03:25:08 +02:00
|
|
|
memory_region_init_io(&dev->msix_table_mmio, OBJECT(dev), &msix_table_mmio_ops, dev,
|
2012-06-14 20:16:37 +02:00
|
|
|
"msix-table", table_size);
|
2012-06-14 20:16:47 +02:00
|
|
|
memory_region_add_subregion(table_bar, table_offset, &dev->msix_table_mmio);
|
2013-06-07 03:25:08 +02:00
|
|
|
memory_region_init_io(&dev->msix_pba_mmio, OBJECT(dev), &msix_pba_mmio_ops, dev,
|
2012-06-14 20:16:37 +02:00
|
|
|
"msix-pba", pba_size);
|
2012-06-14 20:16:47 +02:00
|
|
|
memory_region_add_subregion(pba_bar, pba_offset, &dev->msix_pba_mmio);
|
2009-06-21 18:49:54 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-06-14 20:15:51 +02:00
|
|
|
int msix_init_exclusive_bar(PCIDevice *dev, unsigned short nentries,
|
2017-01-17 07:18:48 +01:00
|
|
|
uint8_t bar_nr, Error **errp)
|
2012-06-14 20:15:51 +02:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
char *name;
|
2015-04-23 08:21:49 +02:00
|
|
|
uint32_t bar_size = 4096;
|
|
|
|
uint32_t bar_pba_offset = bar_size / 2;
|
2018-12-17 00:34:39 +01:00
|
|
|
uint32_t bar_pba_size = QEMU_ALIGN_UP(nentries, 64) / 8;
|
2012-06-14 20:15:51 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Migration compatibility dictates that this remains a 4k
|
|
|
|
* BAR with the vector table in the lower half and PBA in
|
2015-04-23 08:21:49 +02:00
|
|
|
* the upper half for nentries which is lower or equal to 128.
|
|
|
|
* No need to care about using more than 65 entries for legacy
|
|
|
|
* machine types who has at most 64 queues.
|
2012-06-14 20:15:51 +02:00
|
|
|
*/
|
2015-04-23 08:21:49 +02:00
|
|
|
if (nentries * PCI_MSIX_ENTRY_SIZE > bar_pba_offset) {
|
|
|
|
bar_pba_offset = nentries * PCI_MSIX_ENTRY_SIZE;
|
|
|
|
}
|
2012-06-14 20:15:51 +02:00
|
|
|
|
2015-04-23 08:21:49 +02:00
|
|
|
if (bar_pba_offset + bar_pba_size > 4096) {
|
|
|
|
bar_size = bar_pba_offset + bar_pba_size;
|
|
|
|
}
|
|
|
|
|
2015-07-24 14:33:07 +02:00
|
|
|
bar_size = pow2ceil(bar_size);
|
2012-06-14 20:15:51 +02:00
|
|
|
|
2012-08-13 13:05:43 +02:00
|
|
|
name = g_strdup_printf("%s-msix", dev->name);
|
2015-04-23 08:21:49 +02:00
|
|
|
memory_region_init(&dev->msix_exclusive_bar, OBJECT(dev), name, bar_size);
|
2012-08-13 13:05:43 +02:00
|
|
|
g_free(name);
|
2012-06-14 20:15:51 +02:00
|
|
|
|
|
|
|
ret = msix_init(dev, nentries, &dev->msix_exclusive_bar, bar_nr,
|
2015-04-23 08:21:49 +02:00
|
|
|
0, &dev->msix_exclusive_bar,
|
|
|
|
bar_nr, bar_pba_offset,
|
2017-01-17 07:18:48 +01:00
|
|
|
0, errp);
|
2012-06-14 20:15:51 +02:00
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
pci_register_bar(dev, bar_nr, PCI_BASE_ADDRESS_SPACE_MEMORY,
|
|
|
|
&dev->msix_exclusive_bar);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-11-25 11:24:14 +01:00
|
|
|
static void msix_free_irq_entries(PCIDevice *dev)
|
|
|
|
{
|
|
|
|
int vector;
|
|
|
|
|
|
|
|
for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
|
|
|
|
dev->msix_entry_used[vector] = 0;
|
|
|
|
msix_clr_pending(dev, vector);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-08-29 18:40:56 +02:00
|
|
|
static void msix_clear_all_vectors(PCIDevice *dev)
|
|
|
|
{
|
|
|
|
int vector;
|
|
|
|
|
|
|
|
for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
|
|
|
|
msix_clr_pending(dev, vector);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-06-21 18:49:54 +02:00
|
|
|
/* Clean up resources for the device. */
|
2012-06-14 20:16:57 +02:00
|
|
|
void msix_uninit(PCIDevice *dev, MemoryRegion *table_bar, MemoryRegion *pba_bar)
|
2009-06-21 18:49:54 +02:00
|
|
|
{
|
2012-06-04 16:53:48 +02:00
|
|
|
if (!msix_present(dev)) {
|
2012-06-14 20:16:57 +02:00
|
|
|
return;
|
2012-06-04 16:53:48 +02:00
|
|
|
}
|
2009-06-21 18:49:54 +02:00
|
|
|
pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
|
|
|
|
dev->msix_cap = 0;
|
|
|
|
msix_free_irq_entries(dev);
|
|
|
|
dev->msix_entries_nr = 0;
|
2012-06-14 20:16:47 +02:00
|
|
|
memory_region_del_subregion(pba_bar, &dev->msix_pba_mmio);
|
2012-06-14 20:16:37 +02:00
|
|
|
g_free(dev->msix_pba);
|
|
|
|
dev->msix_pba = NULL;
|
2012-06-14 20:16:47 +02:00
|
|
|
memory_region_del_subregion(table_bar, &dev->msix_table_mmio);
|
2012-06-14 20:16:37 +02:00
|
|
|
g_free(dev->msix_table);
|
|
|
|
dev->msix_table = NULL;
|
2011-08-21 05:09:37 +02:00
|
|
|
g_free(dev->msix_entry_used);
|
2009-06-21 18:49:54 +02:00
|
|
|
dev->msix_entry_used = NULL;
|
|
|
|
dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
|
|
|
|
}
|
|
|
|
|
2012-06-14 20:15:51 +02:00
|
|
|
void msix_uninit_exclusive_bar(PCIDevice *dev)
|
|
|
|
{
|
|
|
|
if (msix_present(dev)) {
|
2012-06-14 20:16:47 +02:00
|
|
|
msix_uninit(dev, &dev->msix_exclusive_bar, &dev->msix_exclusive_bar);
|
2012-06-14 20:15:51 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-06-21 18:49:54 +02:00
|
|
|
void msix_save(PCIDevice *dev, QEMUFile *f)
|
|
|
|
{
|
2009-07-01 15:28:00 +02:00
|
|
|
unsigned n = dev->msix_entries_nr;
|
|
|
|
|
2012-06-04 16:53:48 +02:00
|
|
|
if (!msix_present(dev)) {
|
2009-07-01 15:28:00 +02:00
|
|
|
return;
|
2009-07-05 14:58:52 +02:00
|
|
|
}
|
2009-07-01 15:28:00 +02:00
|
|
|
|
2012-06-14 20:16:37 +02:00
|
|
|
qemu_put_buffer(f, dev->msix_table, n * PCI_MSIX_ENTRY_SIZE);
|
2017-06-22 13:04:16 +02:00
|
|
|
qemu_put_buffer(f, dev->msix_pba, DIV_ROUND_UP(n, 8));
|
2009-06-21 18:49:54 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Should be called after restoring the config space. */
|
|
|
|
void msix_load(PCIDevice *dev, QEMUFile *f)
|
|
|
|
{
|
|
|
|
unsigned n = dev->msix_entries_nr;
|
2012-05-17 15:32:31 +02:00
|
|
|
unsigned int vector;
|
2009-06-21 18:49:54 +02:00
|
|
|
|
2012-06-04 16:53:48 +02:00
|
|
|
if (!msix_present(dev)) {
|
2009-06-21 18:49:54 +02:00
|
|
|
return;
|
2009-07-05 10:11:39 +02:00
|
|
|
}
|
2009-06-21 18:49:54 +02:00
|
|
|
|
2012-08-29 18:40:56 +02:00
|
|
|
msix_clear_all_vectors(dev);
|
2012-06-14 20:16:37 +02:00
|
|
|
qemu_get_buffer(f, dev->msix_table, n * PCI_MSIX_ENTRY_SIZE);
|
2017-06-22 13:04:16 +02:00
|
|
|
qemu_get_buffer(f, dev->msix_pba, DIV_ROUND_UP(n, 8));
|
2011-11-21 17:57:21 +01:00
|
|
|
msix_update_function_masked(dev);
|
2012-05-17 15:32:31 +02:00
|
|
|
|
|
|
|
for (vector = 0; vector < n; vector++) {
|
|
|
|
msix_handle_mask_update(dev, vector, true);
|
|
|
|
}
|
2009-06-21 18:49:54 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Does device support MSI-X? */
|
|
|
|
int msix_present(PCIDevice *dev)
|
|
|
|
{
|
|
|
|
return dev->cap_present & QEMU_PCI_CAP_MSIX;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Is MSI-X enabled? */
|
|
|
|
int msix_enabled(PCIDevice *dev)
|
|
|
|
{
|
|
|
|
return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
|
2009-11-25 11:18:00 +01:00
|
|
|
(dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
|
2009-06-21 18:49:54 +02:00
|
|
|
MSIX_ENABLE_MASK);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Send an MSI-X message */
|
|
|
|
void msix_notify(PCIDevice *dev, unsigned vector)
|
|
|
|
{
|
2012-05-17 15:32:29 +02:00
|
|
|
MSIMessage msg;
|
2009-06-21 18:49:54 +02:00
|
|
|
|
2017-01-17 07:18:46 +01:00
|
|
|
if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
|
2009-06-21 18:49:54 +02:00
|
|
|
return;
|
2017-01-17 07:18:46 +01:00
|
|
|
}
|
|
|
|
|
2009-06-21 18:49:54 +02:00
|
|
|
if (msix_is_masked(dev, vector)) {
|
|
|
|
msix_set_pending(dev, vector);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2012-05-17 15:32:29 +02:00
|
|
|
msg = msix_get_message(dev, vector);
|
|
|
|
|
2015-05-27 14:59:59 +02:00
|
|
|
msi_send_message(dev, msg);
|
2009-06-21 18:49:54 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void msix_reset(PCIDevice *dev)
|
|
|
|
{
|
2012-06-04 16:53:48 +02:00
|
|
|
if (!msix_present(dev)) {
|
2009-06-21 18:49:54 +02:00
|
|
|
return;
|
2012-06-04 16:53:48 +02:00
|
|
|
}
|
2012-08-29 18:40:56 +02:00
|
|
|
msix_clear_all_vectors(dev);
|
2009-11-25 11:18:00 +01:00
|
|
|
dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
|
2018-12-13 23:37:37 +01:00
|
|
|
~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
|
2012-06-14 20:16:37 +02:00
|
|
|
memset(dev->msix_table, 0, dev->msix_entries_nr * PCI_MSIX_ENTRY_SIZE);
|
|
|
|
memset(dev->msix_pba, 0, QEMU_ALIGN_UP(dev->msix_entries_nr, 64) / 8);
|
2009-11-25 10:41:48 +01:00
|
|
|
msix_mask_all(dev, dev->msix_entries_nr);
|
2009-06-21 18:49:54 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* PCI spec suggests that devices make it possible for software to configure
|
|
|
|
* less vectors than supported by the device, but does not specify a standard
|
|
|
|
* mechanism for devices to do so.
|
|
|
|
*
|
|
|
|
* We support this by asking devices to declare vectors software is going to
|
|
|
|
* actually use, and checking this on the notification path. Devices that
|
|
|
|
* don't want to follow the spec suggestion can declare all vectors as used. */
|
|
|
|
|
|
|
|
/* Mark vector as used. */
|
|
|
|
int msix_vector_use(PCIDevice *dev, unsigned vector)
|
|
|
|
{
|
2017-01-17 07:18:46 +01:00
|
|
|
if (vector >= dev->msix_entries_nr) {
|
2009-06-21 18:49:54 +02:00
|
|
|
return -EINVAL;
|
2017-01-17 07:18:46 +01:00
|
|
|
}
|
|
|
|
|
2009-06-21 18:49:54 +02:00
|
|
|
dev->msix_entry_used[vector]++;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Mark vector as unused. */
|
|
|
|
void msix_vector_unuse(PCIDevice *dev, unsigned vector)
|
|
|
|
{
|
2009-11-25 11:24:14 +01:00
|
|
|
if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (--dev->msix_entry_used[vector]) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
msix_clr_pending(dev, vector);
|
2009-06-21 18:49:54 +02:00
|
|
|
}
|
2009-11-24 15:44:15 +01:00
|
|
|
|
|
|
|
void msix_unuse_all_vectors(PCIDevice *dev)
|
|
|
|
{
|
2012-06-04 16:53:48 +02:00
|
|
|
if (!msix_present(dev)) {
|
2009-11-24 15:44:15 +01:00
|
|
|
return;
|
2012-06-04 16:53:48 +02:00
|
|
|
}
|
2009-11-24 15:44:15 +01:00
|
|
|
msix_free_irq_entries(dev);
|
|
|
|
}
|
2012-05-17 15:32:31 +02:00
|
|
|
|
2012-05-17 15:32:38 +02:00
|
|
|
unsigned int msix_nr_vectors_allocated(const PCIDevice *dev)
|
|
|
|
{
|
|
|
|
return dev->msix_entries_nr;
|
|
|
|
}
|
|
|
|
|
2012-05-17 15:32:31 +02:00
|
|
|
static int msix_set_notifier_for_vector(PCIDevice *dev, unsigned int vector)
|
|
|
|
{
|
|
|
|
MSIMessage msg;
|
|
|
|
|
|
|
|
if (msix_is_masked(dev, vector)) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
msg = msix_get_message(dev, vector);
|
|
|
|
return dev->msix_vector_use_notifier(dev, vector, msg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void msix_unset_notifier_for_vector(PCIDevice *dev, unsigned int vector)
|
|
|
|
{
|
|
|
|
if (msix_is_masked(dev, vector)) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
dev->msix_vector_release_notifier(dev, vector);
|
|
|
|
}
|
|
|
|
|
|
|
|
int msix_set_vector_notifiers(PCIDevice *dev,
|
|
|
|
MSIVectorUseNotifier use_notifier,
|
2012-12-12 15:10:02 +01:00
|
|
|
MSIVectorReleaseNotifier release_notifier,
|
|
|
|
MSIVectorPollNotifier poll_notifier)
|
2012-05-17 15:32:31 +02:00
|
|
|
{
|
|
|
|
int vector, ret;
|
|
|
|
|
|
|
|
assert(use_notifier && release_notifier);
|
|
|
|
|
|
|
|
dev->msix_vector_use_notifier = use_notifier;
|
|
|
|
dev->msix_vector_release_notifier = release_notifier;
|
2012-12-12 15:10:02 +01:00
|
|
|
dev->msix_vector_poll_notifier = poll_notifier;
|
2012-05-17 15:32:31 +02:00
|
|
|
|
|
|
|
if ((dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
|
|
|
|
(MSIX_ENABLE_MASK | MSIX_MASKALL_MASK)) == MSIX_ENABLE_MASK) {
|
|
|
|
for (vector = 0; vector < dev->msix_entries_nr; vector++) {
|
|
|
|
ret = msix_set_notifier_for_vector(dev, vector);
|
|
|
|
if (ret < 0) {
|
|
|
|
goto undo;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2012-12-12 15:10:02 +01:00
|
|
|
if (dev->msix_vector_poll_notifier) {
|
|
|
|
dev->msix_vector_poll_notifier(dev, 0, dev->msix_entries_nr);
|
|
|
|
}
|
2012-05-17 15:32:31 +02:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
undo:
|
|
|
|
while (--vector >= 0) {
|
|
|
|
msix_unset_notifier_for_vector(dev, vector);
|
|
|
|
}
|
|
|
|
dev->msix_vector_use_notifier = NULL;
|
|
|
|
dev->msix_vector_release_notifier = NULL;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
void msix_unset_vector_notifiers(PCIDevice *dev)
|
|
|
|
{
|
|
|
|
int vector;
|
|
|
|
|
|
|
|
assert(dev->msix_vector_use_notifier &&
|
|
|
|
dev->msix_vector_release_notifier);
|
|
|
|
|
|
|
|
if ((dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
|
|
|
|
(MSIX_ENABLE_MASK | MSIX_MASKALL_MASK)) == MSIX_ENABLE_MASK) {
|
|
|
|
for (vector = 0; vector < dev->msix_entries_nr; vector++) {
|
|
|
|
msix_unset_notifier_for_vector(dev, vector);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
dev->msix_vector_use_notifier = NULL;
|
|
|
|
dev->msix_vector_release_notifier = NULL;
|
2012-12-12 15:10:02 +01:00
|
|
|
dev->msix_vector_poll_notifier = NULL;
|
2012-05-17 15:32:31 +02:00
|
|
|
}
|
2013-05-07 15:16:58 +02:00
|
|
|
|
2017-01-19 20:00:50 +01:00
|
|
|
static int put_msix_state(QEMUFile *f, void *pv, size_t size,
|
2018-11-14 14:29:30 +01:00
|
|
|
const VMStateField *field, QJSON *vmdesc)
|
2013-05-07 15:16:58 +02:00
|
|
|
{
|
|
|
|
msix_save(pv, f);
|
2017-01-19 20:00:50 +01:00
|
|
|
|
|
|
|
return 0;
|
2013-05-07 15:16:58 +02:00
|
|
|
}
|
|
|
|
|
2017-01-19 20:00:50 +01:00
|
|
|
static int get_msix_state(QEMUFile *f, void *pv, size_t size,
|
2018-11-14 14:29:30 +01:00
|
|
|
const VMStateField *field)
|
2013-05-07 15:16:58 +02:00
|
|
|
{
|
|
|
|
msix_load(pv, f);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static VMStateInfo vmstate_info_msix = {
|
|
|
|
.name = "msix state",
|
|
|
|
.get = get_msix_state,
|
|
|
|
.put = put_msix_state,
|
|
|
|
};
|
|
|
|
|
|
|
|
const VMStateDescription vmstate_msix = {
|
|
|
|
.name = "msix",
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
{
|
|
|
|
.name = "msix",
|
|
|
|
.version_id = 0,
|
|
|
|
.field_exists = NULL,
|
|
|
|
.size = 0, /* ouch */
|
|
|
|
.info = &vmstate_info_msix,
|
|
|
|
.flags = VMS_SINGLE,
|
|
|
|
.offset = 0,
|
|
|
|
},
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|