2012-12-06 12:15:58 +01:00
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#ifndef HW_QXL_H
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2016-06-29 15:29:06 +02:00
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#define HW_QXL_H
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2012-12-06 12:15:58 +01:00
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2010-04-27 11:50:11 +02:00
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2013-02-04 15:40:22 +01:00
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#include "hw/pci/pci.h"
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2013-03-18 17:36:02 +01:00
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#include "vga_int.h"
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2012-12-17 18:20:00 +01:00
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#include "qemu/thread.h"
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2010-04-27 11:50:11 +02:00
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#include "ui/qemu-spice.h"
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#include "ui/spice-display.h"
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2020-09-03 22:43:22 +02:00
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#include "qom/object.h"
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2010-04-27 11:50:11 +02:00
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enum qxl_mode {
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QXL_MODE_UNDEFINED,
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QXL_MODE_VGA,
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QXL_MODE_COMPAT, /* spice 0.4.x */
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QXL_MODE_NATIVE,
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};
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2011-10-14 18:05:48 +02:00
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#ifndef QXL_VRAM64_RANGE_INDEX
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#define QXL_VRAM64_RANGE_INDEX 4
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#endif
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2011-07-20 11:20:58 +02:00
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#define QXL_UNDEFINED_IO UINT32_MAX
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2012-02-24 22:19:31 +01:00
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#define QXL_NUM_DIRTY_RECTS 64
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2013-09-11 13:14:25 +02:00
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#define QXL_PAGE_BITS 12
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#define QXL_PAGE_SIZE (1 << QXL_PAGE_BITS);
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2020-09-03 22:43:22 +02:00
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struct PCIQXLDevice {
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2010-04-27 11:50:11 +02:00
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PCIDevice pci;
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2014-04-29 15:38:39 +02:00
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PortioList vga_port_list;
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2010-04-27 11:50:11 +02:00
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SimpleSpiceDisplay ssd;
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int id;
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2018-10-12 13:45:40 +02:00
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bool have_vga;
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2010-04-27 11:50:11 +02:00
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uint32_t debug;
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uint32_t guestdebug;
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uint32_t cmdlog;
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2012-05-24 18:18:54 +02:00
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uint32_t guest_bug;
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2017-04-10 13:31:31 +02:00
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Error *migration_blocker;
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2012-05-24 18:18:54 +02:00
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2010-04-27 11:50:11 +02:00
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enum qxl_mode mode;
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uint32_t cmdflags;
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uint32_t revision;
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int32_t num_memslots;
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2011-07-20 11:20:58 +02:00
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uint32_t current_async;
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QemuMutex async_lock;
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2010-04-27 11:50:11 +02:00
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struct guest_slots {
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QXLMemSlot slot;
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2016-06-22 14:07:23 +02:00
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MemoryRegion *mr;
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uint64_t offset;
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2010-04-27 11:50:11 +02:00
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uint64_t size;
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uint64_t delta;
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uint32_t active;
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} guest_slots[NUM_MEMSLOTS];
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struct guest_primary {
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QXLSurfaceCreate surface;
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uint32_t commands;
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uint32_t resized;
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2011-10-21 15:59:07 +02:00
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int32_t qxl_stride;
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uint32_t abs_stride;
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2010-04-27 11:50:11 +02:00
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uint32_t bits_pp;
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uint32_t bytes_pp;
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2012-02-24 22:19:29 +01:00
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uint8_t *data;
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2010-04-27 11:50:11 +02:00
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} guest_primary;
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struct surfaces {
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2012-09-04 11:39:41 +02:00
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QXLPHYSICAL *cmds;
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2010-04-27 11:50:11 +02:00
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uint32_t count;
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uint32_t max;
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} guest_surfaces;
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QXLPHYSICAL guest_cursor;
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2012-08-22 10:16:25 +02:00
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QXLPHYSICAL guest_monitors_config;
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2018-09-19 12:30:57 +02:00
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uint32_t guest_head0_width;
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uint32_t guest_head0_height;
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2012-08-22 10:16:25 +02:00
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2011-07-20 11:20:53 +02:00
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QemuMutex track_lock;
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2010-04-27 11:50:11 +02:00
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/* thread signaling */
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2013-10-29 13:29:43 +01:00
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QEMUBH *update_irq;
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2010-04-27 11:50:11 +02:00
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/* ram pci bar */
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QXLRam *ram;
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VGACommonState vga;
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uint32_t num_free_res;
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QXLReleaseInfo *last_release;
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uint32_t last_release_offset;
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uint32_t oom_running;
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2012-06-10 17:05:06 +02:00
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uint32_t vgamem_size;
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2010-04-27 11:50:11 +02:00
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/* rom pci bar */
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QXLRom shadow_rom;
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QXLRom *rom;
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QXLModes *modes;
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uint32_t rom_size;
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2011-08-08 15:08:57 +02:00
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MemoryRegion rom_bar;
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2015-07-06 08:56:38 +02:00
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#if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
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uint16_t max_outputs;
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#endif
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2010-04-27 11:50:11 +02:00
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/* vram pci bar */
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2016-06-08 14:40:48 +02:00
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uint64_t vram_size;
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2011-08-08 15:08:57 +02:00
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MemoryRegion vram_bar;
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2016-06-08 14:40:48 +02:00
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uint64_t vram32_size;
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2011-10-14 18:05:48 +02:00
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MemoryRegion vram32_bar;
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2010-04-27 11:50:11 +02:00
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/* io bar */
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2011-08-08 15:08:57 +02:00
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MemoryRegion io_bar;
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2012-02-17 15:03:24 +01:00
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/* user-friendly properties (in megabytes) */
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uint32_t ram_size_mb;
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uint32_t vram_size_mb;
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2011-10-14 18:05:48 +02:00
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uint32_t vram32_size_mb;
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2012-06-10 17:05:06 +02:00
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uint32_t vgamem_size_mb;
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2017-04-21 11:22:34 +02:00
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uint32_t xres;
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uint32_t yres;
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2012-02-24 22:19:31 +01:00
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/* qxl_render_update state */
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int render_update_cookie_num;
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int num_dirty_rects;
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QXLRect dirty[QXL_NUM_DIRTY_RECTS];
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QEMUBH *update_area_bh;
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2020-09-03 22:43:22 +02:00
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};
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typedef struct PCIQXLDevice PCIQXLDevice;
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2010-04-27 11:50:11 +02:00
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2015-05-12 11:27:10 +02:00
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#define TYPE_PCI_QXL "pci-qxl"
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#define PCI_QXL(obj) OBJECT_CHECK(PCIQXLDevice, (obj), TYPE_PCI_QXL)
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2010-04-27 11:50:11 +02:00
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#define PANIC_ON(x) if ((x)) { \
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2017-11-08 23:56:31 +01:00
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printf("%s: PANIC %s failed\n", __func__, #x); \
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2011-07-20 11:20:55 +02:00
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abort(); \
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2010-04-27 11:50:11 +02:00
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}
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#define dprint(_qxl, _level, _fmt, ...) \
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do { \
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if (_qxl->debug >= _level) { \
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fprintf(stderr, "qxl-%d: ", _qxl->id); \
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fprintf(stderr, _fmt, ## __VA_ARGS__); \
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} \
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} while (0)
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2020-02-06 08:43:58 +01:00
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#define QXL_DEFAULT_REVISION (QXL_REVISION_STABLE_V12 + 1)
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2011-07-20 11:21:00 +02:00
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2010-04-27 11:50:11 +02:00
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/* qxl.c */
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void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL phys, int group_id);
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2012-05-24 11:38:12 +02:00
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void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
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GCC_FMT_ATTR(2, 3);
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2010-04-27 11:50:11 +02:00
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2011-07-20 11:20:52 +02:00
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void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
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struct QXLRect *area, struct QXLRect *dirty_rects,
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uint32_t num_dirty_rects,
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2011-07-20 11:20:58 +02:00
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uint32_t clear_dirty_region,
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2012-02-24 22:19:30 +01:00
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qxl_async_io async, QXLCookie *cookie);
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2011-07-20 11:20:52 +02:00
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void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
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uint32_t count);
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void qxl_spice_oom(PCIQXLDevice *qxl);
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void qxl_spice_reset_memslots(PCIQXLDevice *qxl);
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void qxl_spice_reset_image_cache(PCIQXLDevice *qxl);
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void qxl_spice_reset_cursor(PCIQXLDevice *qxl);
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2010-04-27 11:50:11 +02:00
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/* qxl-logger.c */
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2012-04-25 11:13:18 +02:00
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int qxl_log_cmd_cursor(PCIQXLDevice *qxl, QXLCursorCmd *cmd, int group_id);
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int qxl_log_command(PCIQXLDevice *qxl, const char *ring, QXLCommandExt *ext);
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2010-04-27 11:50:11 +02:00
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/* qxl-render.c */
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void qxl_render_resize(PCIQXLDevice *qxl);
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void qxl_render_update(PCIQXLDevice *qxl);
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2012-04-25 11:13:18 +02:00
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int qxl_render_cursor(PCIQXLDevice *qxl, QXLCommandExt *ext);
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2012-02-24 22:19:31 +01:00
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void qxl_render_update_area_done(PCIQXLDevice *qxl, QXLCookie *cookie);
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void qxl_render_update_area_bh(void *opaque);
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2012-12-06 12:15:58 +01:00
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#endif
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