2017-02-28 13:08:20 +01:00
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/*
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* Exynos4210 Clock Controller Emulation
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*
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* Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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2019-08-12 07:23:45 +02:00
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#include "migration/vmstate.h"
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2017-02-28 13:08:20 +01:00
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#include "qemu/log.h"
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2019-05-23 16:35:07 +02:00
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#include "qemu/module.h"
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2020-09-03 22:43:22 +02:00
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#include "qom/object.h"
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2017-02-28 13:08:20 +01:00
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#define TYPE_EXYNOS4210_CLK "exynos4210.clk"
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2020-09-03 22:43:22 +02:00
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typedef struct Exynos4210ClkState Exynos4210ClkState;
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2017-02-28 13:08:20 +01:00
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#define EXYNOS4210_CLK(obj) \
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OBJECT_CHECK(Exynos4210ClkState, (obj), TYPE_EXYNOS4210_CLK)
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#define CLK_PLL_LOCKED BIT(29)
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#define EXYNOS4210_CLK_REGS_MEM_SIZE 0x15104
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typedef struct Exynos4210Reg {
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const char *name; /* for debug only */
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uint32_t offset;
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uint32_t reset_value;
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} Exynos4210Reg;
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/* Clock controller register base: 0x10030000 */
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static const Exynos4210Reg exynos4210_clk_regs[] = {
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{"EPLL_LOCK", 0xc010, 0x00000fff},
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{"VPLL_LOCK", 0xc020, 0x00000fff},
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{"EPLL_CON0", 0xc110, 0x00300301 | CLK_PLL_LOCKED},
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{"EPLL_CON1", 0xc114, 0x00000000},
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{"VPLL_CON0", 0xc120, 0x00240201 | CLK_PLL_LOCKED},
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{"VPLL_CON1", 0xc124, 0x66010464},
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{"APLL_LOCK", 0x14000, 0x00000fff},
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{"MPLL_LOCK", 0x14004, 0x00000fff},
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{"APLL_CON0", 0x14100, 0x00c80601 | CLK_PLL_LOCKED},
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{"APLL_CON1", 0x14104, 0x0000001c},
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{"MPLL_CON0", 0x14108, 0x00c80601 | CLK_PLL_LOCKED},
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{"MPLL_CON1", 0x1410c, 0x0000001c},
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};
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#define EXYNOS4210_REGS_NUM ARRAY_SIZE(exynos4210_clk_regs)
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2020-09-03 22:43:22 +02:00
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struct Exynos4210ClkState {
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2017-02-28 13:08:20 +01:00
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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uint32_t reg[EXYNOS4210_REGS_NUM];
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2020-09-03 22:43:22 +02:00
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};
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2017-02-28 13:08:20 +01:00
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static uint64_t exynos4210_clk_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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const Exynos4210ClkState *s = (Exynos4210ClkState *)opaque;
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const Exynos4210Reg *regs = exynos4210_clk_regs;
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unsigned int i;
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for (i = 0; i < EXYNOS4210_REGS_NUM; i++) {
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if (regs->offset == offset) {
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return s->reg[i];
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}
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regs++;
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}
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qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read offset 0x%04x\n",
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__func__, (uint32_t)offset);
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return 0;
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}
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static void exynos4210_clk_write(void *opaque, hwaddr offset,
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uint64_t val, unsigned size)
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{
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Exynos4210ClkState *s = (Exynos4210ClkState *)opaque;
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const Exynos4210Reg *regs = exynos4210_clk_regs;
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unsigned int i;
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for (i = 0; i < EXYNOS4210_REGS_NUM; i++) {
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if (regs->offset == offset) {
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s->reg[i] = val;
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return;
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}
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regs++;
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}
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qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write offset 0x%04x\n",
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__func__, (uint32_t)offset);
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}
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static const MemoryRegionOps exynos4210_clk_ops = {
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.read = exynos4210_clk_read,
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.write = exynos4210_clk_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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.unaligned = false
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}
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};
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static void exynos4210_clk_reset(DeviceState *dev)
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{
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Exynos4210ClkState *s = EXYNOS4210_CLK(dev);
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unsigned int i;
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/* Set default values for registers */
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for (i = 0; i < EXYNOS4210_REGS_NUM; i++) {
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s->reg[i] = exynos4210_clk_regs[i].reset_value;
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}
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}
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static void exynos4210_clk_init(Object *obj)
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{
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Exynos4210ClkState *s = EXYNOS4210_CLK(obj);
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SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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/* memory mapping */
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memory_region_init_io(&s->iomem, obj, &exynos4210_clk_ops, s,
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TYPE_EXYNOS4210_CLK, EXYNOS4210_CLK_REGS_MEM_SIZE);
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sysbus_init_mmio(dev, &s->iomem);
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}
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static const VMStateDescription exynos4210_clk_vmstate = {
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.name = TYPE_EXYNOS4210_CLK,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(reg, Exynos4210ClkState, EXYNOS4210_REGS_NUM),
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VMSTATE_END_OF_LIST()
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}
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};
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static void exynos4210_clk_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = exynos4210_clk_reset;
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dc->vmsd = &exynos4210_clk_vmstate;
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}
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static const TypeInfo exynos4210_clk_info = {
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.name = TYPE_EXYNOS4210_CLK,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(Exynos4210ClkState),
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.instance_init = exynos4210_clk_init,
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.class_init = exynos4210_clk_class_init,
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};
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static void exynos4210_clk_register(void)
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{
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qemu_log_mask(LOG_GUEST_ERROR, "Clock init\n");
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type_register_static(&exynos4210_clk_info);
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}
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type_init(exynos4210_clk_register)
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